This mmio address is checked at probe-time, which makes this test
redundant. Let's just remove it.
Signed-off-by: Ezequiel Garcia <[email protected]>
---
drivers/dma/mv_xor.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
index 536dcb8..d00d58e 100644
--- a/drivers/dma/mv_xor.c
+++ b/drivers/dma/mv_xor.c
@@ -1076,10 +1076,6 @@ mv_xor_channel_add(struct mv_xor_device *xordev,
}
mv_chan->mmr_base = xordev->xor_base;
- if (!mv_chan->mmr_base) {
- ret = -ENOMEM;
- goto err_free_dma;
- }
tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long)
mv_chan);
--
1.8.1.5
Despite requesting two memory resources, called 'base' and 'high_base', the
driver uses explicitly only the former. The latter is being used implicitly
by addressing at offset +0x200, which in practice accesses high_base.
Instead of relying in such trick, let's define the registers with the
offset from high_base, and use high_base explicitly where appropriate.
Signed-off-by: Ezequiel Garcia <[email protected]>
---
drivers/dma/mv_xor.c | 3 ++-
drivers/dma/mv_xor.h | 25 +++++++++++++------------
2 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c
index d00d58e..c7da545 100644
--- a/drivers/dma/mv_xor.c
+++ b/drivers/dma/mv_xor.c
@@ -1076,6 +1076,7 @@ mv_xor_channel_add(struct mv_xor_device *xordev,
}
mv_chan->mmr_base = xordev->xor_base;
+ mv_chan->mmr_high_base = xordev->xor_high_base;
tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long)
mv_chan);
@@ -1134,7 +1135,7 @@ static void
mv_xor_conf_mbus_windows(struct mv_xor_device *xordev,
const struct mbus_dram_target_info *dram)
{
- void __iomem *base = xordev->xor_base;
+ void __iomem *base = xordev->xor_high_base;
u32 win_enable = 0;
int i;
diff --git a/drivers/dma/mv_xor.h b/drivers/dma/mv_xor.h
index 06b067f..d074922 100644
--- a/drivers/dma/mv_xor.h
+++ b/drivers/dma/mv_xor.h
@@ -34,13 +34,13 @@
#define XOR_OPERATION_MODE_MEMCPY 2
#define XOR_DESCRIPTOR_SWAP BIT(14)
-#define XOR_CURR_DESC(chan) (chan->mmr_base + 0x210 + (chan->idx * 4))
-#define XOR_NEXT_DESC(chan) (chan->mmr_base + 0x200 + (chan->idx * 4))
-#define XOR_BYTE_COUNT(chan) (chan->mmr_base + 0x220 + (chan->idx * 4))
-#define XOR_DEST_POINTER(chan) (chan->mmr_base + 0x2B0 + (chan->idx * 4))
-#define XOR_BLOCK_SIZE(chan) (chan->mmr_base + 0x2C0 + (chan->idx * 4))
-#define XOR_INIT_VALUE_LOW(chan) (chan->mmr_base + 0x2E0)
-#define XOR_INIT_VALUE_HIGH(chan) (chan->mmr_base + 0x2E4)
+#define XOR_CURR_DESC(chan) (chan->mmr_high_base + 0x10 + (chan->idx * 4))
+#define XOR_NEXT_DESC(chan) (chan->mmr_high_base + 0x00 + (chan->idx * 4))
+#define XOR_BYTE_COUNT(chan) (chan->mmr_high_base + 0x20 + (chan->idx * 4))
+#define XOR_DEST_POINTER(chan) (chan->mmr_high_base + 0xB0 + (chan->idx * 4))
+#define XOR_BLOCK_SIZE(chan) (chan->mmr_high_base + 0xC0 + (chan->idx * 4))
+#define XOR_INIT_VALUE_LOW(chan) (chan->mmr_high_base + 0xE0)
+#define XOR_INIT_VALUE_HIGH(chan) (chan->mmr_high_base + 0xE4)
#define XOR_CONFIG(chan) (chan->mmr_base + 0x10 + (chan->idx * 4))
#define XOR_ACTIVATION(chan) (chan->mmr_base + 0x20 + (chan->idx * 4))
@@ -50,11 +50,11 @@
#define XOR_ERROR_ADDR(chan) (chan->mmr_base + 0x60)
#define XOR_INTR_MASK_VALUE 0x3F5
-#define WINDOW_BASE(w) (0x250 + ((w) << 2))
-#define WINDOW_SIZE(w) (0x270 + ((w) << 2))
-#define WINDOW_REMAP_HIGH(w) (0x290 + ((w) << 2))
-#define WINDOW_BAR_ENABLE(chan) (0x240 + ((chan) << 2))
-#define WINDOW_OVERRIDE_CTRL(chan) (0x2A0 + ((chan) << 2))
+#define WINDOW_BASE(w) (0x50 + ((w) << 2))
+#define WINDOW_SIZE(w) (0x70 + ((w) << 2))
+#define WINDOW_REMAP_HIGH(w) (0x90 + ((w) << 2))
+#define WINDOW_BAR_ENABLE(chan) (0x40 + ((chan) << 2))
+#define WINDOW_OVERRIDE_CTRL(chan) (0xA0 + ((chan) << 2))
struct mv_xor_device {
void __iomem *xor_base;
@@ -82,6 +82,7 @@ struct mv_xor_chan {
int pending;
spinlock_t lock; /* protects the descriptor slot pool */
void __iomem *mmr_base;
+ void __iomem *mmr_high_base;
unsigned int idx;
int irq;
enum dma_transaction_type current_type;
--
1.8.1.5
[ adding dmaengine ]
On Mon, Oct 28, 2013 at 3:54 PM, Ezequiel Garcia
<[email protected]> wrote:
> Despite requesting two memory resources, called 'base' and 'high_base', the
> driver uses explicitly only the former. The latter is being used implicitly
> by addressing at offset +0x200, which in practice accesses high_base.
>
> Instead of relying in such trick, let's define the registers with the
> offset from high_base, and use high_base explicitly where appropriate.
>
> Signed-off-by: Ezequiel Garcia <[email protected]>
> ---
> drivers/dma/mv_xor.c | 3 ++-
> drivers/dma/mv_xor.h | 25 +++++++++++++------------
> 2 files changed, 15 insertions(+), 13 deletions(-)
Since it's unused I'd prefer a patch that just deletes xor_high_base.
--
Dan
On Mon, Oct 28, 2013 at 04:47:20PM -0700, Dan Williams wrote:
> [ adding dmaengine ]
>
> On Mon, Oct 28, 2013 at 3:54 PM, Ezequiel Garcia
> <[email protected]> wrote:
> > Despite requesting two memory resources, called 'base' and 'high_base', the
> > driver uses explicitly only the former. The latter is being used implicitly
> > by addressing at offset +0x200, which in practice accesses high_base.
> >
> > Instead of relying in such trick, let's define the registers with the
> > offset from high_base, and use high_base explicitly where appropriate.
> >
> > Signed-off-by: Ezequiel Garcia <[email protected]>
> > ---
> > drivers/dma/mv_xor.c | 3 ++-
> > drivers/dma/mv_xor.h | 25 +++++++++++++------------
> > 2 files changed, 15 insertions(+), 13 deletions(-)
>
> Since it's unused I'd prefer a patch that just deletes xor_high_base.
>
It's wrongly *unused*, the mmio high_base is actually being used
implicitly by always addressing at an offset that addresses +200.
Deleting high_base would actually make it worse, for that region
will no longer be ioremaped. Maybe the commit message is not clear
about it?
--
Ezequiel García, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com
Dear Ezequiel Garcia,
On Mon, 28 Oct 2013 19:54:14 -0300, Ezequiel Garcia wrote:
> This mmio address is checked at probe-time, which makes this test
> redundant. Let's just remove it.
>
> Signed-off-by: Ezequiel Garcia <[email protected]>
Acked-by: Thomas Petazzoni <[email protected]>
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
Dan, Ezequiel,
On Tue, 29 Oct 2013 05:34:08 -0300, Ezequiel Garcia wrote:
> > On Mon, Oct 28, 2013 at 3:54 PM, Ezequiel Garcia
> > <[email protected]> wrote:
> > > Despite requesting two memory resources, called 'base' and 'high_base', the
> > > driver uses explicitly only the former. The latter is being used implicitly
> > > by addressing at offset +0x200, which in practice accesses high_base.
> > >
> > > Instead of relying in such trick, let's define the registers with the
> > > offset from high_base, and use high_base explicitly where appropriate.
> > >
> > > Signed-off-by: Ezequiel Garcia <[email protected]>
> > > ---
> > > drivers/dma/mv_xor.c | 3 ++-
> > > drivers/dma/mv_xor.h | 25 +++++++++++++------------
> > > 2 files changed, 15 insertions(+), 13 deletions(-)
> >
> > Since it's unused I'd prefer a patch that just deletes xor_high_base.
> >
>
> It's wrongly *unused*, the mmio high_base is actually being used
> implicitly by always addressing at an offset that addresses +200.
>
> Deleting high_base would actually make it worse, for that region
> will no longer be ioremaped. Maybe the commit message is not clear
> about it?
I agree with Ezequiel, and I believe his patch is appropriate. The
registers for the XOR engines are indeed split in two areas, so it
makes sense to have this xor_base / xor_high_base split that reflects
the register mapping passed from the Device Tree, and use this split in
the macros used to access the registers.
Best regards,
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
On Tue, Oct 29, 2013 at 2:32 AM, Thomas Petazzoni
<[email protected]> wrote:
> Dan, Ezequiel,
>
> On Tue, 29 Oct 2013 05:34:08 -0300, Ezequiel Garcia wrote:
>
>> > On Mon, Oct 28, 2013 at 3:54 PM, Ezequiel Garcia
>> > <[email protected]> wrote:
>> > > Despite requesting two memory resources, called 'base' and 'high_base', the
>> > > driver uses explicitly only the former. The latter is being used implicitly
>> > > by addressing at offset +0x200, which in practice accesses high_base.
>> > >
>> > > Instead of relying in such trick, let's define the registers with the
>> > > offset from high_base, and use high_base explicitly where appropriate.
>> > >
>> > > Signed-off-by: Ezequiel Garcia <[email protected]>
>> > > ---
>> > > drivers/dma/mv_xor.c | 3 ++-
>> > > drivers/dma/mv_xor.h | 25 +++++++++++++------------
>> > > 2 files changed, 15 insertions(+), 13 deletions(-)
>> >
>> > Since it's unused I'd prefer a patch that just deletes xor_high_base.
>> >
>>
>> It's wrongly *unused*, the mmio high_base is actually being used
>> implicitly by always addressing at an offset that addresses +200.
>>
>> Deleting high_base would actually make it worse, for that region
>> will no longer be ioremaped. Maybe the commit message is not clear
>> about it?
>
> I agree with Ezequiel, and I believe his patch is appropriate. The
> registers for the XOR engines are indeed split in two areas, so it
> makes sense to have this xor_base / xor_high_base split that reflects
> the register mapping passed from the Device Tree, and use this split in
> the macros used to access the registers.
>
Ah ok, so it's a bug if an implementation ever puts the second
resource window at a non 0x200 offset.
Ezequiel , can you resend the patch to the new
[email protected] list (patchwork queue) and clarify that this
is a fix rather than a pure cleanup in the changelog? At least
cleanup is how I first read it.
Thanks for the clarification.
--
Dan
Dear Dan Williams,
On Tue, 29 Oct 2013 12:15:18 -0700, Dan Williams wrote:
> > I agree with Ezequiel, and I believe his patch is appropriate. The
> > registers for the XOR engines are indeed split in two areas, so it
> > makes sense to have this xor_base / xor_high_base split that reflects
> > the register mapping passed from the Device Tree, and use this split in
> > the macros used to access the registers.
> >
>
> Ah ok, so it's a bug if an implementation ever puts the second
> resource window at a non 0x200 offset.
Exactly.
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
On Tue, Oct 29, 2013 at 12:15:18PM -0700, Dan Williams wrote:
> On Tue, Oct 29, 2013 at 2:32 AM, Thomas Petazzoni
> <[email protected]> wrote:
> > Dan, Ezequiel,
> >
> > On Tue, 29 Oct 2013 05:34:08 -0300, Ezequiel Garcia wrote:
> >
> >> > On Mon, Oct 28, 2013 at 3:54 PM, Ezequiel Garcia
> >> > <[email protected]> wrote:
> >> > > Despite requesting two memory resources, called 'base' and 'high_base', the
> >> > > driver uses explicitly only the former. The latter is being used implicitly
> >> > > by addressing at offset +0x200, which in practice accesses high_base.
> >> > >
> >> > > Instead of relying in such trick, let's define the registers with the
> >> > > offset from high_base, and use high_base explicitly where appropriate.
> >> > >
> >> > > Signed-off-by: Ezequiel Garcia <[email protected]>
> >> > > ---
> >> > > drivers/dma/mv_xor.c | 3 ++-
> >> > > drivers/dma/mv_xor.h | 25 +++++++++++++------------
> >> > > 2 files changed, 15 insertions(+), 13 deletions(-)
> >> >
> >> > Since it's unused I'd prefer a patch that just deletes xor_high_base.
> >> >
> >>
> >> It's wrongly *unused*, the mmio high_base is actually being used
> >> implicitly by always addressing at an offset that addresses +200.
> >>
> >> Deleting high_base would actually make it worse, for that region
> >> will no longer be ioremaped. Maybe the commit message is not clear
> >> about it?
> >
> > I agree with Ezequiel, and I believe his patch is appropriate. The
> > registers for the XOR engines are indeed split in two areas, so it
> > makes sense to have this xor_base / xor_high_base split that reflects
> > the register mapping passed from the Device Tree, and use this split in
> > the macros used to access the registers.
> >
>
> Ah ok, so it's a bug if an implementation ever puts the second
> resource window at a non 0x200 offset.
>
> Ezequiel , can you resend the patch to the new
Sure.
> [email protected] list (patchwork queue) and clarify that this
> is a fix rather than a pure cleanup in the changelog? At least
> cleanup is how I first read it.
>
By the way, I didn't initially Cced dmaengine list because it's not
in the MAINTAINERS file.
How about we add it and avoid this happening to other developers?
diff --git a/MAINTAINERS b/MAINTAINERS
index ebaf8bd..cd57b4a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1397,6 +1397,15 @@ F: drivers/dma/
F: include/linux/dmaengine.h
F: include/linux/async_tx.h
+DMAENGINE SUBSYSTEM
+M: Dan Williams <[email protected]>
+L: [email protected]
+S: Maintained
+F: Documentation/dmaengine.txt
+F: drivers/dma/
+F: include/linux/dma/
+F: include/linux/dmaengine.h
+
AT24 EEPROM DRIVER
M: Wolfram Sang <[email protected]>
L: [email protected]
I'll submit the patch if you want. Just check the above is correct.
If there's a git repo, it might be good to add is as well.
--
Ezequiel García, Free Electrons
Embedded Linux, Kernel and Android Engineering
http://free-electrons.com
On Tue, Oct 29, 2013 at 5:33 PM, Ezequiel Garcia
<[email protected]> wrote:
> By the way, I didn't initially Cced dmaengine list because it's not
> in the MAINTAINERS file.
>
> How about we add it and avoid this happening to other developers?
It's there now, but we just created it so you happened to be one of
the first ones through...
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/MAINTAINERS#n2728
--
Dan