LinuxLists.cc - [PATCH 0/4] ARM:sti: Add STiD127 platform and board support

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Subject: [PATCH 4/4] ARM: dts: add B2112 board support

From: Alexandre TORGUE <[email protected]>

Add support for B2112 board based on STiD127 SoC.

Signed-off-by: Alexandre Torgue <[email protected]>
Signed-off-by: Maxime Coquelin <[email protected]>
---
arch/arm/boot/dts/Makefile | 3 ++-
arch/arm/boot/dts/stid127-b2112.dts | 35 +++++++++++++++++++++++++++++++++++
2 files changed, 37 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/stid127-b2112.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d57c1a6..7173dca 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -247,7 +247,8 @@ dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \
stih416-b2000.dtb \
stih415-b2020.dtb \
- stih416-b2020.dtb
+ stih416-b2020.dtb \
+ stid127-b2112.dtb
dtb-$(CONFIG_ARCH_SUNXI) += \
sun4i-a10-a1000.dtb \
sun4i-a10-cubieboard.dtb \
diff --git a/arch/arm/boot/dts/stid127-b2112.dts b/arch/arm/boot/dts/stid127-b2112.dts
new file mode 100644
index 0000000..b4507e3
--- /dev/null
+++ b/arch/arm/boot/dts/stid127-b2112.dts
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics Limited.
+ * Author: Alexandre Torgue <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "stid127.dtsi"
+
+/ {
+ model = "STiD127 B2112 Board";
+ compatible = "st,stid127", "st,stid127-b2112";
+
+ memory{
+ device_type = "memory";
+ reg = <0x40000000 0x10000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyAS0,115200";
+ linux,stdout-path = &uart2;
+ };
+
+ aliases {
+ ttyAS0 = &uart2;
+ };
+
+ soc {
+ uart2: serial@fe532000{
+ status = "okay";
+ };
+ };
+};
--
1.7.9.5

2014-01-30 14:57:49

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Subject: [PATCH 1/4] ARM: STi: add stid127 soc support

From: Alexandre TORGUE <[email protected]>

This patch adds support to STiD127 SoC.
The main adaptation is the L2 cache way size compare to STiH41x SoCs.

Signed-off-by: alexandre torgue <[email protected]>
Signed-off-by: Patrice Chotard <[email protected]>
---
arch/arm/mach-sti/board-dt.c | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/arch/arm/mach-sti/board-dt.c b/arch/arm/mach-sti/board-dt.c
index 1217fb5..be018a9 100644
--- a/arch/arm/mach-sti/board-dt.c
+++ b/arch/arm/mach-sti/board-dt.c
@@ -9,6 +9,7 @@

#include <linux/irq.h>
#include <linux/of_platform.h>
+#include <linux/of.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>

@@ -18,6 +19,10 @@ void __init stih41x_l2x0_init(void)
{
u32 way_size = 0x4;
u32 aux_ctrl;
+
+ if (of_machine_is_compatible("st,stid127"))
+ way_size = 0x3;
+
/* may be this can be encoded in macros like BIT*() */
aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
(0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
@@ -36,6 +41,7 @@ static void __init stih41x_machine_init(void)
static const char *stih41x_dt_match[] __initdata = {
"st,stih415",
"st,stih416",
+ "st,stid127",
NULL
};

--
1.7.9.5

2014-01-30 15:18:31

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Subject: [PATCH 2/4] pinctrl: st: add stid127 support

From: Alexandre TORGUE <[email protected]>

Add STid127 PIOs (psouth, pwest, peast) in pinctrl.

Signed-off-by: alexandre torgue <[email protected]>
---
drivers/pinctrl/pinctrl-st.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index 9cadc68..01227de 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -336,6 +336,27 @@ static const struct st_pctl_data stih416_data = {
.alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,
};

+/* STid127 data */
+static const struct st_pctl_data stid127_data = {
+ .rt_style = st_retime_style_dedicated,
+ /* reuse stih416 delays as they are identical */
+ .input_delays = stih416_delays,
+ .ninput_delays = 14,
+ /* reuse stih416 delays as they are identical */
+ .output_delays = stih416_delays,
+ .noutput_delays = 14,
+ .alt = 0, .oe = 8, .pu = 10, .od = 12, .rt = 14,
+};
+
+static const struct st_pctl_data stid127_psouth_data = {
+ .rt_style = st_retime_style_dedicated,
+ .input_delays = stid127_delays,
+ .ninput_delays = 14,
+ .output_delays = stid127_delays,
+ .noutput_delays = 14,
+ .alt = 0, .oe = 7, .pu = 9, .od = 11, .rt = 13,
+};
+
/* Low level functions.. */
static inline int st_gpio_bank(int gpio)
{
@@ -1264,6 +1285,10 @@ static struct of_device_id st_pctl_of_match[] = {
{ .compatible = "st,stih416-rear-pinctrl", .data = &stih416_data},
{ .compatible = "st,stih416-fvdp-fe-pinctrl", .data = &stih416_data},
{ .compatible = "st,stih416-fvdp-lite-pinctrl", .data = &stih416_data},
+ { .compatible = "st,stid127-pwest-pinctrl", .data = &stid127_data },
+ { .compatible = "st,stid127-psouth-pinctrl",
+ .data = &stid127_psouth_data },
+ { .compatible = "st,stid127-peast-pinctrl", .data = &stid127_data },
{ /* sentinel */ }
};

--
1.7.9.5

2014-01-30 15:18:58

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Subject: [PATCH 3/4] ARM: dts: Add support of STid127 Soc.

From: Alexandre TORGUE <[email protected]>

The STid127 integrates all harware components to function as a cable modem
or, in combination with a back end device, as a Gateway set top boxe.

Supported devices:
-UART0
-UART2

Signed-off-by: alexandre torgue <[email protected]>
---
arch/arm/boot/dts/stid127-clock.dtsi | 31 ++++
arch/arm/boot/dts/stid127-pinctrl.dtsi | 245 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/stid127.dtsi | 130 +++++++++++++++++
3 files changed, 406 insertions(+)
create mode 100644 arch/arm/boot/dts/stid127-clock.dtsi
create mode 100644 arch/arm/boot/dts/stid127-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/stid127.dtsi

diff --git a/arch/arm/boot/dts/stid127-clock.dtsi b/arch/arm/boot/dts/stid127-clock.dtsi
new file mode 100644
index 0000000..c6cafa9
--- /dev/null
+++ b/arch/arm/boot/dts/stid127-clock.dtsi
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited
+ * Author(s): Giuseppe Cavallaro <[email protected]>
+ * Alexandre Torgue <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/ {
+ clocks {
+ /*
+ * ARM Peripheral clock for timers
+ */
+ arm_periph_clk: arm_periph_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
+ /*
+ * Bootloader initialized system infrastructure clock for
+ * serial devices.
+ */
+ CLK_IC_LP_HD: clockgenA0@29 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ clock-output-names = "CLK_IC_LP_HD";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stid127-pinctrl.dtsi b/arch/arm/boot/dts/stid127-pinctrl.dtsi
new file mode 100644
index 0000000..3fa66f3
--- /dev/null
+++ b/arch/arm/boot/dts/stid127-pinctrl.dtsi
@@ -0,0 +1,245 @@
+/*
+ * Copyright (C) 2012 STMicroelectronics Limited.
+ * Author(s): Giuseppe Cavallaro <[email protected]>
+ * Alexandre Torgue <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "st-pincfg.h"
+/ {
+ aliases {
+ gpio0 = &PIO0;
+ gpio1 = &PIO1;
+ gpio2 = &PIO2;
+ gpio3 = &PIO3;
+ gpio4 = &PIO4;
+ gpio5 = &PIO5;
+ gpio6 = &PIO6;
+ gpio7 = &PIO7;
+ gpio8 = &PIO8;
+ gpio9 = &PIO9;
+ gpio10 = &PIO10;
+ gpio11 = &PIO11;
+ gpio12 = &PIO12;
+ gpio13 = &PIO13;
+ gpio14 = &PIO14;
+ gpio15 = &PIO15;
+ gpio16 = &PIO16;
+ gpio17 = &PIO17;
+ gpio18 = &PIO18;
+ gpio19 = &PIO19;
+ gpio20 = &PIO20;
+ gpio21 = &PIO21;
+ gpio22 = &PIO22;
+
+ };
+
+ soc {
+ pin-controller-pwest {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stid127-pwest-pinctrl";
+ st,syscfg = <&syscfg_pwest>;
+ ranges = <0 0xfebe0000 0x8000>;
+
+ PIO0: gpio@febe0000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0 0x100>;
+ interrupts = <0 149 0>;
+ st,bank-name = "PIO0";
+ };
+ PIO1: gpio@febe1000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x1000 0x100>;
+ interrupts = <0 150 0>;
+ st,bank-name = "PIO1";
+ };
+ PIO2: gpio@febe2000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x2000 0x100>;
+ interrupts = <0 151 0>;
+ st,bank-name = "PIO2";
+ };
+ PIO3: gpio@febe3000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x3000 0x100>;
+ interrupts = <0 152 0>;
+ st,bank-name = "PIO3";
+ };
+ PIO4: gpio@febe4000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x4000 0x100>;
+ interrupts = <0 153 0>;
+ st,bank-name = "PIO4";
+ };
+ PIO5: gpio@febe5000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x5000 0x100>;
+ interrupts = <0 154 0>;
+ st,bank-name = "PIO5";
+ };
+ PIO6: gpio@febe6000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x6000 0x100>;
+ interrupts = <0 155 0>;
+ st,bank-name = "PIO6";
+ };
+ PIO7: gpio@febe7000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x7000 0x100>;
+ interrupts = <0 156 0>;
+ st,bank-name = "PIO7";
+ };
+ uart0 {
+ pinctrl_uart0: uart0 {
+ st,pins {
+ tx = <&PIO3 2 ALT2 OUT>;
+ rx = <&PIO3 0 ALT2 IN>;
+ };
+ };
+ };
+
+ };
+
+ pin-controller-psouth {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stid127-psouth-pinctrl";
+ st,syscfg = <&syscfg_psouth>;
+ ranges = <0 0xfef70000 0x7000>;
+
+ PIO8: gpio@fef70000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0 0x100>;
+ interrupts = <0 157 0>;
+ st,bank-name = "PIO8";
+ };
+ PIO9: gpio@fef71000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x1000 0x100>;
+ interrupts = <0 158 0>;
+ st,bank-name = "PIO9";
+ };
+ PIO10: gpio@fef72000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x2000 0x100>;
+ interrupts = <0 159 0>;
+ st,bank-name = "PIO10";
+ };
+ PIO11: gpio@fef73000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x3000 0x100>;
+ interrupts = <0 160 0>;
+ st,bank-name = "PIO11";
+ };
+ PIO12: gpio@fef74000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x4000 0x100>;
+ interrupts = <0 161 0>;
+ st,bank-name = "PIO12";
+ };
+ PIO13: gpio@fef75000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x5000 0x100>;
+ interrupts = <0 162 0>;
+ st,bank-name = "PIO13";
+ };
+ PIO14: gpio@fef76000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x6000 0x100>;
+ interrupts = <0 163 0>;
+ st,bank-name = "PIO14";
+ };
+ };
+
+ pin-controller-peast {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stid127-peast-pinctrl";
+ st,syscfg = <&syscfg_peast>;
+ ranges = <0 0xfebc0000 0x8000>;
+
+ PIO15: gpio@febc0000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = < 0 0x100>;
+ interrupts = <0 164 0>;
+ st,bank-name = "PIO15";
+ };
+ PIO16: gpio@febc1000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x1000 0x100>;
+ interrupts = <0 165 0>;
+ st,bank-name = "PIO16";
+ };
+ PIO17: gpio@febc2000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x2000 0x100>;
+ interrupts = <0 166 0>;
+ st,bank-name = "PIO17";
+ };
+ PIO18: gpio@febc3000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x3000 0x100>;
+ interrupts = <0 167 0>;
+ st,bank-name = "PIO18";
+ };
+ PIO19: gpio@febc4000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x4000 0x100>;
+ interrupts = <0 168 0>;
+ st,bank-name = "PIO19";
+ };
+ PIO20: gpio@febc5000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x5000 0x100>;
+ interrupts = <0 169 0>;
+ st,bank-name = "PIO20";
+ };
+ PIO21: gpio@febc6000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x6000 0x100>;
+ interrupts = <0 170 0>;
+ st,bank-name = "PIO21";
+ };
+ PIO22: gpio@febc7000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x7000 0x100>;
+ interrupts = <0 171 0>;
+ st,bank-name = "PIO22";
+ };
+ uart2 {
+ pinctrl_uart2: uart2-0 {
+ st,pins {
+ tx = <&PIO20 1 ALT3 OUT>;
+ rx = <&PIO20 2 ALT3 IN>;
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stid127.dtsi b/arch/arm/boot/dts/stid127.dtsi
new file mode 100644
index 0000000..a6f0b8fe
--- /dev/null
+++ b/arch/arm/boot/dts/stid127.dtsi
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics Limited.
+ * Author(s): Giuseppe Cavallaro <[email protected]>
+ * Alexandre Torgue <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "stid127-pinctrl.dtsi"
+#include "stid127-clock.dtsi"
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ };
+ };
+
+ intc: interrupt-controller@fffe1000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xfffe1000 0x1000>,
+ <0xfffe0100 0x100>;
+ };
+
+ scu@fffe0000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0xfffe0000 0x1000>;
+ };
+
+ timer@fffe0200 {
+ interrupt-parent = <&intc>;
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0xfffe0200 0x100>;
+ interrupts = <1 11 0x04>;
+ clocks = <&arm_periph_clk>;
+ };
+
+ L2: cache-controller {
+ compatible = "arm,pl310-cache";
+ reg = <0xfffe2000 0x1000>;
+ arm,data-latency = <3 2 2>;
+ arm,tag-latency = <1 1 1>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges;
+ compatible = "simple-bus";
+
+ syscfg_west:west-syscfg@febf0000{
+ compatible = "st,stid127-west-syscfg", "syscon";
+ reg = <0xfebf0000 0x1000>;
+ };
+
+ syscfg_south:south-syscfg@fefa0000{
+ compatible = "st,stid127-south-syscfg", "syscon";
+ reg = <0xfefa0000 0x1000>;
+ };
+
+ syscfg_docsis:docsis-syscfg@fef90000{
+ compatible = "st,stid127-docsys-syscfg", "syscon";
+ reg = <0xfef90000 0x1000>;
+ };
+
+ syscfg_cpu:cpu-syscfg@fe9a0000{
+ compatible = "st,stid127-cpu-syscfg", "syscon";
+ reg = <0xfe9a0000 0x1000>;
+ };
+
+ syscfg_hd:hd-syscfg@fe930000{
+ compatible = "st,stid127-hd-syscfg", "syscon";
+ reg = <0xfe930000 0x1000>;
+ };
+
+ syscfg_pwest:pwest-syscfg@fec00000{
+ compatible = "st,stid127-pwest-syscfg", "syscon";
+ reg = <0xfec00000 0x1000>;
+ };
+
+ syscfg_psouth:psouth-syscfg@fefd0000{
+ compatible = "st,stid127-psouth-syscfg", "syscon";
+ reg = <0xfefd0000 0x1000>;
+ };
+
+ syscfg_peast:peast-syscfg@febd0000{
+ compatible = "st,stid127-peast-syscfg", "syscon";
+ reg = <0xfebd0000 0x1000>;
+ };
+
+ /* Comms block ASCs in SASG2 */
+ uart0: serial@fe530000{
+ compatible = "st,asc";
+ status = "disabled";
+ reg = <0xfe530000 0x2c>;
+ interrupts = <0 25 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&CLK_IC_LP_HD>;
+ };
+
+ uart2: serial@fe532000{
+ compatible = "st,asc";
+ status = "disabled";
+ reg = <0xfe532000 0x2c>;
+ interrupts = <0 27 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&CLK_IC_LP_HD>;
+ };
+ };
+};
--
1.7.9.5

2014-01-30 18:36:05

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Subject: Re: [PATCH 1/4] ARM: STi: add stid127 soc support

On Thursday 30 January 2014, Patrice CHOTARD wrote:
> From: Alexandre TORGUE <[email protected]>
>
> This patch adds support to STiD127 SoC.
> The main adaptation is the L2 cache way size compare to STiH41x SoCs.
>
> Signed-off-by: alexandre torgue <[email protected]>
> Signed-off-by: Patrice Chotard <[email protected]>
> ---
> arch/arm/mach-sti/board-dt.c | 6 ++++++
> 1 file changed, 6 insertions(+)

Wouldn't it be better to read this value from the l2 cache
controller node? I'd assume there might be more SoCs that
will need a similar change, so it's better to come up with
a solution that doesn't involve changing the kernel every
time.

Arnd

2014-01-30 18:39:17

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Subject: Re: [PATCH 1/4] ARM: STi: add stid127 soc support

On Thursday 30 January 2014, Arnd Bergmann wrote:
> On Thursday 30 January 2014, Patrice CHOTARD wrote:
> > From: Alexandre TORGUE <[email protected]>
> >
> > This patch adds support to STiD127 SoC.
> > The main adaptation is the L2 cache way size compare to STiH41x SoCs.
> >
> > Signed-off-by: alexandre torgue <[email protected]>
> > Signed-off-by: Patrice Chotard <[email protected]>
> > ---
> > arch/arm/mach-sti/board-dt.c | 6 ++++++
> > 1 file changed, 6 insertions(+)
>
> Wouldn't it be better to read this value from the l2 cache
> controller node? I'd assume there might be more SoCs that
> will need a similar change, so it's better to come up with
> a solution that doesn't involve changing the kernel every
> time.

Actually reading the code in this file shows that the L2 cache
initialization is the only nonstandard thing in there. We should
really find a way to get rid of the entire function.

Sorry if I missed the initial review, but can you explain
why this is needed to start with?

Arnd

2014-01-31 12:35:06

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Subject: Re: [PATCH 1/4] ARM: STi: add stid127 soc support

Hi Arnd,
On 30/01/14 18:39, Arnd Bergmann wrote:
> Actually reading the code in this file shows that the L2 cache
> initialization is the only nonstandard thing in there. We should
> really find a way to get rid of the entire function.
I think this will get rid of lot of code left in board-dt.

>
> Sorry if I missed the initial review, but can you explain
> why this is needed to start with?
On ST SoCs the default value for L2 AUX_CTRL register is 0x0, so we set
the way-size explicit here.

Thanks,
srini

2014-01-31 12:37:01

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Subject: Re: [PATCH 2/4] pinctrl: st: add stid127 support

Looks good for me.

Acked-by: Srinivas Kandagatla <[email protected]>

On 30/01/14 14:55, Patrice CHOTARD wrote:
> From: Alexandre TORGUE <[email protected]>
>
> Add STid127 PIOs (psouth, pwest, peast) in pinctrl.
>
> Signed-off-by: alexandre torgue <[email protected]>
> ---
> drivers/pinctrl/pinctrl-st.c | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
> index 9cadc68..01227de 100644
> --- a/drivers/pinctrl/pinctrl-st.c
> +++ b/drivers/pinctrl/pinctrl-st.c
> @@ -336,6 +336,27 @@ static const struct st_pctl_data stih416_data = {
> .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,
> };
>
> +/* STid127 data */
> +static const struct st_pctl_data stid127_data = {
> + .rt_style = st_retime_style_dedicated,
> + /* reuse stih416 delays as they are identical */
> + .input_delays = stih416_delays,
> + .ninput_delays = 14,
> + /* reuse stih416 delays as they are identical */
> + .output_delays = stih416_delays,
> + .noutput_delays = 14,
> + .alt = 0, .oe = 8, .pu = 10, .od = 12, .rt = 14,
> +};
> +
> +static const struct st_pctl_data stid127_psouth_data = {
> + .rt_style = st_retime_style_dedicated,
> + .input_delays = stid127_delays,
> + .ninput_delays = 14,
> + .output_delays = stid127_delays,
> + .noutput_delays = 14,
> + .alt = 0, .oe = 7, .pu = 9, .od = 11, .rt = 13,
> +};
> +
> /* Low level functions.. */
> static inline int st_gpio_bank(int gpio)
> {
> @@ -1264,6 +1285,10 @@ static struct of_device_id st_pctl_of_match[] = {
> { .compatible = "st,stih416-rear-pinctrl", .data = &stih416_data},
> { .compatible = "st,stih416-fvdp-fe-pinctrl", .data = &stih416_data},
> { .compatible = "st,stih416-fvdp-lite-pinctrl", .data = &stih416_data},
> + { .compatible = "st,stid127-pwest-pinctrl", .data = &stid127_data },
> + { .compatible = "st,stid127-psouth-pinctrl",
> + .data = &stid127_psouth_data },
> + { .compatible = "st,stid127-peast-pinctrl", .data = &stid127_data },
> { /* sentinel */ }
> };
>
>

2014-01-31 12:57:05

[permalink] [raw]

Subject: Re: [PATCH 3/4] ARM: dts: Add support of STid127 Soc.

Hi Patrice,

On 30/01/14 14:55, Patrice CHOTARD wrote:
> From: Alexandre TORGUE <[email protected]>
>
> The STid127 integrates all harware components to function as a cable modem
s/harware/hardware/

s/STid127/STiD127

Please fix other instances too.

> or, in combination with a back end device, as a Gateway set top boxe.
s/boxe/box/
>
> Supported devices:
> -UART0
> -UART2
>
> Signed-off-by: alexandre torgue <[email protected]>
> ---
> arch/arm/boot/dts/stid127-clock.dtsi | 31 ++++
> arch/arm/boot/dts/stid127-pinctrl.dtsi | 245 ++++++++++++++++++++++++++++++++
> arch/arm/boot/dts/stid127.dtsi | 130 +++++++++++++++++
> 3 files changed, 406 insertions(+)
> create mode 100644 arch/arm/boot/dts/stid127-clock.dtsi
> create mode 100644 arch/arm/boot/dts/stid127-pinctrl.dtsi
> create mode 100644 arch/arm/boot/dts/stid127.dtsi
>
> diff --git a/arch/arm/boot/dts/stid127-clock.dtsi b/arch/arm/boot/dts/stid127-clock.dtsi
> new file mode 100644
> index 0000000..c6cafa9
> --- /dev/null
> +++ b/arch/arm/boot/dts/stid127-clock.dtsi
> @@ -0,0 +1,31 @@
> +/*
> + * Copyright (C) 2013 STMicroelectronics (R&D) Limited

2014

> + * Author(s): Giuseppe Cavallaro <[email protected]>
> + * Alexandre Torgue <[email protected]>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +/ {Acked-by: Srinivas Kandagatla <[email protected]>
> + clocks {
> + /*
> + * ARM Peripheral clock for timers
> + */
> + arm_periph_clk: arm_periph_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <100000000>;
> + };
> + /*
> + * Bootloader initialized system infrastructure clock for
> + * serial devices.
> + */
> + CLK_IC_LP_HD: clockgenA0@29 {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <100000000>;
> + clock-output-names = "CLK_IC_LP_HD";
> + };
> + };
> +};
> diff --git a/arch/arm/boot/dts/stid127-pinctrl.dtsi b/arch/arm/boot/dts/stid127-pinctrl.dtsi
> new file mode 100644
> index 0000000..3fa66f3
> --- /dev/null
> +++ b/arch/arm/boot/dts/stid127-pinctrl.dtsi
> @@ -0,0 +1,245 @@
> +/*
> + * Copyright (C) 2012 STMicroelectronics Limited.

2014

> + * Author(s): Giuseppe Cavallaro <[email protected]>
> + * Alexandre Torgue <[email protected]>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * publishhed by the Free Software Foundation.

s/publishhed/published/

> + */
> +#include "st-pincfg.h"
> +/ {
> + aliases {
> + gpio0 = &PIO0;
> + gpio1 = &PIO1;
> + gpio2 = &PIO2;
> + gpio3 = &PIO3;
> + gpio4 = &PIO4;
> + gpio5 = &PIO5;
> + gpio6 = &PIO6;
> + gpio7 = &PIO7;
> + gpio8 = &PIO8;
> + gpio9 = &PIO9;
> + gpio10 = &PIO10;
> + gpio11 = &PIO11;
> + gpio12 = &PIO12;
> + gpio13 = &PIO13;
> + gpio14 = &PIO14;
> + gpio15 = &PIO15;
> + gpio16 = &PIO16;
> + gpio17 = &PIO17;
> + gpio18 = &PIO18;
> + gpio19 = &PIO19;
> + gpio20 = &PIO20;
> + gpio21 = &PIO21;
> + gpio22 = &PIO22;
> +
> + };
> +
> + soc {
> + pin-controller-pwest {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "st,stid127-pwest-pinctrl";
> + st,syscfg = <&syscfg_pwest>;
> + ranges = <0 0xfebe0000 0x8000>;

Can you add interrupt controller support to the pin controller.

Patches are in : https://lkml.org/lkml/2014/1/16/342
All these patches are due to be in v3.15.

> +
> + PIO0: gpio@febe0000 {
> + gpio-controller;
> + #gpio-cells = <1>;
> + reg = <0 0x100>;
> + interrupts = <0 149 0>;
> + st,bank-name = "PIO0";
> + };
> + rx = <&PIO3 0 ALT2 IN>;
> + };
> + };
> + };
> +
> + };
unnecessary empty line here.

> diff --git a/arch/arm/boot/dts/stid127.dtsi b/arch/arm/boot/dts/stid127.dtsi
> new file mode 100644
> index 0000000..a6f0b8fe
> --- /dev/null
> +++ b/arch/arm/boot/dts/stid127.dtsi
> @@ -0,0 +1,130 @@
> +/*
> + * Copyright (C) 2013 STMicroelectronics Limited.
2014
> + * Author(s): Giuseppe Cavallaro <[email protected]>
> + * Alexandre Torgue <[email protected]>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * publishhed by the Free Software Foundation.

s/publishhed/published/

> + */
> +#include "stid127-pinctrl.dtsi"
> +#include "stid127-clock.dtsi"
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + reg = <0>;
> + };
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + reg = <1>;
> + };
> + };
> +
> + intc: interrupt-controller@fffe1000 {
> + compatible = "arm,cortex-a9-gic";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0xfffe1000 0x1000>,
> + <0xfffe0100 0x100>;
> + };
> +
> + scu@fffe0000 {
> + compatible = "arm,cortex-a9-scu";
> + reg = <0xfffe0000 0x1000>;
> + };
> +
> + timer@fffe0200 {
> + interrupt-parent = <&intc>;
> + compatible = "arm,cortex-a9-global-timer";
> + reg = <0xfffe0200 0x100>;
> + interrupts = <1 11 0x04>;
> + clocks = <&arm_periph_clk>;

Fix the tab spacing here.

Thanks,
srini
>

2014-01-31 12:58:10

[permalink] [raw]

Subject: Re: [PATCH 4/4] ARM: dts: add B2112 board support

On 30/01/14 14:55, Patrice CHOTARD wrote:
> From: Alexandre TORGUE <[email protected]>
>
> Add support for B2112 board based on STiD127 SoC.
>
> Signed-off-by: Alexandre Torgue <[email protected]>
> Signed-off-by: Maxime Coquelin <[email protected]>
> ---
> arch/arm/boot/dts/Makefile | 3 ++-
> arch/arm/boot/dts/stid127-b2112.dts | 35 +++++++++++++++++++++++++++++++++++
> 2 files changed, 37 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/stid127-b2112.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index d57c1a6..7173dca 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -247,7 +247,8 @@ dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
> dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \
> stih416-b2000.dtb \
> stih415-b2020.dtb \
> - stih416-b2020.dtb
> + stih416-b2020.dtb \
> + stid127-b2112.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += \
> sun4i-a10-a1000.dtb \
> sun4i-a10-cubieboard.dtb \
> diff --git a/arch/arm/boot/dts/stid127-b2112.dts b/arch/arm/boot/dts/stid127-b2112.dts
> new file mode 100644
> index 0000000..b4507e3
> --- /dev/null
> +++ b/arch/arm/boot/dts/stid127-b2112.dts
> @@ -0,0 +1,35 @@
> +/*
> + * Copyright (C) 2013 STMicroelectronics Limited.

2014

> + * Author: Alexandre Torgue <[email protected]>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * publishhed by the Free Software Foundation.

s/publishhed/published/

> + */
> +/dts-v1/;
> +#include "stid127.dtsi"
> +
> +/ {
> + model = "STiD127 B2112 Board";
> + compatible = "st,stid127", "st,stid127-b2112";
> +
> + memory{
> + device_type = "memory";
> + reg = <0x40000000 0x10000000>;
> + };
> +
> + chosen {
> + bootargs = "console=ttyAS0,115200";
> + linux,stdout-path = &uart2;
> + };
> +
> + aliases {
> + ttyAS0 = &uart2;
> + };
> +
> + soc {
> + uart2: serial@fe532000{
> + status = "okay";
> + };
> + };
> +};
>

2014-01-31 20:15:45

[permalink] [raw]

Subject: Re: [PATCH 1/4] ARM: STi: add stid127 soc support

On Friday 31 January 2014, srinivas kandagatla wrote:

> > Sorry if I missed the initial review, but can you explain
> > why this is needed to start with?
>
> On ST SoCs the default value for L2 AUX_CTRL register is 0x0, so we set
> the way-size explicit here.

Unfortunately, we keep going back and forth on the L2 cache controller
setup between "it should work automatically" and "we don't want to
have configuration data in DT", where my personal opinion is that
the first one is more important here.

Now, there are a couple of properties that are defined in
Documentation/devicetree/bindings/arm/l2cc.txt to let some of the
things get set up automatically already. Can you check which bits
are missing there, if any? Are they better described as "configuration"
or "hardware" settings?

Arnd

2014-02-03 08:35:31

by Alexandre Torgue

[permalink] [raw]

Subject: Re: [PATCH 1/4] ARM: STi: add stid127 soc support

On 01/31/2014 09:15 PM, Arnd Bergmann wrote:
> On Friday 31 January 2014, srinivas kandagatla wrote:
>
>>> Sorry if I missed the initial review, but can you explain
>>> why this is needed to start with?
>> On ST SoCs the default value for L2 AUX_CTRL register is 0x0, so we set
>> the way-size explicit here.
> Unfortunately, we keep going back and forth on the L2 cache controller
> setup between "it should work automatically" and "we don't want to
> have configuration data in DT", where my personal opinion is that
> the first one is more important here.
>
> Now, there are a couple of properties that are defined in
> Documentation/devicetree/bindings/arm/l2cc.txt to let some of the
> things get set up automatically already. Can you check which bits
> are missing there, if any? Are they better described as "configuration"
> or "hardware" settings?
Hi Arnd,

Thanks for remarks. I will a have a look on it, but unfortunately not
before 2 weeks.

Alex.

>
> Arnd

2014-02-04 20:54:34

by Linus Walleij

[permalink] [raw]

Subject: Re: [PATCH 2/4] pinctrl: st: add stid127 support

On Thu, Jan 30, 2014 at 3:55 PM, Patrice CHOTARD <[email protected]> wrote:

> From: Alexandre TORGUE <[email protected]>
>
> Add STid127 PIOs (psouth, pwest, peast) in pinctrl.
>
> Signed-off-by: alexandre torgue <[email protected]>

Patch applied with Srinivas ACK.

Yours,
Linus Walleij

2014-02-05 10:29:15

[permalink] [raw]

Subject: Re: [PATCH 3/4] ARM: dts: Add support of STid127 Soc.

Hi Srinivas

Thanks for reviewing, a V2 serie will be pushed with all required fixes.

Patrice

On 01/31/2014 01:50 PM, srinivas kandagatla wrote:
> Hi Patrice,
>
> On 30/01/14 14:55, Patrice CHOTARD wrote:
>> From: Alexandre TORGUE <[email protected]>
>>
>> The STid127 integrates all harware components to function as a cable modem
> s/harware/hardware/
>
> s/STid127/STiD127
>
> Please fix other instances too.
>
>> or, in combination with a back end device, as a Gateway set top boxe.
> s/boxe/box/
>> Supported devices:
>> -UART0
>> -UART2
>>
>> Signed-off-by: alexandre torgue <[email protected]>
>> ---
>> arch/arm/boot/dts/stid127-clock.dtsi | 31 ++++
>> arch/arm/boot/dts/stid127-pinctrl.dtsi | 245 ++++++++++++++++++++++++++++++++
>> arch/arm/boot/dts/stid127.dtsi | 130 +++++++++++++++++
>> 3 files changed, 406 insertions(+)
>> create mode 100644 arch/arm/boot/dts/stid127-clock.dtsi
>> create mode 100644 arch/arm/boot/dts/stid127-pinctrl.dtsi
>> create mode 100644 arch/arm/boot/dts/stid127.dtsi
>>
>> diff --git a/arch/arm/boot/dts/stid127-clock.dtsi b/arch/arm/boot/dts/stid127-clock.dtsi
>> new file mode 100644
>> index 0000000..c6cafa9
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/stid127-clock.dtsi
>> @@ -0,0 +1,31 @@
>> +/*
>> + * Copyright (C) 2013 STMicroelectronics (R&D) Limited
> 2014
>
>> + * Author(s): Giuseppe Cavallaro <[email protected]>
>> + * Alexandre Torgue <[email protected]>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +/ {Acked-by: Srinivas Kandagatla <[email protected]>
>> + clocks {
>> + /*
>> + * ARM Peripheral clock for timers
>> + */
>> + arm_periph_clk: arm_periph_clk {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <100000000>;
>> + };
>> + /*
>> + * Bootloader initialized system infrastructure clock for
>> + * serial devices.
>> + */
>> + CLK_IC_LP_HD: clockgenA0@29 {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <100000000>;
>> + clock-output-names = "CLK_IC_LP_HD";
>> + };
>> + };
>> +};
>> diff --git a/arch/arm/boot/dts/stid127-pinctrl.dtsi b/arch/arm/boot/dts/stid127-pinctrl.dtsi
>> new file mode 100644
>> index 0000000..3fa66f3
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/stid127-pinctrl.dtsi
>> @@ -0,0 +1,245 @@
>> +/*
>> + * Copyright (C) 2012 STMicroelectronics Limited.
> 2014
>
>> + * Author(s): Giuseppe Cavallaro <[email protected]>
>> + * Alexandre Torgue <[email protected]>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * publishhed by the Free Software Foundation.
> s/publishhed/published/
>
>> + */
>> +#include "st-pincfg.h"
>> +/ {
>> + aliases {
>> + gpio0 = &PIO0;
>> + gpio1 = &PIO1;
>> + gpio2 = &PIO2;
>> + gpio3 = &PIO3;
>> + gpio4 = &PIO4;
>> + gpio5 = &PIO5;
>> + gpio6 = &PIO6;
>> + gpio7 = &PIO7;
>> + gpio8 = &PIO8;
>> + gpio9 = &PIO9;
>> + gpio10 = &PIO10;
>> + gpio11 = &PIO11;
>> + gpio12 = &PIO12;
>> + gpio13 = &PIO13;
>> + gpio14 = &PIO14;
>> + gpio15 = &PIO15;
>> + gpio16 = &PIO16;
>> + gpio17 = &PIO17;
>> + gpio18 = &PIO18;
>> + gpio19 = &PIO19;
>> + gpio20 = &PIO20;
>> + gpio21 = &PIO21;
>> + gpio22 = &PIO22;
>> +
>> + };
>> +
>> + soc {
>> + pin-controller-pwest {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "st,stid127-pwest-pinctrl";
>> + st,syscfg = <&syscfg_pwest>;
>> + ranges = <0 0xfebe0000 0x8000>;
> Can you add interrupt controller support to the pin controller.
>
> Patches are in : https://lkml.org/lkml/2014/1/16/342
> All these patches are due to be in v3.15.
>
>> +
>> + PIO0: gpio@febe0000 {
>> + gpio-controller;
>> + #gpio-cells = <1>;
>> + reg = <0 0x100>;
>> + interrupts = <0 149 0>;
>> + st,bank-name = "PIO0";
>> + };
>> + rx = <&PIO3 0 ALT2 IN>;
>> + };
>> + };
>> + };
>> +
>> + };
> unnecessary empty line here.
>
>> diff --git a/arch/arm/boot/dts/stid127.dtsi b/arch/arm/boot/dts/stid127.dtsi
>> new file mode 100644
>> index 0000000..a6f0b8fe
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/stid127.dtsi
>> @@ -0,0 +1,130 @@
>> +/*
>> + * Copyright (C) 2013 STMicroelectronics Limited.
> 2014
>> + * Author(s): Giuseppe Cavallaro <[email protected]>
>> + * Alexandre Torgue <[email protected]>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * publishhed by the Free Software Foundation.
> s/publishhed/published/
>
>> + */
>> +#include "stid127-pinctrl.dtsi"
>> +#include "stid127-clock.dtsi"
>> +/ {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu@0 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a9";
>> + reg = <0>;
>> + };
>> + cpu@1 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a9";
>> + reg = <1>;
>> + };
>> + };
>> +
>> + intc: interrupt-controller@fffe1000 {
>> + compatible = "arm,cortex-a9-gic";
>> + #interrupt-cells = <3>;
>> + interrupt-controller;
>> + reg = <0xfffe1000 0x1000>,
>> + <0xfffe0100 0x100>;
>> + };
>> +
>> + scu@fffe0000 {
>> + compatible = "arm,cortex-a9-scu";
>> + reg = <0xfffe0000 0x1000>;
>> + };
>> +
>> + timer@fffe0200 {
>> + interrupt-parent = <&intc>;
>> + compatible = "arm,cortex-a9-global-timer";
>> + reg = <0xfffe0200 0x100>;
>> + interrupts = <1 11 0x04>;
>> + clocks = <&arm_periph_clk>;
> Fix the tab spacing here.
>
> Thanks,
> srini

2014-02-05 11:55:50

[permalink] [raw]

Subject: Re: [PATCH 1/4] ARM: STi: add stid127 soc support

Hi Arnd,
On 31/01/14 20:15, Arnd Bergmann wrote:
> On Friday 31 January 2014, srinivas kandagatla wrote:
>
>>> Sorry if I missed the initial review, but can you explain
>>> why this is needed to start with?
>>
>> On ST SoCs the default value for L2 AUX_CTRL register is 0x0, so we set
>> the way-size explicit here.
>
> Unfortunately, we keep going back and forth on the L2 cache controller
> setup between "it should work automatically" and "we don't want to
> have configuration data in DT", where my personal opinion is that
> the first one is more important here.
>
> Now, there are a couple of properties that are defined in
> Documentation/devicetree/bindings/arm/l2cc.txt to let some of the
> things get set up automatically already. Can you check which bits
> are missing there, if any? Are they better described as "configuration"
> or "hardware" settings?

Currently l2cc bindings has few optional properties like.

- arm,data-latency
- arm,tag-latency
- arm,dirty-latency
- arm,filter-ranges
- interrupts :
- cache-id-part:
- wt-override:

These does not include properties to set "way-size", "associativity",
"enabling prefetching", "Prefetch drop enable", "prefetch offset",
"Double linefill" and few more in prefect control register and
aux-control register.

This is not just a issue with STi SOCs, having a quick look, I can see
that few more SOCs have similar requirements to set these properties.

We could do two things to get l2 setup automatically on STi SOCS.

1> Either define these properties case-by-case basic, which might be
useful for other SOCs too.

2> Or Add new compatible string for STi SoCs so that they can
automatically setup these values in cache-l2x0.c

Am Ok with either approaches.

Thanks,
srini

>
> Arnd
>
>

2014-02-06 16:46:47

[permalink] [raw]

Subject: Re: [PATCH 1/4] ARM: STi: add stid127 soc support

On Wednesday 05 February 2014, srinivas kandagatla wrote:
> Currently l2cc bindings has few optional properties like.
>
> - arm,data-latency
> - arm,tag-latency
> - arm,dirty-latency
> - arm,filter-ranges
> - interrupts :
> - cache-id-part:
> - wt-override:
>
> These does not include properties to set "way-size", "associativity",
> "enabling prefetching", "Prefetch drop enable", "prefetch offset",
> "Double linefill" and few more in prefect control register and
> aux-control register.
>
> This is not just a issue with STi SOCs, having a quick look, I can see
> that few more SOCs have similar requirements to set these properties.
>
> We could do two things to get l2 setup automatically on STi SOCS.
>
> 1> Either define these properties case-by-case basic, which might be
> useful for other SOCs too.
>
> 2> Or Add new compatible string for STi SoCs so that they can
> automatically setup these values in cache-l2x0.c
>
> Am Ok with either approaches.
>

I suggested 1 in the past, but the objection that I saw (can't
find the email at the moment) was that the additional settings
are "configuration" rather than "hardware properties". What I'd
really need to know from you is which of properties you listed
as missing above are actually needed for your platform, and whether
they can be classified as hardware specific or just configuration.

Arnd

2014-02-07 08:15:36

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Subject: Re: [PATCH 1/4] ARM: STi: add stid127 soc support

On 06/02/14 16:46, Arnd Bergmann wrote:
> On Wednesday 05 February 2014, srinivas kandagatla wrote:
>> Currently l2cc bindings has few optional properties like.
>>
>> - arm,data-latency
>> - arm,tag-latency
>> - arm,dirty-latency
>> - arm,filter-ranges
>> - interrupts :
>> - cache-id-part:
>> - wt-override:
>>
>> These does not include properties to set "way-size", "associativity",
>> "enabling prefetching", "Prefetch drop enable", "prefetch offset",
>> "Double linefill" and few more in prefect control register and
>> aux-control register.
>>
>> This is not just a issue with STi SOCs, having a quick look, I can see
>> that few more SOCs have similar requirements to set these properties.
>>
>> We could do two things to get l2 setup automatically on STi SOCS.
>>
>> 1> Either define these properties case-by-case basic, which might be
>> useful for other SOCs too.
>>
>> 2> Or Add new compatible string for STi SoCs so that they can
>> automatically setup these values in cache-l2x0.c
>>
>> Am Ok with either approaches.
>>
>
> I suggested 1 in the past, but the objection that I saw (can't
> find the email at the moment) was that the additional settings
> are "configuration" rather than "hardware properties". What I'd
> really need to know from you is which of properties you listed
> as missing above are actually needed for your platform, and whether
> they can be classified as hardware specific or just configuration.

On STi Platforms we need below properties to got for option 1.
arm,way-size;
arm,instruction-prefetch-enable;
arm,data-prefetch-enable;

we also want a property or a way to set
"Shareable attribute Override Enable" bit in the Auxiliary Control
Register, bit[22].

Thanks,
srini
>
> Arnd
>
>

2014-02-27 12:28:01