This series does some cleanups, fixes for handling two interrupts
getting mapped twice to same crossbar and provides support for
hardwired IRQ and crossbar definitions.
On certain platforms such as DRA7, SPIs 0, 1, 2, 3, 5, 6, 10,
131, 132, 133 are direct wired to hardware blocks bypassing
crossbar. This quirky implementation is *NOT* supposed to be the
expectation of crossbar hardware usage. This series adds support
to represent such hard-wired irqs through DT and avoid generic
allocation/programming of crossbar in the driver.
This way of supporting hard-wired irqs was a result of
the below discussions.
http://www.spinics.net/lists/arm-kernel/msg329946.html
Based on 3.16 rc2 mainline.
All the patches are available here
[email protected]:Sricharanti/sricharan.git crossbar_updates
The fixes series[1] earlier posted is merged in to this.
[1] http://www.spinics.net/lists/arm-kernel/msg328273.html
[V2] Merged the above series and rebased on 3.15 mainline
[V3] Modified patch#3 to get irqs-skip properties from DT,
merged path#8 for checkpatch warning to other relevant
patches and fixed comments for other patches.
[V4] Based on 3.16rc2 and fixed Jason's <[email protected]> comments.
Nishanth Menon (14):
irqchip: crossbar: Dont use '0' to mark reserved interrupts
irqchip: crossbar: Check for premapped crossbar before allocating
irqchip: crossbar: Introduce ti,irqs-skip to skip irqs that bypass
crossbar
irqchip: crossbar: Initialise the crossbar with a safe value
irqchip: crossbar: Change allocation logic by reversing search for
free irqs
irqchip: crossbar: Remove IS_ERR_VALUE check
irqchip: crossbar: Fix sparse and checkpatch warnings
irqchip: crossbar: Fix kerneldoc warning
irqchip: crossbar: Return proper error value
irqchip: crossbar: Change the goto naming
irqchip: crossbar: Introduce ti,max-crossbar-sources to identify
valid crossbar mapping
irqchip: crossbar: Introduce centralized check for crossbar write
documentation: dt: omap: crossbar: Add description for interrupt
consumer
irqchip: crossbar: Allow for quirky hardware with direct hardwiring
of GIC
Sricharan R (2):
irqchip: crossbar: Set cb pointer to null in case of error
irqchip: crossbar: Add kerneldoc for crossbar_domain_unmap callback
.../devicetree/bindings/arm/omap/crossbar.txt | 36 +++++
drivers/irqchip/irq-crossbar.c | 168 +++++++++++++++++---
2 files changed, 179 insertions(+), 25 deletions(-)
--
1.7.9.5
From: Nishanth Menon <[email protected]>
Today '0' is actually reserved, but may not be the same in the future.
So, use a flag to mark the GIC interrupts that are reserved.
Signed-off-by: Nishanth Menon <[email protected]>
Signed-off-by: Sricharan R <[email protected]>
Acked-by: Santosh Shilimkar <[email protected]>
---
drivers/irqchip/irq-crossbar.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index 3d15d16..20105bc 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -17,6 +17,7 @@
#include <linux/irqchip/arm-gic.h>
#define IRQ_FREE -1
+#define IRQ_RESERVED -2
#define GIC_IRQ_START 32
/*
@@ -139,7 +140,7 @@ static int __init crossbar_of_init(struct device_node *node)
pr_err("Invalid reserved entry\n");
goto err3;
}
- cb->irq_map[entry] = 0;
+ cb->irq_map[entry] = IRQ_RESERVED;
}
}
@@ -170,7 +171,7 @@ static int __init crossbar_of_init(struct device_node *node)
* reserved irqs. so find and store the offsets once.
*/
for (i = 0; i < max; i++) {
- if (!cb->irq_map[i])
+ if (cb->irq_map[i] == IRQ_RESERVED)
continue;
cb->register_offsets[i] = reserved;
--
1.7.9.5
From: Nishanth Menon <[email protected]>
Since crossbar is s/w configurable, the initial settings of the
crossbar cannot be assumed to be sane. This implies that:
a) On initialization all un-reserved crossbars must be initialized to
a known 'safe' value.
b) When unmapping the interrupt, the safe value must be written to
ensure that the crossbar mapping matches with interrupt controller
usage.
So provide a safe value in the dt data to map if
'0' is not safe for the platform and use it during init and unmap
While at this, fix the below checkpatch warning.
Fixes checkpatch warning:
WARNING: Unnecessary space before function pointer arguments
#37: FILE: drivers/irqchip/irq-crossbar.c:37:
+ void (*write) (int, int);
Signed-off-by: Nishanth Menon <[email protected]>
Signed-off-by: Sricharan R <[email protected]>
Acked-by: Santosh Shilimkar <[email protected]>
---
.../devicetree/bindings/arm/omap/crossbar.txt | 3 +++
drivers/irqchip/irq-crossbar.c | 19 +++++++++++++++++--
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
index 0795765..5f45c78 100644
--- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -22,6 +22,9 @@ Optional properties:
SOC-specific hard-wiring of those irqs which unexpectedly bypasses the
crossbar. These irqs have a crossbar register, but still cannot be used.
+- ti,irqs-safe-map: integer which maps to a safe configuration to use
+ when the interrupt controller irq is unused (when not provided, default is 0)
+
Examples:
crossbar_mpu: @4a020000 {
compatible = "ti,irq-crossbar";
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index 0533a71..4be30c0 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -23,16 +23,18 @@
/*
* @int_max: maximum number of supported interrupts
+ * @safe_map: safe default value to initialize the crossbar
* @irq_map: array of interrupts to crossbar number mapping
* @crossbar_base: crossbar base address
* @register_offsets: offsets for each irq number
*/
struct crossbar_device {
uint int_max;
+ uint safe_map;
uint *irq_map;
void __iomem *crossbar_base;
int *register_offsets;
- void (*write) (int, int);
+ void (*write)(int, int);
};
static struct crossbar_device *cb;
@@ -88,8 +90,10 @@ static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq)
{
irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq;
- if (hw > GIC_IRQ_START)
+ if (hw > GIC_IRQ_START) {
cb->irq_map[hw - GIC_IRQ_START] = IRQ_FREE;
+ cb->write(hw - GIC_IRQ_START, cb->safe_map);
+ }
}
static int crossbar_domain_xlate(struct irq_domain *d,
@@ -214,6 +218,17 @@ static int __init crossbar_of_init(struct device_node *node)
reserved += size;
}
+ of_property_read_u32(node, "ti,irqs-safe-map", &cb->safe_map);
+
+ /* Initialize the crossbar with safe map to start with */
+ for (i = 0; i < max; i++) {
+ if (cb->irq_map[i] == IRQ_RESERVED ||
+ cb->irq_map[i] == IRQ_SKIP)
+ continue;
+
+ cb->write(i, cb->safe_map);
+ }
+
register_routable_domain_ops(&routable_irq_domain_ops);
return 0;
--
1.7.9.5
From: Nishanth Menon <[email protected]>
Reverse the search algorithm to ensure that address mapping and IRQ
allocation logics are proper. This makes the below bugs visible sooner.
class 1. address space errors -> example:
reg = <a size_b>
ti,max-irqs = is a wrong parameter
class 2: irq-reserved list - which decides which entries in the
address space is not actually wired in
class 3: wrong list of routable-irqs.
In general allocating from max to min tends to have benefits in
ensuring the different issues that may be present in dts is easily
caught at definition time, rather than at a later point in time.
Signed-off-by: Nishanth Menon <[email protected]>
Signed-off-by: Sricharan R <[email protected]>
Acked-by: Santosh Shilimkar <[email protected]>
---
drivers/irqchip/irq-crossbar.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index 4be30c0..a39cb31 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -58,7 +58,7 @@ static inline int get_prev_map_irq(int cb_no)
{
int i;
- for (i = 0; i < cb->int_max; i++)
+ for (i = cb->int_max - 1; i >= 0; i--)
if (cb->irq_map[i] == cb_no)
return i;
@@ -69,7 +69,7 @@ static inline int allocate_free_irq(int cb_no)
{
int i;
- for (i = 0; i < cb->int_max; i++) {
+ for (i = cb->int_max - 1; i >= 0; i--) {
if (cb->irq_map[i] == IRQ_FREE) {
cb->irq_map[i] = cb_no;
return i;
--
1.7.9.5
From: Nishanth Menon <[email protected]>
Adding missing properties for kerneldoc (@write) and cleanup
of harmless warnings while we are here.
kerneldoc warnings:
Warning(drivers/irqchip/irq-crossbar.c:27): missing initial short description on line:
* struct crossbar_device: crossbar device description
Info(drivers/irqchip/irq-crossbar.c:27): Scanning doc for struct
Warning(drivers/irqchip/irq-crossbar.c:39): No description found for parameter 'write'
2 warnings
Signed-off-by: Nishanth Menon <[email protected]>
Signed-off-by: Sricharan R <[email protected]>
Acked-by: Santosh Shilimkar <[email protected]>
---
drivers/irqchip/irq-crossbar.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index f7eda9f..cee556b 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -22,12 +22,14 @@
#define IRQ_SKIP -3
#define GIC_IRQ_START 32
-/*
+/**
+ * struct crossbar_device - crossbar device description
* @int_max: maximum number of supported interrupts
* @safe_map: safe default value to initialize the crossbar
* @irq_map: array of interrupts to crossbar number mapping
* @crossbar_base: crossbar base address
* @register_offsets: offsets for each irq number
+ * @write: register write function pointer
*/
struct crossbar_device {
uint int_max;
--
1.7.9.5
If crossbar_of_init returns with a error, then set the cb pointer
to null.
Signed-off-by: Sricharan R <[email protected]>
Acked-by: Santosh Shilimkar <[email protected]>
---
drivers/irqchip/irq-crossbar.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index afc35fd..a8c6156 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -250,6 +250,8 @@ err_base:
iounmap(cb->crossbar_base);
err_cb:
kfree(cb);
+
+ cb = NULL;
return ret;
}
--
1.7.9.5
Adding kerneldoc for unmap callback function.
Signed-off-by: Sricharan R <[email protected]>
Acked-by: Santosh Shilimkar <[email protected]>
---
drivers/irqchip/irq-crossbar.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index a8c6156..518d712 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -89,6 +89,17 @@ static int crossbar_domain_map(struct irq_domain *d, unsigned int irq,
return 0;
}
+/**
+ * crossbar_domain_unmap - unmap a crossbar<->irq connection
+ * @d: domain of irq to unmap
+ * @irq: virq number
+ *
+ * We do not maintain a use count of total number of map/unmap
+ * calls for a particular irq to find out if a irq can be really
+ * unmapped. This is because unmap is called during irq_dispose_mapping(irq),
+ * after which irq is anyways unusable. So an explicit map has to be called
+ * after that.
+ */
static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq)
{
irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq;
--
1.7.9.5
From: Nishanth Menon <[email protected]>
This is a basic check to ensure that crossbar register needs to be
written. This ensures that we have a common check which is used in
both map and unmap logic.
Signed-off-by: Nishanth Menon <[email protected]>
Signed-off-by: Sricharan R <[email protected]>
Acked-by: Santosh Shilimkar <[email protected]>
---
drivers/irqchip/irq-crossbar.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index c9f068c..83f803b 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -84,10 +84,20 @@ static inline int allocate_free_irq(int cb_no)
return -ENODEV;
}
+static inline bool needs_crossbar_write(irq_hw_number_t hw)
+{
+ if (hw > GIC_IRQ_START)
+ return true;
+
+ return false;
+}
+
static int crossbar_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hw)
{
- cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]);
+ if (needs_crossbar_write(hw))
+ cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]);
+
return 0;
}
@@ -106,7 +116,7 @@ static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq)
{
irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq;
- if (hw > GIC_IRQ_START) {
+ if (needs_crossbar_write(hw)) {
cb->irq_map[hw - GIC_IRQ_START] = IRQ_FREE;
cb->write(hw - GIC_IRQ_START, cb->safe_map);
}
--
1.7.9.5
From: Nishanth Menon <[email protected]>
The current crossbar description does not include the description
required for the consumer of the crossbar, a.k.a devices whoes events
pass through the crossbar into the GIC interrupt controller.
So, provide documentation for the same.
Signed-off-by: Nishanth Menon <[email protected]>
Signed-off-by: Sricharan R <[email protected]>
Acked-by: Santosh Shilimkar <[email protected]>
---
.../devicetree/bindings/arm/omap/crossbar.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
index 6923531..35356b6 100644
--- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -36,3 +36,20 @@ Examples:
ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
ti,irqs-skip = <10 133 139 140>;
};
+
+Consumer:
+========
+See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
+Documentation/devicetree/bindings/arm/gic.txt for further details.
+
+An interrupt consumer on an SoC using crossbar will use:
+ interrupts = <GIC_SPI request_number interrupt_level>
+request number shall be between 0 to that described by
+"ti,max-crossbar-sources"
+
+Example:
+ device_x@0x4a023000 {
+ /* Crossbar 8 used */
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ ...
+ };
--
1.7.9.5
From: Nishanth Menon <[email protected]>
On certain platforms such as DRA7, SPIs 0, 1, 2, 3, 5, 6, 10, 131,
132, 133 are direct wired to hardware blocks bypassing crossbar.
This quirky implementation is *NOT* supposed to be the expectation
of crossbar hardware usage. However, these are already marked in our
description of the hardware with SKIP and RESERVED where appropriate.
Unfortunately, we need to be able to refer to these hardwired IRQs.
So, to request these, crossbar driver can use the existing information
from it's table that these SKIP/RESERVED maps are direct wired sources
and generic allocation/programming of crossbar should be avoided.
Signed-off-by: Nishanth Menon <[email protected]>
Signed-off-by: Sricharan R <[email protected]>
Acked-by: Santosh Shilimkar <[email protected]>
---
.../devicetree/bindings/arm/omap/crossbar.txt | 12 ++++++++++--
drivers/irqchip/irq-crossbar.c | 20 ++++++++++++++++++--
2 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
index 35356b6..51a85c3 100644
--- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -44,8 +44,10 @@ Documentation/devicetree/bindings/arm/gic.txt for further details.
An interrupt consumer on an SoC using crossbar will use:
interrupts = <GIC_SPI request_number interrupt_level>
-request number shall be between 0 to that described by
-"ti,max-crossbar-sources"
+When the request number is between 0 to that described by
+"ti,max-crossbar-sources", it is assumed to be a crossbar mapping. If the
+request_number is greater than "ti,max-crossbar-sources", then it is mapped as a
+quirky hardware mapping direct to GIC.
Example:
device_x@0x4a023000 {
@@ -53,3 +55,9 @@ Example:
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
...
};
+
+ device_y@0x4a033000 {
+ /* Direct mapped GIC SPI 1 used */
+ interrupts = <GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH>;
+ ...
+ };
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index 83f803b..85c2985 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -86,8 +86,13 @@ static inline int allocate_free_irq(int cb_no)
static inline bool needs_crossbar_write(irq_hw_number_t hw)
{
- if (hw > GIC_IRQ_START)
- return true;
+ int cb_no;
+
+ if (hw > GIC_IRQ_START) {
+ cb_no = cb->irq_map[hw - GIC_IRQ_START];
+ if (cb_no != IRQ_RESERVED && cb_no != IRQ_SKIP)
+ return true;
+ }
return false;
}
@@ -130,8 +135,19 @@ static int crossbar_domain_xlate(struct irq_domain *d,
{
int ret;
int req_num = intspec[1];
+ int direct_map_num;
if (req_num >= cb->max_crossbar_sources) {
+ direct_map_num = req_num - cb->max_crossbar_sources;
+ if (direct_map_num < cb->int_max) {
+ ret = cb->irq_map[direct_map_num];
+ if (ret == IRQ_RESERVED || ret == IRQ_SKIP) {
+ /* We use the interrupt num as h/w irq num */
+ ret = direct_map_num;
+ goto found;
+ }
+ }
+
pr_err("%s: requested crossbar number %d > max %d\n",
__func__, req_num, cb->max_crossbar_sources);
return -EINVAL;
--
1.7.9.5
From: Nishanth Menon <[email protected]>
Currently we attempt to map any crossbar value to an IRQ, however,
this is not correct from hardware perspective. There is a max crossbar
event number upto which hardware supports. So describe the same in
device tree using 'ti,max-crossbar-sources' property and use it to
validate requests.
Signed-off-by: Nishanth Menon <[email protected]>
Signed-off-by: Sricharan R <[email protected]>
Acked-by: Santosh Shilimkar <[email protected]>
---
.../devicetree/bindings/arm/omap/crossbar.txt | 2 ++
drivers/irqchip/irq-crossbar.c | 21 ++++++++++++++++++--
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
index 5f45c78..6923531 100644
--- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -10,6 +10,7 @@ Required properties:
- compatible : Should be "ti,irq-crossbar"
- reg: Base address and the size of the crossbar registers.
- ti,max-irqs: Total number of irqs available at the interrupt controller.
+- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
- ti,reg-size: Size of a individual register in bytes. Every individual
register is assumed to be of same size. Valid sizes are 1, 2, 4.
- ti,irqs-reserved: List of the reserved irq lines that are not muxed using
@@ -30,6 +31,7 @@ Examples:
compatible = "ti,irq-crossbar";
reg = <0x4a002a48 0x130>;
ti,max-irqs = <160>;
+ ti,max-crossbar-sources = <MAX_SOURCES>;
ti,reg-size = <2>;
ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
ti,irqs-skip = <10 133 139 140>;
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index 518d712..c9f068c 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -26,6 +26,7 @@
* struct crossbar_device - crossbar device description
* @int_max: maximum number of supported interrupts
* @safe_map: safe default value to initialize the crossbar
+ * @max_crossbar_sources: Maximum number of crossbar sources
* @irq_map: array of interrupts to crossbar number mapping
* @crossbar_base: crossbar base address
* @register_offsets: offsets for each irq number
@@ -34,6 +35,7 @@
struct crossbar_device {
uint int_max;
uint safe_map;
+ uint max_crossbar_sources;
uint *irq_map;
void __iomem *crossbar_base;
int *register_offsets;
@@ -117,12 +119,19 @@ static int crossbar_domain_xlate(struct irq_domain *d,
unsigned int *out_type)
{
int ret;
+ int req_num = intspec[1];
- ret = get_prev_map_irq(intspec[1]);
+ if (req_num >= cb->max_crossbar_sources) {
+ pr_err("%s: requested crossbar number %d > max %d\n",
+ __func__, req_num, cb->max_crossbar_sources);
+ return -EINVAL;
+ }
+
+ ret = get_prev_map_irq(req_num);
if (ret >= 0)
goto found;
- ret = allocate_free_irq(intspec[1]);
+ ret = allocate_free_irq(req_num);
if (ret < 0)
return ret;
@@ -153,6 +162,14 @@ static int __init crossbar_of_init(struct device_node *node)
if (!cb->crossbar_base)
goto err_cb;
+ of_property_read_u32(node, "ti,max-crossbar-sources",
+ &cb->max_crossbar_sources);
+ if (!cb->max_crossbar_sources) {
+ pr_err("missing 'ti,max-crossbar-sources' property\n");
+ ret = -EINVAL;
+ goto err_base;
+ }
+
of_property_read_u32(node, "ti,max-irqs", &max);
if (!max) {
pr_err("missing 'ti,max-irqs' property\n");
--
1.7.9.5
From: Nishanth Menon <[email protected]>
Using err1,2,3,4 etc makes it hard to ensure a new exit path in the
middle will not result in spurious changes, so rename the error paths
as per the function it does.
Signed-off-by: Nishanth Menon <[email protected]>
Signed-off-by: Sricharan R <[email protected]>
Acked-by: Santosh Shilimkar <[email protected]>
---
drivers/irqchip/irq-crossbar.c | 23 +++++++++++------------
1 file changed, 11 insertions(+), 12 deletions(-)
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index 10d723d..afc35fd 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -140,17 +140,17 @@ static int __init crossbar_of_init(struct device_node *node)
cb->crossbar_base = of_iomap(node, 0);
if (!cb->crossbar_base)
- goto err1;
+ goto err_cb;
of_property_read_u32(node, "ti,max-irqs", &max);
if (!max) {
pr_err("missing 'ti,max-irqs' property\n");
ret = -EINVAL;
- goto err2;
+ goto err_base;
}
cb->irq_map = kcalloc(max, sizeof(int), GFP_KERNEL);
if (!cb->irq_map)
- goto err2;
+ goto err_base;
cb->int_max = max;
@@ -169,7 +169,7 @@ static int __init crossbar_of_init(struct device_node *node)
if (entry > max) {
pr_err("Invalid reserved entry\n");
ret = -EINVAL;
- goto err3;
+ goto err_irq_map;
}
cb->irq_map[entry] = IRQ_RESERVED;
}
@@ -187,7 +187,7 @@ static int __init crossbar_of_init(struct device_node *node)
if (entry > max) {
pr_err("Invalid skip entry\n");
ret = -EINVAL;
- goto err3;
+ goto err_irq_map;
}
cb->irq_map[entry] = IRQ_SKIP;
}
@@ -196,7 +196,7 @@ static int __init crossbar_of_init(struct device_node *node)
cb->register_offsets = kcalloc(max, sizeof(int), GFP_KERNEL);
if (!cb->register_offsets)
- goto err3;
+ goto err_irq_map;
of_property_read_u32(node, "ti,reg-size", &size);
@@ -213,7 +213,7 @@ static int __init crossbar_of_init(struct device_node *node)
default:
pr_err("Invalid reg-size property\n");
ret = -EINVAL;
- goto err4;
+ goto err_reg_offset;
break;
}
@@ -230,7 +230,6 @@ static int __init crossbar_of_init(struct device_node *node)
}
of_property_read_u32(node, "ti,irqs-safe-map", &cb->safe_map);
-
/* Initialize the crossbar with safe map to start with */
for (i = 0; i < max; i++) {
if (cb->irq_map[i] == IRQ_RESERVED ||
@@ -243,13 +242,13 @@ static int __init crossbar_of_init(struct device_node *node)
register_routable_domain_ops(&routable_irq_domain_ops);
return 0;
-err4:
+err_reg_offset:
kfree(cb->register_offsets);
-err3:
+err_irq_map:
kfree(cb->irq_map);
-err2:
+err_base:
iounmap(cb->crossbar_base);
-err1:
+err_cb:
kfree(cb);
return ret;
}
--
1.7.9.5
From: Nishanth Menon <[email protected]>
There is absolutely no need for crossbar driver to expose functions and
variables into global namespace. So make them all static
Also fix a couple of checkpatch warnings.
Fixes sparse warnings:
drivers/irqchip/irq-crossbar.c:129:29: warning: symbol 'routable_irq_domain_ops' was not declared. Should it be static?
drivers/irqchip/irq-crossbar.c:261:12: warning: symbol 'irqcrossbar_init' was not declared. Should it be static?
Checkpatch warnings:
WARNING: Prefer kcalloc over kzalloc with multiply
+ cb->irq_map = kzalloc(max * sizeof(int), GFP_KERNEL);
WARNING: Prefer kcalloc over kzalloc with multiply
+ cb->register_offsets = kzalloc(max * sizeof(int), GFP_KERNEL);
Signed-off-by: Nishanth Menon <[email protected]>
Signed-off-by: Sricharan R <[email protected]>
Acked-by: Santosh Shilimkar <[email protected]>
---
drivers/irqchip/irq-crossbar.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index 88fbe0f..f7eda9f 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -15,6 +15,7 @@
#include <linux/of_irq.h>
#include <linux/slab.h>
#include <linux/irqchip/arm-gic.h>
+#include <linux/irqchip/irq-crossbar.h>
#define IRQ_FREE -1
#define IRQ_RESERVED -2
@@ -118,7 +119,7 @@ found:
return 0;
}
-const struct irq_domain_ops routable_irq_domain_ops = {
+static const struct irq_domain_ops routable_irq_domain_ops = {
.map = crossbar_domain_map,
.unmap = crossbar_domain_unmap,
.xlate = crossbar_domain_xlate
@@ -139,7 +140,7 @@ static int __init crossbar_of_init(struct device_node *node)
goto err1;
of_property_read_u32(node, "ti,max-irqs", &max);
- cb->irq_map = kzalloc(max * sizeof(int), GFP_KERNEL);
+ cb->irq_map = kcalloc(max, sizeof(int), GFP_KERNEL);
if (!cb->irq_map)
goto err2;
@@ -184,7 +185,7 @@ static int __init crossbar_of_init(struct device_node *node)
}
- cb->register_offsets = kzalloc(max * sizeof(int), GFP_KERNEL);
+ cb->register_offsets = kcalloc(max, sizeof(int), GFP_KERNEL);
if (!cb->register_offsets)
goto err3;
--
1.7.9.5
From: Nishanth Menon <[email protected]>
crossbar_of_init always returns -ENOMEM in case of errors.
There can be other causes of failure like invalid data from
DT. So return a appropriate error value for that case.
Signed-off-by: Nishanth Menon <[email protected]>
Signed-off-by: Sricharan R <[email protected]>
Acked-by: Santosh Shilimkar <[email protected]>
---
drivers/irqchip/irq-crossbar.c | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index cee556b..10d723d 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -129,19 +129,25 @@ static const struct irq_domain_ops routable_irq_domain_ops = {
static int __init crossbar_of_init(struct device_node *node)
{
- int i, size, max, reserved = 0, entry;
+ int i, size, max = 0, reserved = 0, entry;
const __be32 *irqsr;
+ int ret = -ENOMEM;
cb = kzalloc(sizeof(*cb), GFP_KERNEL);
if (!cb)
- return -ENOMEM;
+ return ret;
cb->crossbar_base = of_iomap(node, 0);
if (!cb->crossbar_base)
goto err1;
of_property_read_u32(node, "ti,max-irqs", &max);
+ if (!max) {
+ pr_err("missing 'ti,max-irqs' property\n");
+ ret = -EINVAL;
+ goto err2;
+ }
cb->irq_map = kcalloc(max, sizeof(int), GFP_KERNEL);
if (!cb->irq_map)
goto err2;
@@ -162,6 +168,7 @@ static int __init crossbar_of_init(struct device_node *node)
i, &entry);
if (entry > max) {
pr_err("Invalid reserved entry\n");
+ ret = -EINVAL;
goto err3;
}
cb->irq_map[entry] = IRQ_RESERVED;
@@ -205,6 +212,7 @@ static int __init crossbar_of_init(struct device_node *node)
break;
default:
pr_err("Invalid reg-size property\n");
+ ret = -EINVAL;
goto err4;
break;
}
@@ -243,7 +251,7 @@ err2:
iounmap(cb->crossbar_base);
err1:
kfree(cb);
- return -ENOMEM;
+ return ret;
}
static const struct of_device_id crossbar_match[] __initconst = {
--
1.7.9.5
From: Nishanth Menon <[email protected]>
IS_ERR_VALUE makes sense only *if* there could be valid values in
negative error range. But in the cases that we do use it, there is no
such case. Just remove the same.
Signed-off-by: Nishanth Menon <[email protected]>
Signed-off-by: Sricharan R <[email protected]>
Acked-by: Santosh Shilimkar <[email protected]>
---
drivers/irqchip/irq-crossbar.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index a39cb31..88fbe0f 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -102,15 +102,15 @@ static int crossbar_domain_xlate(struct irq_domain *d,
unsigned long *out_hwirq,
unsigned int *out_type)
{
- unsigned long ret;
+ int ret;
ret = get_prev_map_irq(intspec[1]);
- if (!IS_ERR_VALUE(ret))
+ if (ret >= 0)
goto found;
ret = allocate_free_irq(intspec[1]);
- if (IS_ERR_VALUE(ret))
+ if (ret < 0)
return ret;
found:
--
1.7.9.5
From: Nishanth Menon <[email protected]>
If irq_of_parse_and_map is executed twice, the same crossbar is mapped to two
different GIC interrupts. This is completely undesirable. Instead, check
if the requested crossbar event is pre-allocated and provide that GIC
mapping back to caller if already allocated.
Signed-off-by: Nishanth Menon <[email protected]>
Signed-off-by: Sricharan R <[email protected]>
Acked-by: Santosh Shilimkar <[email protected]>
---
drivers/irqchip/irq-crossbar.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index 20105bc..51d4b87 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -51,6 +51,17 @@ static inline void crossbar_writeb(int irq_no, int cb_no)
writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
}
+static inline int get_prev_map_irq(int cb_no)
+{
+ int i;
+
+ for (i = 0; i < cb->int_max; i++)
+ if (cb->irq_map[i] == cb_no)
+ return i;
+
+ return -ENODEV;
+}
+
static inline int allocate_free_irq(int cb_no)
{
int i;
@@ -88,11 +99,16 @@ static int crossbar_domain_xlate(struct irq_domain *d,
{
unsigned long ret;
+ ret = get_prev_map_irq(intspec[1]);
+ if (!IS_ERR_VALUE(ret))
+ goto found;
+
ret = allocate_free_irq(intspec[1]);
if (IS_ERR_VALUE(ret))
return ret;
+found:
*out_hwirq = ret + GIC_IRQ_START;
return 0;
}
--
1.7.9.5
From: Nishanth Menon <[email protected]>
When, in the system due to varied reasons, interrupts might be unusable
due to hardware behavior, but register maps do exist, then those interrupts
should be skipped while mapping irq to crossbars.
Signed-off-by: Nishanth Menon <[email protected]>
Signed-off-by: Sricharan R <[email protected]>
Acked-by: Santosh Shilimkar <[email protected]>
---
.../devicetree/bindings/arm/omap/crossbar.txt | 6 ++++++
drivers/irqchip/irq-crossbar.c | 20 ++++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
index fb88585..0795765 100644
--- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -17,6 +17,11 @@ Required properties:
so crossbar bar driver should not consider them as free
lines.
+Optional properties:
+- ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for
+ SOC-specific hard-wiring of those irqs which unexpectedly bypasses the
+ crossbar. These irqs have a crossbar register, but still cannot be used.
+
Examples:
crossbar_mpu: @4a020000 {
compatible = "ti,irq-crossbar";
@@ -24,4 +29,5 @@ Examples:
ti,max-irqs = <160>;
ti,reg-size = <2>;
ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
+ ti,irqs-skip = <10 133 139 140>;
};
diff --git a/drivers/irqchip/irq-crossbar.c b/drivers/irqchip/irq-crossbar.c
index 51d4b87..0533a71 100644
--- a/drivers/irqchip/irq-crossbar.c
+++ b/drivers/irqchip/irq-crossbar.c
@@ -18,6 +18,7 @@
#define IRQ_FREE -1
#define IRQ_RESERVED -2
+#define IRQ_SKIP -3
#define GIC_IRQ_START 32
/*
@@ -160,6 +161,25 @@ static int __init crossbar_of_init(struct device_node *node)
}
}
+ /* Skip irqs hardwired to bypass the crossbar */
+ irqsr = of_get_property(node, "ti,irqs-skip", &size);
+ if (irqsr) {
+ size /= sizeof(__be32);
+
+ for (i = 0; i < size; i++) {
+ of_property_read_u32_index(node,
+ "ti,irqs-skip",
+ i, &entry);
+ if (entry > max) {
+ pr_err("Invalid skip entry\n");
+ ret = -EINVAL;
+ goto err3;
+ }
+ cb->irq_map[entry] = IRQ_SKIP;
+ }
+ }
+
+
cb->register_offsets = kzalloc(max * sizeof(int), GFP_KERNEL);
if (!cb->register_offsets)
goto err3;
--
1.7.9.5
* Sricharan R <[email protected]> [140626 00:14]:
> This series does some cleanups, fixes for handling two interrupts
> getting mapped twice to same crossbar and provides support for
> hardwired IRQ and crossbar definitions.
>
> On certain platforms such as DRA7, SPIs 0, 1, 2, 3, 5, 6, 10,
> 131, 132, 133 are direct wired to hardware blocks bypassing
> crossbar. This quirky implementation is *NOT* supposed to be the
> expectation of crossbar hardware usage. This series adds support
> to represent such hard-wired irqs through DT and avoid generic
> allocation/programming of crossbar in the driver.
>
> This way of supporting hard-wired irqs was a result of
> the below discussions.
> http://www.spinics.net/lists/arm-kernel/msg329946.html
>
> Based on 3.16 rc2 mainline.
Jason, once these patches look OK for merging, can you please
set them up into an immutable branch so I too can merge them in?
The immutable branch is needed so I can eventually apply
the related .dts changes to enable the crossbar interrupts.
Regards,
Tony
On Thu, Jun 26, 2014 at 12:40:33PM +0530, Sricharan R wrote:
> From: Nishanth Menon <[email protected]>
>
> The current crossbar description does not include the description
> required for the consumer of the crossbar, a.k.a devices whoes events
> pass through the crossbar into the GIC interrupt controller.
>
> So, provide documentation for the same.
>
> Signed-off-by: Nishanth Menon <[email protected]>
> Signed-off-by: Sricharan R <[email protected]>
> Acked-by: Santosh Shilimkar <[email protected]>
> ---
> .../devicetree/bindings/arm/omap/crossbar.txt | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
> index 6923531..35356b6 100644
> --- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
> +++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
> @@ -36,3 +36,20 @@ Examples:
> ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
> ti,irqs-skip = <10 133 139 140>;
> };
> +
> +Consumer:
> +========
> +See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
> +Documentation/devicetree/bindings/arm/gic.txt for further details.
> +
> +An interrupt consumer on an SoC using crossbar will use:
> + interrupts = <GIC_SPI request_number interrupt_level>
> +request number shall be between 0 to that described by
> +"ti,max-crossbar-sources"
> +
> +Example:
> + device_x@0x4a023000 {
> + /* Crossbar 8 used */
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
If you are going to reference MAX_SOURCES in the previous patch to the
docs, then you should use the macro here as well and explain both. Or,
just use numbers in the docs, and macros in the dtsi files.
If you prefer the latter, just let me know and I'll fixup the other
patch when applying these. Otherwise, you can just send a v5 of the two
patches affected.
thx,
Jason.
On Thu, Jun 26, 2014 at 12:40:31PM +0530, Sricharan R wrote:
> From: Nishanth Menon <[email protected]>
>
> Currently we attempt to map any crossbar value to an IRQ, however,
> this is not correct from hardware perspective. There is a max crossbar
> event number upto which hardware supports. So describe the same in
> device tree using 'ti,max-crossbar-sources' property and use it to
> validate requests.
>
> Signed-off-by: Nishanth Menon <[email protected]>
> Signed-off-by: Sricharan R <[email protected]>
> Acked-by: Santosh Shilimkar <[email protected]>
> ---
> .../devicetree/bindings/arm/omap/crossbar.txt | 2 ++
> drivers/irqchip/irq-crossbar.c | 21 ++++++++++++++++++--
> 2 files changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
> index 5f45c78..6923531 100644
> --- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
> +++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
> @@ -10,6 +10,7 @@ Required properties:
> - compatible : Should be "ti,irq-crossbar"
> - reg: Base address and the size of the crossbar registers.
> - ti,max-irqs: Total number of irqs available at the interrupt controller.
> +- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
> - ti,reg-size: Size of a individual register in bytes. Every individual
> register is assumed to be of same size. Valid sizes are 1, 2, 4.
> - ti,irqs-reserved: List of the reserved irq lines that are not muxed using
> @@ -30,6 +31,7 @@ Examples:
> compatible = "ti,irq-crossbar";
> reg = <0x4a002a48 0x130>;
> ti,max-irqs = <160>;
> + ti,max-crossbar-sources = <MAX_SOURCES>;
As mentioned in my reply to #15, I can change this to 400 when I apply
it, or you can send a new version of #15 using the macro and explaining
it's definition.
Thinking about it more, it's probably best just to use numbers in the
docs.
thx,
Jason.
On Thu, Jun 26, 2014 at 12:42:09AM -0700, Tony Lindgren wrote:
> * Sricharan R <[email protected]> [140626 00:14]:
> > This series does some cleanups, fixes for handling two interrupts
> > getting mapped twice to same crossbar and provides support for
> > hardwired IRQ and crossbar definitions.
> >
> > On certain platforms such as DRA7, SPIs 0, 1, 2, 3, 5, 6, 10,
> > 131, 132, 133 are direct wired to hardware blocks bypassing
> > crossbar. This quirky implementation is *NOT* supposed to be the
> > expectation of crossbar hardware usage. This series adds support
> > to represent such hard-wired irqs through DT and avoid generic
> > allocation/programming of crossbar in the driver.
> >
> > This way of supporting hard-wired irqs was a result of
> > the below discussions.
> > http://www.spinics.net/lists/arm-kernel/msg329946.html
> >
> > Based on 3.16 rc2 mainline.
>
> Jason, once these patches look OK for merging, can you please
> set them up into an immutable branch so I too can merge them in?
Sure thing.
thx,
Jason.
On Thu, Jun 26, 2014 at 12:40:18PM +0530, Sricharan R wrote:
> This series does some cleanups, fixes for handling two interrupts
> getting mapped twice to same crossbar and provides support for
> hardwired IRQ and crossbar definitions.
>
> On certain platforms such as DRA7, SPIs 0, 1, 2, 3, 5, 6, 10,
> 131, 132, 133 are direct wired to hardware blocks bypassing
> crossbar. This quirky implementation is *NOT* supposed to be the
> expectation of crossbar hardware usage. This series adds support
> to represent such hard-wired irqs through DT and avoid generic
> allocation/programming of crossbar in the driver.
>
> This way of supporting hard-wired irqs was a result of
> the below discussions.
> http://www.spinics.net/lists/arm-kernel/msg329946.html
>
> Based on 3.16 rc2 mainline.
>
> All the patches are available here
> [email protected]:Sricharanti/sricharan.git crossbar_updates
>
> The fixes series[1] earlier posted is merged in to this.
> [1] http://www.spinics.net/lists/arm-kernel/msg328273.html
>
> [V2] Merged the above series and rebased on 3.15 mainline
>
> [V3] Modified patch#3 to get irqs-skip properties from DT,
> merged path#8 for checkpatch warning to other relevant
> patches and fixed comments for other patches.
>
> [V4] Based on 3.16rc2 and fixed Jason's <[email protected]> comments.
>
> Nishanth Menon (14):
> irqchip: crossbar: Dont use '0' to mark reserved interrupts
> irqchip: crossbar: Check for premapped crossbar before allocating
> irqchip: crossbar: Introduce ti,irqs-skip to skip irqs that bypass
> crossbar
> irqchip: crossbar: Initialise the crossbar with a safe value
> irqchip: crossbar: Change allocation logic by reversing search for
> free irqs
> irqchip: crossbar: Remove IS_ERR_VALUE check
> irqchip: crossbar: Fix sparse and checkpatch warnings
> irqchip: crossbar: Fix kerneldoc warning
> irqchip: crossbar: Return proper error value
> irqchip: crossbar: Change the goto naming
> irqchip: crossbar: Introduce ti,max-crossbar-sources to identify
> valid crossbar mapping
> irqchip: crossbar: Introduce centralized check for crossbar write
> documentation: dt: omap: crossbar: Add description for interrupt
> consumer
> irqchip: crossbar: Allow for quirky hardware with direct hardwiring
> of GIC
>
> Sricharan R (2):
> irqchip: crossbar: Set cb pointer to null in case of error
> irqchip: crossbar: Add kerneldoc for crossbar_domain_unmap callback
>
> .../devicetree/bindings/arm/omap/crossbar.txt | 36 +++++
> drivers/irqchip/irq-crossbar.c | 168 +++++++++++++++++---
> 2 files changed, 179 insertions(+), 25 deletions(-)
Whole series applied to irqchip/crossbar, I'll give it a day or two in
-next, then I'll merge it into irqchip/core.
Tony: Right now, it's immutable unless you tell me I applied something
incorrectly. Once it goes into irqchip/core, it's immutable no matter
what you say. ;-)
thx,
Jason.
On Fri, Jun 27, 2014 at 08:00:35AM -0400, Jason Cooper wrote:
> On Thu, Jun 26, 2014 at 12:40:31PM +0530, Sricharan R wrote:
> > From: Nishanth Menon <[email protected]>
> >
> > Currently we attempt to map any crossbar value to an IRQ, however,
> > this is not correct from hardware perspective. There is a max crossbar
> > event number upto which hardware supports. So describe the same in
> > device tree using 'ti,max-crossbar-sources' property and use it to
> > validate requests.
> >
> > Signed-off-by: Nishanth Menon <[email protected]>
> > Signed-off-by: Sricharan R <[email protected]>
> > Acked-by: Santosh Shilimkar <[email protected]>
> > ---
> > .../devicetree/bindings/arm/omap/crossbar.txt | 2 ++
> > drivers/irqchip/irq-crossbar.c | 21 ++++++++++++++++++--
> > 2 files changed, 21 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
> > index 5f45c78..6923531 100644
> > --- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
> > +++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
> > @@ -10,6 +10,7 @@ Required properties:
> > - compatible : Should be "ti,irq-crossbar"
> > - reg: Base address and the size of the crossbar registers.
> > - ti,max-irqs: Total number of irqs available at the interrupt controller.
> > +- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
> > - ti,reg-size: Size of a individual register in bytes. Every individual
> > register is assumed to be of same size. Valid sizes are 1, 2, 4.
> > - ti,irqs-reserved: List of the reserved irq lines that are not muxed using
> > @@ -30,6 +31,7 @@ Examples:
> > compatible = "ti,irq-crossbar";
> > reg = <0x4a002a48 0x130>;
> > ti,max-irqs = <160>;
> > + ti,max-crossbar-sources = <MAX_SOURCES>;
>
> As mentioned in my reply to #15, I can change this to 400 when I apply
> it, or you can send a new version of #15 using the macro and explaining
> it's definition.
>
> Thinking about it more, it's probably best just to use numbers in the
> docs.
I just did s/MAX_SOURCES/400/ when I applied this. We shouldn't be
polluting the binding docs with implementation details.
thx,
Jason.
* Jason Cooper <[email protected]> [140630 12:30]:
>
> Whole series applied to irqchip/crossbar, I'll give it a day or two in
> -next, then I'll merge it into irqchip/core.
>
> Tony: Right now, it's immutable unless you tell me I applied something
> incorrectly. Once it goes into irqchip/core, it's immutable no matter
> what you say. ;-)
Thanks, looks good to me. Sricharan and Nishant, can you please
check that we can now apply the related .dts changes on top of
Jason's branch at:
git://git.infradead.org/users/jcooper/linux.git irqchip/crossbar
Regards,
Tony
Hi Tony,
On Tuesday 01 July 2014 01:29 PM, Tony Lindgren wrote:
> * Jason Cooper <[email protected]> [140630 12:30]:
>>
>> Whole series applied to irqchip/crossbar, I'll give it a day or two in
>> -next, then I'll merge it into irqchip/core.
>>
>> Tony: Right now, it's immutable unless you tell me I applied something
>> incorrectly. Once it goes into irqchip/core, it's immutable no matter
>> what you say. ;-)
>
> Thanks, looks good to me. Sricharan and Nishant, can you please
> check that we can now apply the related .dts changes on top of
> Jason's branch at:
>
> git://git.infradead.org/users/jcooper/linux.git irqchip/crossbar
>
I applied the dts patches on top of this and it worked fine for
me on dra72 evm
Regards,
Sricharan
On Tue, Jul 01, 2014 at 03:06:36PM +0530, Sricharan R wrote:
> Hi Tony,
>
> On Tuesday 01 July 2014 01:29 PM, Tony Lindgren wrote:
> > * Jason Cooper <[email protected]> [140630 12:30]:
> >>
> >> Whole series applied to irqchip/crossbar, I'll give it a day or two in
> >> -next, then I'll merge it into irqchip/core.
> >>
> >> Tony: Right now, it's immutable unless you tell me I applied something
> >> incorrectly. Once it goes into irqchip/core, it's immutable no matter
> >> what you say. ;-)
> >
> > Thanks, looks good to me. Sricharan and Nishant, can you please
> > check that we can now apply the related .dts changes on top of
> > Jason's branch at:
> >
> > git://git.infradead.org/users/jcooper/linux.git irqchip/crossbar
> >
>
> I applied the dts patches on top of this and it worked fine for
> me on dra72 evm
Awesome, thanks. irqchip/crossbar has been merged into irqchip/core.
thx,
Jason.