Hello Kukjin,
This series adds support for the remaining peripherals that were not
supported in the Exynos5420 Peach Pit and Exynos5800 Peach Pi boards.
Javier Martinez Canillas (2):
ARM: dts: Mux XMMCnDATA[0] pad correctly for Exynos5420 boards.
ARM: dts: Add WiFi module support for Peach boards
Tushar Behera (1):
ARM: dts: Add mclk entry for Peach Pit/Pi boards
arch/arm/boot/dts/exynos5420-arndale-octa.dts | 4 +-
arch/arm/boot/dts/exynos5420-peach-pit.dts | 62 ++++++++++++++++++++++++++-
arch/arm/boot/dts/exynos5420-smdk5420.dts | 4 +-
arch/arm/boot/dts/exynos5422-odroidxu3.dts | 4 +-
arch/arm/boot/dts/exynos5800-peach-pi.dts | 62 ++++++++++++++++++++++++++-
5 files changed, 126 insertions(+), 10 deletions(-)
Patch #1 is just a bugfix since the DTS was relying in the bootloader
to mux the XMMCnDATA[0] pad in function mode SD_n_DATA[0] for the uSD
and eMMC. The same bug was present in all Exynos5420/5422/5800 boards
probably due a difference in how the 5250 and 5420 pinctrl is defined.
Patch #2 adds support for the SDIO WiFi module present in Peach boards
and patch #3 adds a phandle for the audio codec master clock source.
After this series all the peripherals in the Peach boards are working
at least at a basic level, more work is needed to make the ASoC audio
driver more robust or the WiFi chip to support highspeed mode but that
can be made as a follow-up.
Best regards,
Javier
The Exynos5420 SoC has 3 sets of 8 pads used as data lines for the 3
MMC/SD/SDIO slots. These needs to be muxed as SD_n_DATA instead of a
GPIO or external interrupt to allow the MMC controller to communicate
with the attached cards or SDIO devices.
Which data lines needs to be muxed as SD_n_DATA depends on the bus
width used for data transfer:
* bus-width = <1> needs SD_n_DATA[0]
* bus-width = <4> needs SD_n_DATA[0-3]
* bus-width = <8> needs SD_n_DATA[0-7]
The Exynos5250-pinctrl.dtsi file that defines the groups of pins has
SD_n_DATA[0] muxed for both sdn_bus1 and sdn_bus4 so just one of them
needs to be included in the device node's pinctrl property.
But Exynos5420-pinctrl has a different definition and only includes
SD_n_DATA[1-3] for sdn_bus4. So for a bus-width = <4>, both sdn_bus1
and sdn_bus4 have to be in the dev pinctrl to mux all the needed pads.
It seems all Exynos5420 boards had just cargo cult the pinctrl lines
assuming that sdn_bus4 also included SD_n_DATA[0] and it only works
because the bootloader muxes the pads correctly. But that is not the
case for the devices not used by the bootloader such as WiFi modules.
Add sdn_bus1 too in the nodes pinctrl to not rely on the bootloader.
Suggested-by: Doug Anderson <[email protected]>
Signed-off-by: Javier Martinez Canillas <[email protected]>
---
arch/arm/boot/dts/exynos5420-arndale-octa.dts | 4 ++--
arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 ++--
arch/arm/boot/dts/exynos5420-smdk5420.dts | 4 ++--
arch/arm/boot/dts/exynos5422-odroidxu3.dts | 4 ++--
arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 ++--
5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index db2c1c4cd900..b82b6fa15f48 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -55,7 +55,7 @@
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
vmmc-supply = <&ldo10_reg>;
bus-width = <8>;
cap-mmc-highspeed;
@@ -68,7 +68,7 @@
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
vmmc-supply = <&ldo19_reg>;
vqmmc-supply = <&ldo13_reg>;
bus-width = <4>;
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index ec86d9523935..c4db5aed8a8c 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -687,7 +687,7 @@
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
bus-width = <8>;
};
@@ -701,7 +701,7 @@
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
bus-width = <4>;
};
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 8be3d7b489ff..7a56852efada 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -81,7 +81,7 @@
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
bus-width = <8>;
cap-mmc-highspeed;
};
@@ -93,7 +93,7 @@
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
bus-width = <4>;
cap-sd-highspeed;
};
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
index 790fb4ce295d..edc25cf1d717 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
@@ -312,7 +312,7 @@
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
bus-width = <8>;
cap-mmc-highspeed;
};
@@ -324,7 +324,7 @@
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
bus-width = <4>;
cap-sd-highspeed;
};
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 06737c60d333..ca73fb2d2da5 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -649,7 +649,7 @@
samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default";
- pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
bus-width = <8>;
};
@@ -663,7 +663,7 @@
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
bus-width = <4>;
};
--
2.1.3
Peach Pit and Pi boards have a WiFi module that is always powered
but needs toggling an enable pin and ungating a 32kHz reference
clock as part of their power sequencing.
Add a dev node for the SDIO slot and a MMC power sequence provider.
Signed-off-by: Javier Martinez Canillas <[email protected]>
---
arch/arm/boot/dts/exynos5420-peach-pit.dts | 56 ++++++++++++++++++++++++++++++
arch/arm/boot/dts/exynos5800-peach-pi.dts | 56 ++++++++++++++++++++++++++++++
2 files changed, 112 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index c4db5aed8a8c..80db9137abdd 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -125,6 +125,13 @@
};
};
};
+
+ mmc1_pwrseq: mmc1_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */
+ clocks = <&max77802 MAX77802_CLK_32K_CP>;
+ clock-names = "ext_clock";
+ };
};
&adc {
@@ -691,6 +698,25 @@
bus-width = <8>;
};
+&mmc_1 {
+ status = "okay";
+ num-slots = <1>;
+ broken-cd;
+ cap-sdio-irq;
+ card-detect-delay = <200>;
+ clock-frequency = <400000000>;
+ samsung,dw-mshc-ciu-div = <1>;
+ samsung,dw-mshc-sdr-timing = <0 1>;
+ samsung,dw-mshc-ddr-timing = <0 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>,
+ <&sd1_bus4>, <&sd1_bus8>, <&wifi_en>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ mmc-pwrseq = <&mmc1_pwrseq>;
+ vqmmc-supply = <&buck10_reg>;
+};
+
&mmc_2 {
status = "okay";
num-slots = <1>;
@@ -710,6 +736,13 @@
pinctrl-names = "default";
pinctrl-0 = <&mask_tpm_reset>;
+ wifi_en: wifi-en {
+ samsung,pins = "gpx0-0";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
max98090_irq: max98090-irq {
samsung,pins = "gpx0-2";
samsung,pin-function = <0>;
@@ -797,6 +830,29 @@
};
};
+&pinctrl_1 {
+ /* Adjust WiFi drive strengths lower for EMI */
+ sd1_clk: sd1-clk {
+ samsung,pin-drv = <2>;
+ };
+
+ sd1_cmd: sd1-cmd {
+ samsung,pin-drv = <2>;
+ };
+
+ sd1_bus1: sd1-bus-width1 {
+ samsung,pin-drv = <2>;
+ };
+
+ sd1_bus4: sd1-bus-width4 {
+ samsung,pin-drv = <2>;
+ };
+
+ sd1_bus8: sd1-bus-width8 {
+ samsung,pin-drv = <2>;
+ };
+};
+
&pinctrl_2 {
pmic_dvs_2: pmic-dvs-2 {
samsung,pins = "gpj4-2";
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index ca73fb2d2da5..9db2b5927821 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -119,6 +119,13 @@
power-supply = <&tps65090_fet6>;
backlight = <&backlight>;
};
+
+ mmc1_pwrseq: mmc1_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */
+ clocks = <&max77802 MAX77802_CLK_32K_CP>;
+ clock-names = "ext_clock";
+ };
};
&adc {
@@ -653,6 +660,25 @@
bus-width = <8>;
};
+&mmc_1 {
+ status = "okay";
+ num-slots = <1>;
+ broken-cd;
+ cap-sdio-irq;
+ card-detect-delay = <200>;
+ clock-frequency = <400000000>;
+ samsung,dw-mshc-ciu-div = <1>;
+ samsung,dw-mshc-sdr-timing = <0 1>;
+ samsung,dw-mshc-ddr-timing = <0 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_int>, <&sd1_bus1>,
+ <&sd1_bus4>, <&sd1_bus8>, <&wifi_en>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ mmc-pwrseq = <&mmc1_pwrseq>;
+ vqmmc-supply = <&buck10_reg>;
+};
+
&mmc_2 {
status = "okay";
num-slots = <1>;
@@ -672,6 +698,13 @@
pinctrl-names = "default";
pinctrl-0 = <&mask_tpm_reset>;
+ wifi_en: wifi-en {
+ samsung,pins = "gpx0-0";
+ samsung,pin-function = <1>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
max98091_irq: max98091-irq {
samsung,pins = "gpx0-2";
samsung,pin-function = <0>;
@@ -759,6 +792,29 @@
};
};
+&pinctrl_1 {
+ /* Adjust WiFi drive strengths lower for EMI */
+ sd1_clk: sd1-clk {
+ samsung,pin-drv = <2>;
+ };
+
+ sd1_cmd: sd1-cmd {
+ samsung,pin-drv = <2>;
+ };
+
+ sd1_bus1: sd1-bus-width1 {
+ samsung,pin-drv = <2>;
+ };
+
+ sd1_bus4: sd1-bus-width4 {
+ samsung,pin-drv = <2>;
+ };
+
+ sd1_bus8: sd1-bus-width8 {
+ samsung,pin-drv = <2>;
+ };
+};
+
&pinctrl_2 {
pmic_dvs_2: pmic-dvs-2 {
samsung,pins = "gpj4-2";
--
2.1.3
From: Tushar Behera <[email protected]>
On Peach Pit and Pi boards, the Exynos SoC XCLKOUT pin provides
master clock (mclk) to the codec. So make it a clock consumer.
Signed-off-by: Tushar Behera <[email protected]>
Signed-off-by: Javier Martinez Canillas <[email protected]>
---
arch/arm/boot/dts/exynos5420-peach-pit.dts | 2 ++
arch/arm/boot/dts/exynos5800-peach-pi.dts | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 80db9137abdd..d0ee55f4d09f 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -601,6 +601,8 @@
interrupt-parent = <&gpx0>;
pinctrl-names = "default";
pinctrl-0 = <&max98090_irq>;
+ clocks = <&pmu_system_controller 0>;
+ clock-names = "mclk";
};
light-sensor@44 {
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 9db2b5927821..7ea1d66dd719 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -588,6 +588,8 @@
interrupt-parent = <&gpx0>;
pinctrl-names = "default";
pinctrl-0 = <&max98091_irq>;
+ clocks = <&pmu_system_controller 0>;
+ clock-names = "mclk";
};
light-sensor@44 {
--
2.1.3
Javier Martinez Canillas wrote:
>
> Hello Kukjin,
>
Hi,
> This series adds support for the remaining peripherals that were not
> supported in the Exynos5420 Peach Pit and Exynos5800 Peach Pi boards.
>
> Javier Martinez Canillas (2):
> ARM: dts: Mux XMMCnDATA[0] pad correctly for Exynos5420 boards.
> ARM: dts: Add WiFi module support for Peach boards
>
> Tushar Behera (1):
> ARM: dts: Add mclk entry for Peach Pit/Pi boards
>
> arch/arm/boot/dts/exynos5420-arndale-octa.dts | 4 +-
> arch/arm/boot/dts/exynos5420-peach-pit.dts | 62 ++++++++++++++++++++++++++-
> arch/arm/boot/dts/exynos5420-smdk5420.dts | 4 +-
> arch/arm/boot/dts/exynos5422-odroidxu3.dts | 4 +-
> arch/arm/boot/dts/exynos5800-peach-pi.dts | 62 ++++++++++++++++++++++++++-
> 5 files changed, 126 insertions(+), 10 deletions(-)
>
> Patch #1 is just a bugfix since the DTS was relying in the bootloader
> to mux the XMMCnDATA[0] pad in function mode SD_n_DATA[0] for the uSD
> and eMMC. The same bug was present in all Exynos5420/5422/5800 boards
> probably due a difference in how the 5250 and 5420 pinctrl is defined.
>
> Patch #2 adds support for the SDIO WiFi module present in Peach boards
> and patch #3 adds a phandle for the audio codec master clock source.
>
> After this series all the peripherals in the Peach boards are working
> at least at a basic level, more work is needed to make the ASoC audio
> driver more robust or the WiFi chip to support highspeed mode but that
> can be made as a follow-up.
>
Sounds great and looks good to me after quick looking at this series.
Will apply this whole series.
Thanks,
Kukjin
Hello Kukjin,
On 02/26/2015 04:55 PM, Kukjin Kim wrote:
> Javier Martinez Canillas wrote:
>>
>> After this series all the peripherals in the Peach boards are working
>> at least at a basic level, more work is needed to make the ASoC audio
>> driver more robust or the WiFi chip to support highspeed mode but that
>> can be made as a follow-up.
>>
> Sounds great and looks good to me after quick looking at this series.
>
> Will apply this whole series.
>
Great, thanks a lot for your help.
> Thanks,
> Kukjin
>
Best regards,
Javier