This series fixes a few issues with the MIPS Coherent Processing System
SMP implementation, provides some extra capabilities with regards to
debug and does a little spring cleaning. A couple of the issues fixed
were introduced in v4.1-rc1 and (spuriously) marked for stable backports
as far as v3.16, so the fixes in this series are marked likewise.
Applies atop v4.2-rc5.
Paul Burton (6):
MIPS: CPS: use 32b accesses to GCRs
MIPS: CPS: stop dangling delay slot from has_mt
MIPS: CPS: don't include MT code in non-MT kernels
MIPS: CPS: #ifdef on CONFIG_MIPS_MT_SMP rather than CONFIG_MIPS_MT
MIPS: CONFIG_MIPS_MT_SMP should depend upon CPU_MIPSR2
MIPS: CPS: drop .set mips64r2 directives
arch/mips/Kconfig | 2 +-
arch/mips/kernel/cps-vec.S | 18 +++++++++---------
2 files changed, 10 insertions(+), 10 deletions(-)
--
2.5.0
Commit b677bc03d757 ("MIPS: cps-vec: Use macros for various arithmetics
and memory operations") replaced various load & store instructions
through cps-vec.S with the PTR_L & PTR_S macros. However it was somewhat
overzealous in doing so for CM GCR accesses, since the bit width of the
CM doesn't necessarily match that of the CPU. The registers accessed
(GCR_CL_COHERENCE & GCR_CL_ID) should be safe to simply always access
using 32b instructions, so do so in order to avoid issues when using a
32b CM with a 64b CPU.
Signed-off-by: Paul Burton <[email protected]>
Cc: Markos Chandras <[email protected]>
Cc: <[email protected]> # 3.16+
---
arch/mips/kernel/cps-vec.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 1b6ca63..9f71c06 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -152,7 +152,7 @@ dcache_done:
/* Enter the coherent domain */
li t0, 0xff
- PTR_S t0, GCR_CL_COHERENCE_OFS(v1)
+ sw t0, GCR_CL_COHERENCE_OFS(v1)
ehb
/* Jump to kseg0 */
@@ -302,7 +302,7 @@ LEAF(mips_cps_boot_vpes)
PTR_L t0, 0(t0)
/* Calculate a pointer to this cores struct core_boot_config */
- PTR_L t0, GCR_CL_ID_OFS(t0)
+ lw t0, GCR_CL_ID_OFS(t0)
li t1, COREBOOTCFG_SIZE
mul t0, t0, t1
PTR_LA t1, mips_cps_core_bootcfg
--
2.5.0
The has_mt macro ended with a branch, leaving its callers with a delay
slot that would be executed if Config3.MT is not set. However it would
not be executed if Config3 (or earlier Config registers) don't exist
which makes it somewhat inconsistent at best. Fill the delay slot in the
macro & fix the mips_cps_boot_vpes caller appropriately.
Signed-off-by: Paul Burton <[email protected]>
Cc: Markos Chandras <[email protected]>
Cc: <[email protected]> # 3.16+
---
arch/mips/kernel/cps-vec.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 9f71c06..fa159aa 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -39,6 +39,7 @@
mfc0 \dest, CP0_CONFIG, 3
andi \dest, \dest, MIPS_CONF3_MT
beqz \dest, \nomt
+ nop
.endm
.section .text.cps-vec
@@ -226,7 +227,6 @@ LEAF(mips_cps_core_init)
#ifdef CONFIG_MIPS_MT
/* Check that the core implements the MT ASE */
has_mt t0, 3f
- nop
.set push
.set mips64r2
@@ -310,8 +310,8 @@ LEAF(mips_cps_boot_vpes)
PTR_ADDU t0, t0, t1
/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
+ li t9, 0
has_mt ta2, 1f
- li t9, 0
/* Find the number of VPEs present in the core */
mfc0 t1, CP0_MVPCONF0
--
2.5.0
The MT-specific code in mips_cps_boot_vpes can safely be omitted from
kernels which don't support MT, with the default VPE==0 case being used
as it would be after the has_mt (Config3.MT) check failed at runtime.
Discarding the code entirely will save us a few bytes & allow cleaner
handling of MT ASE instructions by later patches.
Signed-off-by: Paul Burton <[email protected]>
Cc: Markos Chandras <[email protected]>
Cc: <[email protected]> # 3.16+
---
arch/mips/kernel/cps-vec.S | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index fa159aa..57642f5 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -311,6 +311,7 @@ LEAF(mips_cps_boot_vpes)
/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
li t9, 0
+#ifdef CONFIG_MIPS_MT
has_mt ta2, 1f
/* Find the number of VPEs present in the core */
@@ -330,6 +331,7 @@ LEAF(mips_cps_boot_vpes)
/* Retrieve the VPE ID from EBase.CPUNum */
mfc0 t9, $15, 1
and t9, t9, t1
+#endif
1: /* Calculate a pointer to this VPEs struct vpe_boot_config */
li t1, VPEBOOTCFG_SIZE
--
2.5.0
The CONFIG_MIPS_MT symbol can be selected by CONFIG_MIPS_VPE_LOADER in
addition to CONFIG_MIPS_MT_SMP. We only want MT code in the CPS SMP boot
vector if we're using MT for SMP. Thus switch the config symbol we ifdef
against to CONFIG_MIPS_MT_SMP.
Signed-off-by: Paul Burton <[email protected]>
Cc: Markos Chandras <[email protected]>
Cc: <[email protected]> # 3.16+
---
arch/mips/kernel/cps-vec.S | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 57642f5..209ded1 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -224,7 +224,7 @@ LEAF(excep_ejtag)
END(excep_ejtag)
LEAF(mips_cps_core_init)
-#ifdef CONFIG_MIPS_MT
+#ifdef CONFIG_MIPS_MT_SMP
/* Check that the core implements the MT ASE */
has_mt t0, 3f
@@ -311,7 +311,7 @@ LEAF(mips_cps_boot_vpes)
/* Calculate this VPEs ID. If the core doesn't support MT use 0 */
li t9, 0
-#ifdef CONFIG_MIPS_MT
+#ifdef CONFIG_MIPS_MT_SMP
has_mt ta2, 1f
/* Find the number of VPEs present in the core */
@@ -339,7 +339,7 @@ LEAF(mips_cps_boot_vpes)
PTR_L ta3, COREBOOTCFG_VPECONFIG(t0)
PTR_ADDU v0, v0, ta3
-#ifdef CONFIG_MIPS_MT
+#ifdef CONFIG_MIPS_MT_SMP
/* If the core doesn't support MT then return */
bnez ta2, 1f
@@ -453,7 +453,7 @@ LEAF(mips_cps_boot_vpes)
2: .set pop
-#endif /* CONFIG_MIPS_MT */
+#endif /* CONFIG_MIPS_MT_SMP */
/* Return */
jr ra
--
2.5.0
The MT ASE cannot be used with CPUs that implement older releases of the
MIPS architecture than release 2, and is replaced in release 6. Encode
these constraints in Kconfig to ensure that MT code is only built as
part of kernels targeting an appropriate revision of the architecture.
Signed-off-by: Paul Burton <[email protected]>
Cc: Markos Chandras <[email protected]>
Cc: <[email protected]> # 3.16+
---
arch/mips/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index cee5f93..ef248cf 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2114,7 +2114,7 @@ config CPU_R4K_CACHE_TLB
config MIPS_MT_SMP
bool "MIPS MT SMP support (1 TC on each available VPE)"
- depends on SYS_SUPPORTS_MULTITHREADING
+ depends on SYS_SUPPORTS_MULTITHREADING && CPU_MIPSR2
select CPU_MIPSR2_IRQ_VI
select CPU_MIPSR2_IRQ_EI
select SYNC_R4K
--
2.5.0
Commit 977e043d5ea1 ("MIPS: kernel: cps-vec: Replace mips32r2 ISA level
with mips64r2") leads to .set mips64r2 directives being present in 32
bit (ie. CONFIG_32BIT=y) kernels. This is incorrect & leads to MIPS64
instructions being emitted by the assembler when expanding
pseudo-instructions. For example the "move" instruction can legitimately
be expanded to a "daddu". This causes problems when the kernel is run on
a MIPS32 CPU, as CONFIG_32BIT kernels of course often are...
Fix this by dropping the .set <ISA> directives entirely now that Kconfig
should be ensuring that kernels including this code are built with a
suitable -march= compiler flag.
Signed-off-by: Paul Burton <[email protected]>
Cc: Markos Chandras <[email protected]>
Cc: <[email protected]> # 3.16+
---
arch/mips/kernel/cps-vec.S | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 209ded1..763d8b7 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -229,7 +229,6 @@ LEAF(mips_cps_core_init)
has_mt t0, 3f
.set push
- .set mips64r2
.set mt
/* Only allow 1 TC per VPE to execute... */
@@ -348,7 +347,6 @@ LEAF(mips_cps_boot_vpes)
nop
.set push
- .set mips64r2
.set mt
1: /* Enter VPE configuration state */
--
2.5.0
Hi Paul / Rafl,
> -----Original Message-----
> From: [email protected] [mailto:linux-mips-bounce@linux-
> mips.org] On Behalf Of Paul Burton
> Sent: 05 August 2015 11:43 PM
> To: [email protected]
> Cc: Paul Burton; [email protected]; James Hogan; Markos Chandras;
> Ralf Baechle
> Subject: [PATCH 0/6] MIPS CPS SMP fixes, debug & cleanups
>
> This series fixes a few issues with the MIPS Coherent Processing System SMP
> implementation, provides some extra capabilities with regards to debug and does
> a little spring cleaning. A couple of the issues fixed were introduced in v4.1-rc1
> and (spuriously) marked for stable backports as far as v3.16, so the fixes in this
> series are marked likewise.
>
> Applies atop v4.2-rc5.
>
> Paul Burton (6):
> MIPS: CPS: use 32b accesses to GCRs
> MIPS: CPS: stop dangling delay slot from has_mt
> MIPS: CPS: don't include MT code in non-MT kernels
> MIPS: CPS: #ifdef on CONFIG_MIPS_MT_SMP rather than CONFIG_MIPS_MT
> MIPS: CONFIG_MIPS_MT_SMP should depend upon CPU_MIPSR2
> MIPS: CPS: drop .set mips64r2 directives
>
> arch/mips/Kconfig | 2 +-
> arch/mips/kernel/cps-vec.S | 18 +++++++++---------
> 2 files changed, 10 insertions(+), 10 deletions(-)
I just boot tested on Pistachio Platform (MIPS interAptiv (multi) (32)).
Without this patch series boot is broken for pistachio platform for 4.2-rc5.
--
Thanks,
Govindraj.R
> -----Original Message-----
> From: [email protected] [mailto:linux-mips-bounce@linux-
> mips.org] On Behalf Of Govindraj Raja
> Sent: 06 August 2015 12:05 PM
> To: Paul Burton; [email protected]; Ralf Baechle ([email protected])
> Cc: [email protected]; James Hogan; Markos Chandras; Ralf Baechle
> Subject: RE: [PATCH 0/6] MIPS CPS SMP fixes, debug & cleanups
>
> Hi Paul / Rafl,
>
> > -----Original Message-----
> > From: [email protected]
> > [mailto:linux-mips-bounce@linux- mips.org] On Behalf Of Paul Burton
> > Sent: 05 August 2015 11:43 PM
> > To: [email protected]
> > Cc: Paul Burton; [email protected]; James Hogan; Markos
> > Chandras; Ralf Baechle
> > Subject: [PATCH 0/6] MIPS CPS SMP fixes, debug & cleanups
> >
> > This series fixes a few issues with the MIPS Coherent Processing
> > System SMP implementation, provides some extra capabilities with
> > regards to debug and does a little spring cleaning. A couple of the
> > issues fixed were introduced in v4.1-rc1 and (spuriously) marked for
> > stable backports as far as v3.16, so the fixes in this series are marked likewise.
> >
> > Applies atop v4.2-rc5.
> >
> > Paul Burton (6):
> > MIPS: CPS: use 32b accesses to GCRs
> > MIPS: CPS: stop dangling delay slot from has_mt
> > MIPS: CPS: don't include MT code in non-MT kernels
> > MIPS: CPS: #ifdef on CONFIG_MIPS_MT_SMP rather than CONFIG_MIPS_MT
> > MIPS: CONFIG_MIPS_MT_SMP should depend upon CPU_MIPSR2
> > MIPS: CPS: drop .set mips64r2 directives
> >
> > arch/mips/Kconfig | 2 +-
> > arch/mips/kernel/cps-vec.S | 18 +++++++++---------
> > 2 files changed, 10 insertions(+), 10 deletions(-)
Tested-by: Govindraj Raja <[email protected]>
[For Pistachio Platform]
--
Thanks,
Govindraj.R
On Sat, Sep 12, 2015 at 08:11:31AM -0700, Paul Burton wrote:
> Date: Sat, 12 Sep 2015 08:11:31 -0700
> From: Paul Burton <[email protected]>
> To: Ralf Baechle <[email protected]>
> CC: [email protected], Markos Chandras
> <[email protected]>, [email protected],
> [email protected]
> Subject: Re: [PATCH 5/6] MIPS: CONFIG_MIPS_MT_SMP should depend upon
> CPU_MIPSR2
> Content-Type: text/plain; charset="utf-8"
>
> On Sat, Sep 12, 2015 at 12:16:39PM +0200, Ralf Baechle wrote:
> > > config MIPS_MT_SMP
> > > bool "MIPS MT SMP support (1 TC on each available VPE)"
> > > - depends on SYS_SUPPORTS_MULTITHREADING
> > > + depends on SYS_SUPPORTS_MULTITHREADING && CPU_MIPSR2
> >
> > Right now this line is
> >
> > depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6
> >
> > which I believe is correct. The MT SMP support aka VSMP had been
> > carefully crafted to work on older ASEs that is all use of MIPS MT
> > instructions or features was carefully protected by cpu_has_mipsmt
> > or similar.
>
> I disagree. The "background" section in the introduction to the MT ASE
> spec (MD00376, revision 1.12) reads:
>
> > Multi-threading, or the concurrent presence of multiple active threads
> > or contexts of execution on the same CPU, is an increasingly
> > widely-used technique for tolerating memory and execution latency and
> > for getting higher utilization out of processor functional units. The
> > MIPS? Multi-threading (MT) Module is an extension to Release 2 (and
> > newer) of the MIPS32? Architecture which provides a framework for
> > multi-threading the MIPS processor architecture.
>
> MT is quite clearly an extension to r2. The MT bit in Config3 has this
> note in the MIPS32 PRA (MD00088, revision 6.01):
>
> > For Release 6 and MIPS after, this bit must be 0.
>
> Thus MT is an option from r2 <= ISA < r6. The current !CPU_MIPSR6
> constraint in Kconfig only enforces half of that. Depending upon
> CPU_MIPSR2 would enforce the whole.
Correct. Still, VSMP's use of MT instruction is very limited to a few
particular places in the kernel which makes a simple exervise to support
a kernel that is capable of supporting VSMP yet will support MIPS IV,
MIPS 32R1 CPUs or MIPS 32R2+ without MT.
Ralf