MT2712 is a SoC based on 64bit ARMv8 architecture.
MT2712 share many HW IP with MT8173. This patchset was tested on MT2712 evaluation board, and boot to shell ok.
This series contains document bindings, device tree including interrupt and uart.
Changes compared to v3:
- use two uart clocks refer to the bindings
Changes compared to v2:
- remove alias from serial1 to serial5
- remove initrd-start and initrd-end
- change GIC_CPU_MASK_SIMPLE(6) to GIC_CPU_MASK_RAW(0x13)
- change gic-400 reg range
Changes compared to v1:
- change subject prefix for bindings
- change device tree license to SPDX tag.
- change bootargs parameter to DT usage.
- change intpol-controller to interrupt-controller
YT Shen (2):
dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform
arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and
Makefile
Documentation/devicetree/bindings/arm/mediatek.txt | 4 +
.../interrupt-controller/mediatek,sysirq.txt | 1 +
.../devicetree/bindings/serial/mtk-uart.txt | 1 +
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 32 ++++
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 172 +++++++++++++++++++++
6 files changed, 211 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
--
1.9.1
This adds dt-binding documentation for Mediatek MT2712.
Only include very basic items: cpu, gic and uart.
Signed-off-by: YT Shen <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/arm/mediatek.txt | 4 ++++
.../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt | 1 +
Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
3 files changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
index c860b24..3161651 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -7,6 +7,7 @@ Required root node property:
compatible: Must contain one of
"mediatek,mt2701"
+ "mediatek,mt2712"
"mediatek,mt6580"
"mediatek,mt6589"
"mediatek,mt6592"
@@ -23,6 +24,9 @@ Supported boards:
- Evaluation board for MT2701:
Required root node properties:
- compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
+- Evaluation board for MT2712:
+ Required root node properties:
+ - compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
- Evaluation board for MT6580:
Required root node properties:
- compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index a89c03b..653adb5 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -16,6 +16,7 @@ Required properties:
"mediatek,mt6580-sysirq"
"mediatek,mt6577-sysirq"
"mediatek,mt2701-sysirq"
+ "mediatek,mt2712-sysirq"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
- interrupt-parent: phandle of irq parent for sysirq. The parent must
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index 0015c72..5f88e0d 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -3,6 +3,7 @@
Required properties:
- compatible should contain:
* "mediatek,mt2701-uart" for MT2701 compatible UARTS
+ * "mediatek,mt2712-uart" for MT2712 compatible UARTS
* "mediatek,mt6580-uart" for MT6580 compatible UARTS
* "mediatek,mt6582-uart" for MT6582 compatible UARTS
* "mediatek,mt6589-uart" for MT6589 compatible UARTS
--
1.9.1
This adds basic chip support for Mediatek 2712
Signed-off-by: YT Shen <[email protected]>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 32 ++++++
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 172 ++++++++++++++++++++++++++++
3 files changed, 205 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 9fbfd32..fcc0604 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
new file mode 100644
index 0000000..8c804df
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen <[email protected]>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt2712e.dtsi"
+
+/ {
+ model = "MediaTek MT2712 evaluation board";
+ compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x80000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
new file mode 100644
index 0000000..461ee0f
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: YT Shen <[email protected]>
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "mediatek,mt2712";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu2>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x001>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x200>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ uart_clk: dummy26m {
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+ #clock-cells = <0>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ uart5: serial@1000f000 {
+ compatible = "mediatek,mt2712-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x1000f000 0 0x400>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ sysirq: interrupt-controller@10220a80 {
+ compatible = "mediatek,mt2712-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10220a80 0 0x40>;
+ };
+
+ gic: interrupt-controller@10510000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x10510000 0 0x10000>,
+ <0 0x10520000 0 0x20000>,
+ <0 0x10540000 0 0x20000>,
+ <0 0x10560000 0 0x20000>;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt2712-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x400>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt2712-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x400>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: serial@11004000 {
+ compatible = "mediatek,mt2712-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x400>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart3: serial@11005000 {
+ compatible = "mediatek,mt2712-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11005000 0 0x400>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart4: serial@11019000 {
+ compatible = "mediatek,mt2712-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11019000 0 0x400>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+ };
+};
+
--
1.9.1
Hi Matthias,
Just a gentle ping.
Should I rebase to 4.13-rc1 and send v5?
Thanks
yt.shen
On Thu, 2017-06-22 at 17:32 +0800, YT Shen wrote:
> MT2712 is a SoC based on 64bit ARMv8 architecture.
> MT2712 share many HW IP with MT8173. This patchset was tested on MT2712 evaluation board, and boot to shell ok.
>
> This series contains document bindings, device tree including interrupt and uart.
>
> Changes compared to v3:
> - use two uart clocks refer to the bindings
>
> Changes compared to v2:
> - remove alias from serial1 to serial5
> - remove initrd-start and initrd-end
> - change GIC_CPU_MASK_SIMPLE(6) to GIC_CPU_MASK_RAW(0x13)
> - change gic-400 reg range
>
> Changes compared to v1:
> - change subject prefix for bindings
> - change device tree license to SPDX tag.
> - change bootargs parameter to DT usage.
> - change intpol-controller to interrupt-controller
>
> YT Shen (2):
> dt-bindings: arm: Add bindings for Mediatek MT2712 SoC Platform
> arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and
> Makefile
>
> Documentation/devicetree/bindings/arm/mediatek.txt | 4 +
> .../interrupt-controller/mediatek,sysirq.txt | 1 +
> .../devicetree/bindings/serial/mtk-uart.txt | 1 +
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 32 ++++
> arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 172 +++++++++++++++++++++
> 6 files changed, 211 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
>
On 06/22/2017 11:32 AM, YT Shen wrote:
> This adds basic chip support for Mediatek 2712
>
> Signed-off-by: YT Shen <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 32 ++++++
> arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 172 ++++++++++++++++++++++++++++
> 3 files changed, 205 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index 9fbfd32..fcc0604 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -1,3 +1,4 @@
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> new file mode 100644
> index 0000000..8c804df
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> @@ -0,0 +1,32 @@
> +/*
> + * Copyright (c) 2017 MediaTek Inc.
> + * Author: YT Shen <[email protected]>
> + *
> + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> + */
> +
> +/dts-v1/;
> +#include "mt2712e.dtsi"
> +
> +/ {
> + model = "MediaTek MT2712 evaluation board";
> + compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0 0x40000000 0 0x80000000>;
> + };
> +
> + chosen {
> + stdout-path = "serial0:921600n8";
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> new file mode 100644
> index 0000000..461ee0f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> @@ -0,0 +1,172 @@
> +/*
> + * Copyright (c) 2017 MediaTek Inc.
> + * Author: YT Shen <[email protected]>
> + *
> + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + compatible = "mediatek,mt2712";
> + interrupt-parent = <&sysirq>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&cpu2>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a35";
> + reg = <0x000>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a35";
> + reg = <0x001>;
> + enable-method = "psci";
> + };
> +
> + cpu2: cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0x200>;
> + enable-method = "psci";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + uart_clk: dummy26m {
> + compatible = "fixed-clock";
> + clock-frequency = <26000000>;
> + #clock-cells = <0>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_PPI 13
> + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14
> + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11
> + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10
> + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + uart5: serial@1000f000 {
> + compatible = "mediatek,mt2712-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x1000f000 0 0x400>;
> + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&uart_clk>, <&uart_clk>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
So baud and bus clock are both 26 MHz?
Regards,
Matthias
On Tue, 2017-07-18 at 18:29 +0200, Matthias Brugger wrote:
>
> On 06/22/2017 11:32 AM, YT Shen wrote:
> > This adds basic chip support for Mediatek 2712
> >
> > Signed-off-by: YT Shen <[email protected]>
> > ---
> > arch/arm64/boot/dts/mediatek/Makefile | 1 +
> > arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 32 ++++++
> > arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 172 ++++++++++++++++++++++++++++
> > 3 files changed, 205 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> > index 9fbfd32..fcc0604 100644
> > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > @@ -1,3 +1,4 @@
> > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
> > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > new file mode 100644
> > index 0000000..8c804df
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
> > @@ -0,0 +1,32 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen <[email protected]>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +/dts-v1/;
> > +#include "mt2712e.dtsi"
> > +
> > +/ {
> > + model = "MediaTek MT2712 evaluation board";
> > + compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
> > +
> > + aliases {
> > + serial0 = &uart0;
> > + };
> > +
> > + memory@40000000 {
> > + device_type = "memory";
> > + reg = <0 0x40000000 0 0x80000000>;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:921600n8";
> > + };
> > +};
> > +
> > +&uart0 {
> > + status = "okay";
> > +};
> > +
> > diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > new file mode 100644
> > index 0000000..461ee0f
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> > @@ -0,0 +1,172 @@
> > +/*
> > + * Copyright (c) 2017 MediaTek Inc.
> > + * Author: YT Shen <[email protected]>
> > + *
> > + * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > + compatible = "mediatek,mt2712";
> > + interrupt-parent = <&sysirq>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu-map {
> > + cluster0 {
> > + core0 {
> > + cpu = <&cpu0>;
> > + };
> > + core1 {
> > + cpu = <&cpu1>;
> > + };
> > + };
> > +
> > + cluster1 {
> > + core0 {
> > + cpu = <&cpu2>;
> > + };
> > + };
> > + };
> > +
> > + cpu0: cpu@0 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a35";
> > + reg = <0x000>;
> > + };
> > +
> > + cpu1: cpu@1 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a35";
> > + reg = <0x001>;
> > + enable-method = "psci";
> > + };
> > +
> > + cpu2: cpu@200 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + reg = <0x200>;
> > + enable-method = "psci";
> > + };
> > + };
> > +
> > + psci {
> > + compatible = "arm,psci-0.2";
> > + method = "smc";
> > + };
> > +
> > + uart_clk: dummy26m {
> > + compatible = "fixed-clock";
> > + clock-frequency = <26000000>;
> > + #clock-cells = <0>;
> > + };
> > +
> > + timer {
> > + compatible = "arm,armv8-timer";
> > + interrupt-parent = <&gic>;
> > + interrupts = <GIC_PPI 13
> > + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
> > + <GIC_PPI 14
> > + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
> > + <GIC_PPI 11
> > + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
> > + <GIC_PPI 10
> > + (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
> > + };
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + compatible = "simple-bus";
> > + ranges;
> > +
> > + uart5: serial@1000f000 {
> > + compatible = "mediatek,mt2712-uart",
> > + "mediatek,mt6577-uart";
> > + reg = <0 0x1000f000 0 0x400>;
> > + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&uart_clk>, <&uart_clk>;
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
>
> So baud and bus clock are both 26 MHz?
We didn't have CCF clock support in this series.
After we have clock source support, we could use the correct clocks to
the UARTs and drop the 26MHz fixed rate UART clock.
The bus clock is 26MHz. The baud clock could be from another clock
source, using the same 26MHz fixed clock works also.
[1] https://patchwork.kernel.org/patch/9670877/
[2] https://patchwork.kernel.org/patch/6436021/
> Regards,
> Matthias
On 07/19/2017 08:48 AM, YT Shen wrote:
> On Tue, 2017-07-18 at 18:29 +0200, Matthias Brugger wrote:
>>
>> On 06/22/2017 11:32 AM, YT Shen wrote:
>>> This adds basic chip support for Mediatek 2712
[...]
>>> +
>>> + uart_clk: dummy26m {
>>> + compatible = "fixed-clock";
>>> + clock-frequency = <26000000>;
>>> + #clock-cells = <0>;
>>> + };
>>> +
[...]
>>> +
>>> + soc {
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + compatible = "simple-bus";
>>> + ranges;
>>> +
>>> + uart5: serial@1000f000 {
>>> + compatible = "mediatek,mt2712-uart",
>>> + "mediatek,mt6577-uart";
>>> + reg = <0 0x1000f000 0 0x400>;
>>> + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
>>> + clocks = <&uart_clk>, <&uart_clk>;
>>> + clock-names = "baud", "bus";
>>> + status = "disabled";
>>> + };
>>
>> So baud and bus clock are both 26 MHz?
> We didn't have CCF clock support in this series.
> After we have clock source support, we could use the correct clocks to
> the UARTs and drop the 26MHz fixed rate UART clock.
>
> The bus clock is 26MHz. The baud clock could be from another clock
> source, using the same 26MHz fixed clock works also.
>
>
> [1] https://patchwork.kernel.org/patch/9670877/
> [2] https://patchwork.kernel.org/patch/6436021/
>
Yes, just using one 26 MHz clock works, but it uses an deprecated
binding, so we should not do this, as through copying from the source of
other SoCs we will keep it alive forever. Anyway that's not your case,
as you defined the two clocks.
The device tree should reflect the HW, that's why I asked for the clock
frequency of both clocks. I searched the git history and it was never
done right before. So you could be the first :)
Thanks,
Matthias
On Wed, 2017-07-19 at 11:26 +0200, Matthias Brugger wrote:
>
> On 07/19/2017 08:48 AM, YT Shen wrote:
> > On Tue, 2017-07-18 at 18:29 +0200, Matthias Brugger wrote:
> >>
> >> On 06/22/2017 11:32 AM, YT Shen wrote:
> >>> This adds basic chip support for Mediatek 2712
>
> [...]
>
> >>> +
> >>> + uart_clk: dummy26m {
> >>> + compatible = "fixed-clock";
> >>> + clock-frequency = <26000000>;
> >>> + #clock-cells = <0>;
> >>> + };
> >>> +
>
> [...]
>
> >>> +
> >>> + soc {
> >>> + #address-cells = <2>;
> >>> + #size-cells = <2>;
> >>> + compatible = "simple-bus";
> >>> + ranges;
> >>> +
> >>> + uart5: serial@1000f000 {
> >>> + compatible = "mediatek,mt2712-uart",
> >>> + "mediatek,mt6577-uart";
> >>> + reg = <0 0x1000f000 0 0x400>;
> >>> + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
> >>> + clocks = <&uart_clk>, <&uart_clk>;
> >>> + clock-names = "baud", "bus";
> >>> + status = "disabled";
> >>> + };
> >>
> >> So baud and bus clock are both 26 MHz?
> > We didn't have CCF clock support in this series.
> > After we have clock source support, we could use the correct clocks to
> > the UARTs and drop the 26MHz fixed rate UART clock.
> >
> > The bus clock is 26MHz. The baud clock could be from another clock
> > source, using the same 26MHz fixed clock works also.
> >
> >
> > [1] https://patchwork.kernel.org/patch/9670877/
> > [2] https://patchwork.kernel.org/patch/6436021/
> >
>
> Yes, just using one 26 MHz clock works, but it uses an deprecated
> binding, so we should not do this, as through copying from the source of
> other SoCs we will keep it alive forever. Anyway that's not your case,
> as you defined the two clocks.
>
> The device tree should reflect the HW, that's why I asked for the clock
> frequency of both clocks. I searched the git history and it was never
> done right before. So you could be the first :)
>
> Thanks,
> Matthias
Ok, I want to make it clear. The following example
baud_clk: dummy26m {
compatible = "fixed-clock";
clock-frequency = <26000000>;
#clock-cells = <0>;
};
sys_clk: dummyclk {
compatible = "fixed-clock";
clock-frequency = <26000000>;
#clock-cells = <0>;
};
uart0: serial@11002000 {
[...]
clocks = <&baud_clk>, <&sys_clk>;
[...]
}
Do you think it is clear to reflect the HW that the baud clock and sys
clock can be different source or we need to choose another frequency?
Thanks.
yt.shen
On 07/21/2017 08:32 AM, YT Shen wrote:
> On Wed, 2017-07-19 at 11:26 +0200, Matthias Brugger wrote:
>>
>> On 07/19/2017 08:48 AM, YT Shen wrote:
>>> On Tue, 2017-07-18 at 18:29 +0200, Matthias Brugger wrote:
>>>>
>>>> On 06/22/2017 11:32 AM, YT Shen wrote:
>>>>> This adds basic chip support for Mediatek 2712
>>
>> [...]
>>
>>>>> +
>>>>> + uart_clk: dummy26m {
>>>>> + compatible = "fixed-clock";
>>>>> + clock-frequency = <26000000>;
>>>>> + #clock-cells = <0>;
>>>>> + };
>>>>> +
>>
>> [...]
>>
>>>>> +
>>>>> + soc {
>>>>> + #address-cells = <2>;
>>>>> + #size-cells = <2>;
>>>>> + compatible = "simple-bus";
>>>>> + ranges;
>>>>> +
>>>>> + uart5: serial@1000f000 {
>>>>> + compatible = "mediatek,mt2712-uart",
>>>>> + "mediatek,mt6577-uart";
>>>>> + reg = <0 0x1000f000 0 0x400>;
>>>>> + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
>>>>> + clocks = <&uart_clk>, <&uart_clk>;
>>>>> + clock-names = "baud", "bus";
>>>>> + status = "disabled";
>>>>> + };
>>>>
>>>> So baud and bus clock are both 26 MHz?
>>> We didn't have CCF clock support in this series.
>>> After we have clock source support, we could use the correct clocks to
>>> the UARTs and drop the 26MHz fixed rate UART clock.
>>>
>>> The bus clock is 26MHz. The baud clock could be from another clock
>>> source, using the same 26MHz fixed clock works also.
>>>
>>>
>>> [1] https://patchwork.kernel.org/patch/9670877/
>>> [2] https://patchwork.kernel.org/patch/6436021/
>>>
>>
>> Yes, just using one 26 MHz clock works, but it uses an deprecated
>> binding, so we should not do this, as through copying from the source of
>> other SoCs we will keep it alive forever. Anyway that's not your case,
>> as you defined the two clocks.
>>
>> The device tree should reflect the HW, that's why I asked for the clock
>> frequency of both clocks. I searched the git history and it was never
>> done right before. So you could be the first :)
>>
>> Thanks,
>> Matthias
> Ok, I want to make it clear. The following example
>
> baud_clk: dummy26m {
> compatible = "fixed-clock";
> clock-frequency = <26000000>;
> #clock-cells = <0>;
> };
>
> sys_clk: dummyclk {
> compatible = "fixed-clock";
> clock-frequency = <26000000>;
> #clock-cells = <0>;
> };
>
> uart0: serial@11002000 {
> [...]
> clocks = <&baud_clk>, <&sys_clk>;
> [...]
> }
>
> Do you think it is clear to reflect the HW that the baud clock and sys
> clock can be different source or we need to choose another frequency?
> Thanks.
>
Best would be to choose the frequency you expect from both clocks. E.g.
the frequency set by the bootloader. If the clock is the same, then we
can leave the patch as-is.
Thanks,
Matthias