2017-09-08 19:50:31

by Krishna Reddy

[permalink] [raw]
Subject: [PATCH] mmc: tegra: Mark 64 bit dma broken on Tegra186

SDHCI controllers on Tegra186 support 40 bit addressing.
IOVA addresses are 48-bit wide on Tegra186.
SDHCI host common code sets dma mask as either 32-bit or 64-bit.
To avoid access issues when SMMU is enabled, disable 64-bit dma.

Signed-off-by: Krishna Reddy <[email protected]>
---
drivers/mmc/host/sdhci-tegra.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 0cd6fa80db66..b877c13184c2 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -422,7 +422,15 @@ static const struct sdhci_pltfm_data sdhci_tegra186_pdata = {
SDHCI_QUIRK_NO_HISPD_BIT |
SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
- .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
+ /* SDHCI controllers on Tegra186 support 40-bit addressing.
+ * IOVA addresses are 48-bit wide on Tegra186.
+ * With 64-bit dma mask used for SDHCI, accesses can
+ * be broken. Disable 64-bit dma, which would fall back
+ * to 32-bit dma mask. Ideally 40-bit dma mask would work,
+ * But it is not supported as of now.
+ */
+ SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
.ops = &tegra114_sdhci_ops,
};

--
2.1.4


2017-09-08 22:00:14

by Thierry Reding

[permalink] [raw]
Subject: Re: [PATCH] mmc: tegra: Mark 64 bit dma broken on Tegra186

On Fri, Sep 08, 2017 at 12:48:33PM -0700, Krishna Reddy wrote:
> SDHCI controllers on Tegra186 support 40 bit addressing.
> IOVA addresses are 48-bit wide on Tegra186.
> SDHCI host common code sets dma mask as either 32-bit or 64-bit.
> To avoid access issues when SMMU is enabled, disable 64-bit dma.
>
> Signed-off-by: Krishna Reddy <[email protected]>
> ---
> drivers/mmc/host/sdhci-tegra.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)

This matches a local commit:

Tested-by: Thierry Reding <[email protected]>
Acked-by: Thierry Reding <[email protected]>

Attachments:
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2017-09-11 05:54:14

by Adrian Hunter

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Subject: Re: [PATCH] mmc: tegra: Mark 64 bit dma broken on Tegra186

On 08/09/17 22:48, Krishna Reddy wrote:
> SDHCI controllers on Tegra186 support 40 bit addressing.
> IOVA addresses are 48-bit wide on Tegra186.
> SDHCI host common code sets dma mask as either 32-bit or 64-bit.
> To avoid access issues when SMMU is enabled, disable 64-bit dma.
>
> Signed-off-by: Krishna Reddy <[email protected]>

Acked-by: Adrian Hunter <[email protected]>

> ---
> drivers/mmc/host/sdhci-tegra.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
> index 0cd6fa80db66..b877c13184c2 100644
> --- a/drivers/mmc/host/sdhci-tegra.c
> +++ b/drivers/mmc/host/sdhci-tegra.c
> @@ -422,7 +422,15 @@ static const struct sdhci_pltfm_data sdhci_tegra186_pdata = {
> SDHCI_QUIRK_NO_HISPD_BIT |
> SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
> SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
> - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
> + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
> + /* SDHCI controllers on Tegra186 support 40-bit addressing.
> + * IOVA addresses are 48-bit wide on Tegra186.
> + * With 64-bit dma mask used for SDHCI, accesses can
> + * be broken. Disable 64-bit dma, which would fall back
> + * to 32-bit dma mask. Ideally 40-bit dma mask would work,
> + * But it is not supported as of now.
> + */
> + SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
> .ops = &tegra114_sdhci_ops,
> };
>
>

2017-09-22 09:45:22

by Ulf Hansson

[permalink] [raw]
Subject: Re: [PATCH] mmc: tegra: Mark 64 bit dma broken on Tegra186

On 8 September 2017 at 21:48, Krishna Reddy <[email protected]> wrote:
> SDHCI controllers on Tegra186 support 40 bit addressing.
> IOVA addresses are 48-bit wide on Tegra186.
> SDHCI host common code sets dma mask as either 32-bit or 64-bit.
> To avoid access issues when SMMU is enabled, disable 64-bit dma.
>
> Signed-off-by: Krishna Reddy <[email protected]>

Thanks, applied for next!

Kind regards
Uffe

> ---
> drivers/mmc/host/sdhci-tegra.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
> index 0cd6fa80db66..b877c13184c2 100644
> --- a/drivers/mmc/host/sdhci-tegra.c
> +++ b/drivers/mmc/host/sdhci-tegra.c
> @@ -422,7 +422,15 @@ static const struct sdhci_pltfm_data sdhci_tegra186_pdata = {
> SDHCI_QUIRK_NO_HISPD_BIT |
> SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
> SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
> - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
> + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
> + /* SDHCI controllers on Tegra186 support 40-bit addressing.
> + * IOVA addresses are 48-bit wide on Tegra186.
> + * With 64-bit dma mask used for SDHCI, accesses can
> + * be broken. Disable 64-bit dma, which would fall back
> + * to 32-bit dma mask. Ideally 40-bit dma mask would work,
> + * But it is not supported as of now.
> + */
> + SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
> .ops = &tegra114_sdhci_ops,
> };
>
> --
> 2.1.4
>