2017-09-30 12:13:09

by David Wu

Subject: [PATCH 0/2] Fix two pinctrl issues

They are:
1. Fix the rk3399 gpio0 and gpio1 banks' drive strength offset.
2. Fix the correct routing config for the gmac-m1 pins between rmii and rgmii.

David Wu (2):
pinctrl: rockchip: Fix the rk3399 gpio0 and gpio1 banks' drv_offset at
pmu grf
pinctrl: rockchip: Fix the correct routing config for the gmac-m1 pins
of rmii and rgmii

drivers/pinctrl/pinctrl-rockchip.c | 23 +++++++++++++++--------
1 file changed, 15 insertions(+), 8 deletions(-)

--
1.9.1

2017-09-30 12:13:22

by David Wu

Subject: [PATCH 2/2] pinctrl: rockchip: Fix the correct routing config for the gmac-m1 pins of rmii and rgmii

If the gmac-m1 optimization(bit10) is selected, the gpio function
of gmac pins is not valid. We may use the rmii mode for gmac interface,
the pins such as rx_d2, rx_d3, which the rgmii mode used, but rmii not
used could be taken as gpio function. So gmac_rxd0m1 selects the bit2,
and gmac_rxd0m3 select bit10 is more correct.

Signed-off-by: David Wu <[email protected]>
---
drivers/pinctrl/pinctrl-rockchip.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index c7c9beb..9e0cabf 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -900,12 +900,19 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
.route_offset = 0x50,
.route_val = BIT(16) | BIT(16 + 1) | BIT(0),
}, {
- /* gmac-m1-optimized_rxd0 */
+ /* gmac-m1_rxd0 */
.bank_num = 1,
.pin = 11,
.func = 2,
.route_offset = 0x50,
- .route_val = BIT(16 + 2) | BIT(16 + 10) | BIT(2) | BIT(10),
+ .route_val = BIT(16 + 2) | BIT(2),
+ }, {
+ /* gmac-m1-optimized_rxd3 */
+ .bank_num = 1,
+ .pin = 14,
+ .func = 2,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 10) | BIT(10),
}, {
/* pdm_sdi0m0 */
.bank_num = 2,
--
1.9.1

2017-09-30 12:13:08

by David Wu

Subject: [PATCH 1/2] pinctrl: rockchip: Fix the rk3399 gpio0 and gpio1 banks' drv_offset at pmu grf

The offset of gpio0 and gpio1 bank drive strength is 0x8, not 0x4.
But the mux is 0x4, we couldn't use the IOMUX_WIDTH_4BIT flag, so
we give them actual offset.

Signed-off-by: David Wu <[email protected]>
---
drivers/pinctrl/pinctrl-rockchip.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index b5cb785..c7c9beb 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3456,8 +3456,8 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
DRV_TYPE_IO_1V8_ONLY,
DRV_TYPE_IO_DEFAULT,
DRV_TYPE_IO_DEFAULT,
- 0x0,
- 0x8,
+ 0x80,
+ 0x88,
-1,
-1,
PULL_TYPE_IO_1V8_ONLY,
@@ -3473,10 +3473,10 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
DRV_TYPE_IO_1V8_OR_3V0,
DRV_TYPE_IO_1V8_OR_3V0,
DRV_TYPE_IO_1V8_OR_3V0,
- 0x20,
- 0x28,
- 0x30,
- 0x38
+ 0xa0,
+ 0xa8,
+ 0xb0,
+ 0xb8
),
PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
DRV_TYPE_IO_1V8_OR_3V0,
--
1.9.1

2017-09-30 15:07:54

by Heiko Stuebner

Subject: Re: [PATCH 2/2] pinctrl: rockchip: Fix the correct routing config for the gmac-m1 pins of rmii and rgmii

Hi David,

Am Samstag, 30. September 2017, 20:13:21 CEST schrieb David Wu:
> If the gmac-m1 optimization(bit10) is selected, the gpio function
> of gmac pins is not valid. We may use the rmii mode for gmac interface,
> the pins such as rx_d2, rx_d3, which the rgmii mode used, but rmii not
> used could be taken as gpio function. So gmac_rxd0m1 selects the bit2,
> and gmac_rxd0m3 select bit10 is more correct.
>
> Signed-off-by: David Wu <[email protected]>

the patch subject should mention the the rk3328 whose routing gets fixed
(like adding a simple "on rk3328" to it), otherwise

Reviewed-by: Heiko Stuebner <[email protected]>