This patch series adds support for coresight on Hi6220; the first patch
is to fix coresight PLL so can avoid system hang after we enable
coresight, the second patch is to add DT binding according to coresight
topology.
The patch has been tested on Hikey; By using OpenCSD snapshot mode, it
can successfully decode ETF and ETB trace data.
Leo Yan (1):
clk: hi6220: mark clock cs_atb_syspll as critical
Li Pengcheng (1):
arm64: dts: hi6220: add coresight binding
.../arm64/boot/dts/hisilicon/hi6220-coresight.dtsi | 379 +++++++++++++++++++++
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 +
drivers/clk/hisilicon/clk-hi6220.c | 2 +-
3 files changed, 382 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi
--
2.7.4
Clock cs_atb_syspll is pll used for coresight trace bus; when clock
cs_atb_syspll is disabled and operates its child clock node cs_atb
results in system hang. So mark clock cs_atb_syspll as critical to
keep it enabled.
Cc: Guodong Xu <[email protected]>
Cc: Zhangfei Gao <[email protected]>
Cc: Haojian Zhuang <[email protected]>
Signed-off-by: Leo Yan <[email protected]>
---
drivers/clk/hisilicon/clk-hi6220.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c
index 4181b68..4742e8f 100644
--- a/drivers/clk/hisilicon/clk-hi6220.c
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -145,7 +145,7 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] __initdata = {
{ HI6220_BBPPLL_SEL, "bbppll_sel", "pll0_bbp_gate", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 9, 0, },
{ HI6220_MEDIA_PLL_SRC, "media_pll_src", "pll_media_gate", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 10, 0, },
{ HI6220_MMC2_SEL, "mmc2_sel", "mmc2_mux1", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 11, 0, },
- { HI6220_CS_ATB_SYSPLL, "cs_atb_syspll", "syspll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 12, 0, },
+ { HI6220_CS_ATB_SYSPLL, "cs_atb_syspll", "syspll", CLK_SET_RATE_PARENT|CLK_IS_CRITICAL, 0x270, 12, 0, },
};
static struct hisi_mux_clock hi6220_mux_clks_sys[] __initdata = {
--
2.7.4
From: Li Pengcheng <[email protected]>
For detailed coresight topology, Hi6220 has 8xCA53 CPUs and each CPU
has one Embedded Trace Macrocell (ETM); the CPU trace data is output
to the cluster funnel. Due system has another CPU and one MCU, all of
them transfer the trace data through trace bus (ATB) to SoC funnel;
the SoC funnel is connected to Embedded Trace FIFO (ETF) with 8KB
buffer; an non-configurable replicator is used to output trace data
for two sinks, one is Embedded Trace Route (ETR) so trace data can be
saved into DRAM, another is Trace Port Interface Unit (TPIU) for
capturing trace data by external debugger.
According to the Hi6220 coresight topology, this patch is to add
coresight dt binding.
Cc: Mathieu Poirier <[email protected]>
Cc: Mike Leach <[email protected]>
Cc: Guodong Xu <[email protected]>
Cc: Zhangfei Gao <[email protected]>
Cc: Haojian Zhuang <[email protected]>
Signed-off-by: Li Pengcheng <[email protected]>
Signed-off-by: Li Zhong <[email protected]>
Signed-off-by: Leo Yan <[email protected]>
---
.../arm64/boot/dts/hisilicon/hi6220-coresight.dtsi | 379 +++++++++++++++++++++
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 +
2 files changed, 381 insertions(+)
create mode 100644 arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi
new file mode 100644
index 0000000..31e4e95
--- /dev/null
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi
@@ -0,0 +1,379 @@
+/*
+ * dtsi file for Hisilicon Hi6220 coresight
+ *
+ * Copyright (C) 2017 Hisilicon Ltd.
+ *
+ * Author: Pengcheng Li <[email protected]>
+ * Leo Yan <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ *
+ */
+
+/ {
+ soc {
+ funnel@f6401000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0xf6401000 0 0x1000>;
+ clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ soc_funnel_out: endpoint {
+ remote-endpoint =
+ <&etf_in>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ soc_funnel_in: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&acpu_funnel_out>;
+ };
+ };
+ };
+ };
+
+ etf@f6402000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0xf6402000 0 0x1000>;
+ clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ etf_in: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&soc_funnel_out>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ etf_out: endpoint {
+ remote-endpoint =
+ <&replicator_in>;
+ };
+ };
+ };
+ };
+
+ replicator {
+ compatible = "arm,coresight-replicator";
+ clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ replicator_in: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etf_out>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ replicator_out0: endpoint {
+ remote-endpoint =
+ <&etr_in>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ replicator_out1: endpoint {
+ remote-endpoint =
+ <&tpiu_in>;
+ };
+ };
+ };
+ };
+
+ etr@f6404000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0xf6404000 0 0x1000>;
+ clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ etr_in: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&replicator_out0>;
+ };
+ };
+ };
+ };
+
+ tpiu@f6405000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0 0xf6405000 0 0x1000>;
+ clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ tpiu_in: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&replicator_out1>;
+ };
+ };
+ };
+ };
+
+ funnel@f6501000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0xf6501000 0 0x1000>;
+ clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ acpu_funnel_out: endpoint {
+ remote-endpoint =
+ <&soc_funnel_in>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ acpu_funnel_in0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ acpu_funnel_in1: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm1_out>;
+ };
+ };
+
+ port@3 {
+ reg = <2>;
+ acpu_funnel_in2: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm2_out>;
+ };
+ };
+
+ port@4 {
+ reg = <3>;
+ acpu_funnel_in3: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm3_out>;
+ };
+ };
+
+ port@5 {
+ reg = <4>;
+ acpu_funnel_in4: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm4_out>;
+ };
+ };
+
+ port@6 {
+ reg = <5>;
+ acpu_funnel_in5: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm5_out>;
+ };
+ };
+
+ port@7 {
+ reg = <6>;
+ acpu_funnel_in6: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm6_out>;
+ };
+ };
+
+ port@8 {
+ reg = <7>;
+ acpu_funnel_in7: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm7_out>;
+ };
+ };
+ };
+ };
+
+ etm@f659c000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xf659c000 0 0x1000>;
+
+ clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
+ clock-names = "apb_pclk";
+
+ cpu = <&cpu0>;
+
+ port {
+ etm0_out: endpoint {
+ remote-endpoint =
+ <&acpu_funnel_in0>;
+ };
+ };
+ };
+
+ etm@f659d000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xf659d000 0 0x1000>;
+
+ clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
+ clock-names = "apb_pclk";
+
+ cpu = <&cpu1>;
+
+ port {
+ etm1_out: endpoint {
+ remote-endpoint =
+ <&acpu_funnel_in1>;
+ };
+ };
+ };
+
+ etm@f659e000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xf659e000 0 0x1000>;
+
+ clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
+ clock-names = "apb_pclk";
+
+ cpu = <&cpu2>;
+
+ port {
+ etm2_out: endpoint {
+ remote-endpoint =
+ <&acpu_funnel_in2>;
+ };
+ };
+ };
+
+ etm@f659f000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xf659f000 0 0x1000>;
+
+ clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
+ clock-names = "apb_pclk";
+
+ cpu = <&cpu3>;
+
+ port {
+ etm3_out: endpoint {
+ remote-endpoint =
+ <&acpu_funnel_in3>;
+ };
+ };
+ };
+
+ etm@f65dc000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xf65dc000 0 0x1000>;
+
+ clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
+ clock-names = "apb_pclk";
+
+ cpu = <&cpu4>;
+
+ port {
+ etm4_out: endpoint {
+ remote-endpoint =
+ <&acpu_funnel_in4>;
+ };
+ };
+ };
+
+ etm@f65dd000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xf65dd000 0 0x1000>;
+
+ clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
+ clock-names = "apb_pclk";
+
+ cpu = <&cpu5>;
+
+ port {
+ etm5_out: endpoint {
+ remote-endpoint =
+ <&acpu_funnel_in5>;
+ };
+ };
+ };
+
+ etm@f65de000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xf65de000 0 0x1000>;
+
+ clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
+ clock-names = "apb_pclk";
+
+ cpu = <&cpu6>;
+
+ port {
+ etm6_out: endpoint {
+ remote-endpoint =
+ <&acpu_funnel_in6>;
+ };
+ };
+ };
+
+ etm@f65df000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0xf65df000 0 0x1000>;
+
+ clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
+ clock-names = "apb_pclk";
+
+ cpu = <&cpu7>;
+
+ port {
+ etm7_out: endpoint {
+ remote-endpoint =
+ <&acpu_funnel_in7>;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 02a3aa4..b3b21d7 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -986,3 +986,5 @@
};
};
};
+
+#include "hi6220-coresight.dtsi"
--
2.7.4
On 09/01, Leo Yan wrote:
> This patch series adds support for coresight on Hi6220; the first patch
> is to fix coresight PLL so can avoid system hang after we enable
> coresight, the second patch is to add DT binding according to coresight
> topology.
>
> The patch has been tested on Hikey; By using OpenCSD snapshot mode, it
> can successfully decode ETF and ETB trace data.
>
I can take the first one and second one goes through arm-soc?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On Wed, Nov 01, 2017 at 04:48:50PM +0100, Michael Turquette wrote:
> Quoting Wei Xu (2017-10-13 10:57:02)
> > Hi Leo,
> >
> > On 2017/10/7 13:18, Leo Yan wrote:
> > > Hi Stephen, Wei,
> > >
> > > On Thu, Aug 31, 2017 at 06:33:01PM -0700, Stephen Boyd wrote:
> > >> On 09/01, Leo Yan wrote:
> > >>> This patch series adds support for coresight on Hi6220; the first patch
> > >>> is to fix coresight PLL so can avoid system hang after we enable
> > >>> coresight, the second patch is to add DT binding according to coresight
> > >>> topology.
> > >>>
> > >>> The patch has been tested on Hikey; By using OpenCSD snapshot mode, it
> > >>> can successfully decode ETF and ETB trace data.
> > >>>
> > >>
> > >> I can take the first one and second one goes through arm-soc?
> > >
> > > Could you pick these two patches for Hi6220 coresight enabling for
> > > this merge window? Or need me resend these two patches?
> >
> > Applied patch 2 into hisilicon dt tree with slight fix.
> > Thanks!
>
> Cool. Patch #1 applied to clk tree.
Thanks, Mike and Wei.
> Regards,
> Mike
>
> >
> > BR,
> > Wei
> >
> > >
> > > Thanks,
> > > Leo Yan
From 1582879358203184920@xxx Wed Nov 01 15:49:49 +0000 2017
X-GM-THRID: 1577296285423753778
X-Gmail-Labels: Inbox,Category Forums
Quoting Wei Xu (2017-10-13 10:57:02)
> Hi Leo,
>
> On 2017/10/7 13:18, Leo Yan wrote:
> > Hi Stephen, Wei,
> >
> > On Thu, Aug 31, 2017 at 06:33:01PM -0700, Stephen Boyd wrote:
> >> On 09/01, Leo Yan wrote:
> >>> This patch series adds support for coresight on Hi6220; the first patch
> >>> is to fix coresight PLL so can avoid system hang after we enable
> >>> coresight, the second patch is to add DT binding according to coresight
> >>> topology.
> >>>
> >>> The patch has been tested on Hikey; By using OpenCSD snapshot mode, it
> >>> can successfully decode ETF and ETB trace data.
> >>>
> >>
> >> I can take the first one and second one goes through arm-soc?
> >
> > Could you pick these two patches for Hi6220 coresight enabling for
> > this merge window? Or need me resend these two patches?
>
> Applied patch 2 into hisilicon dt tree with slight fix.
> Thanks!
Cool. Patch #1 applied to clk tree.
Regards,
Mike
>
> BR,
> Wei
>
> >
> > Thanks,
> > Leo Yan
> >
> > .
> >
>
From 1581132322192696235@xxx Fri Oct 13 09:01:26 +0000 2017
X-GM-THRID: 1577296285423753778
X-Gmail-Labels: Inbox,Category Forums
Hi Leo,
On 2017/10/7 13:18, Leo Yan wrote:
> Hi Stephen, Wei,
>
> On Thu, Aug 31, 2017 at 06:33:01PM -0700, Stephen Boyd wrote:
>> On 09/01, Leo Yan wrote:
>>> This patch series adds support for coresight on Hi6220; the first patch
>>> is to fix coresight PLL so can avoid system hang after we enable
>>> coresight, the second patch is to add DT binding according to coresight
>>> topology.
>>>
>>> The patch has been tested on Hikey; By using OpenCSD snapshot mode, it
>>> can successfully decode ETF and ETB trace data.
>>>
>>
>> I can take the first one and second one goes through arm-soc?
>
> Could you pick these two patches for Hi6220 coresight enabling for
> this merge window? Or need me resend these two patches?
Applied patch 2 into hisilicon dt tree with slight fix.
Thanks!
BR,
Wei
>
> Thanks,
> Leo Yan
>
> .
>
From 1580601160965640550@xxx Sat Oct 07 12:18:51 +0000 2017
X-GM-THRID: 1577296285423753778
X-Gmail-Labels: Inbox,Category Forums
Hi Stephen, Wei,
On Thu, Aug 31, 2017 at 06:33:01PM -0700, Stephen Boyd wrote:
> On 09/01, Leo Yan wrote:
> > This patch series adds support for coresight on Hi6220; the first patch
> > is to fix coresight PLL so can avoid system hang after we enable
> > coresight, the second patch is to add DT binding according to coresight
> > topology.
> >
> > The patch has been tested on Hikey; By using OpenCSD snapshot mode, it
> > can successfully decode ETF and ETB trace data.
> >
>
> I can take the first one and second one goes through arm-soc?
Could you pick these two patches for Hi6220 coresight enabling for
this merge window? Or need me resend these two patches?
Thanks,
Leo Yan
From 1577299116338350685@xxx Fri Sep 01 01:34:16 +0000 2017
X-GM-THRID: 1577296285423753778
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