From: Ludovic Barre <[email protected]>
This series adds:
-Management of multi-bank of external interrupts
stm32h7 has up to 96 inputs (3 banks of 32 inputs).
-Fix initial value after cold/hot boot (wakeup issue).
Changes v3:
-remove chip.name and handler, already done by
irq_alloc_domain_generic_chips
-add Rob ack in dt-bindings commit
Changes v2:
-Remove irq_mask and adds const on struct stm32_exti_bank
-Add wrapper functions pending and ack
-Replace BITS_PER_LONG by IRQS_PER_BANK
-Fill commit message on
"ARM: dts: stm32: add support of exti on stm32h743"
-Add system config bank for stm32h7
Ludovic Barre (9):
irqchip: stm32: select GENERIC_IRQ_CHIP
irqchip: stm32: add multi-bank management
dt-bindings: interrupt-controllers: add compatible string for stm32h7
irqchip: stm32: add stm32h7 support
irqchip: stm32: fix initial values
irqchip: stm32: move the wakeup on interrupt mask
ARM: dts: stm32: add exti support for stm32h743
ARM: dts: stm32: add system config bank node for stm32h743
ARM: dts: stm32: add support of exti on stm32h743 pinctrl
.../interrupt-controller/st,stm32-exti.txt | 4 +-
arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 24 +++
arch/arm/boot/dts/stm32h743.dtsi | 13 ++
drivers/irqchip/Kconfig | 1 +
drivers/irqchip/irq-stm32-exti.c | 206 ++++++++++++++++-----
5 files changed, 198 insertions(+), 50 deletions(-)
--
2.7.4
From 1583338358922479186@xxx Mon Nov 06 17:25:27 +0000 2017
X-GM-THRID: 1583338358922479186
X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread
From: Ludovic Barre <[email protected]>
stm32h7 has up to 96 inputs
(3 banks of 32 inputs max).
Signed-off-by: Ludovic Barre <[email protected]>
---
drivers/irqchip/irq-stm32-exti.c | 42 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index ef37870..8f409a9 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -38,6 +38,39 @@ static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
&stm32f4xx_exti_b1,
};
+static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
+ .imr_ofst = 0x80,
+ .emr_ofst = 0x84,
+ .rtsr_ofst = 0x00,
+ .ftsr_ofst = 0x04,
+ .swier_ofst = 0x08,
+ .pr_ofst = 0x88,
+};
+
+static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
+ .imr_ofst = 0x90,
+ .emr_ofst = 0x94,
+ .rtsr_ofst = 0x20,
+ .ftsr_ofst = 0x24,
+ .swier_ofst = 0x28,
+ .pr_ofst = 0x98,
+};
+
+static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
+ .imr_ofst = 0xA0,
+ .emr_ofst = 0xA4,
+ .rtsr_ofst = 0x40,
+ .ftsr_ofst = 0x44,
+ .swier_ofst = 0x48,
+ .pr_ofst = 0xA8,
+};
+
+static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
+ &stm32h7xx_exti_b1,
+ &stm32h7xx_exti_b2,
+ &stm32h7xx_exti_b3,
+};
+
static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
{
const struct stm32_exti_bank *stm32_bank = gc->private;
@@ -256,3 +289,12 @@ static int __init stm32f4_exti_of_init(struct device_node *np,
}
IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
+
+static int __init stm32h7_exti_of_init(struct device_node *np,
+ struct device_node *parent)
+{
+ return stm32_exti_init(stm32h7xx_exti_banks,
+ ARRAY_SIZE(stm32h7xx_exti_banks), np);
+}
+
+IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);
--
2.7.4
From 1583421130156145403@xxx Tue Nov 07 15:21:03 +0000 2017
X-GM-THRID: 1582684052372565644
X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread
From: Ludovic Barre <[email protected]>
This patch adds GENERIC_IRQ_CHIP to stm32 exti
config.
Signed-off-by: Ludovic Barre <[email protected]>
---
drivers/irqchip/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 9d8a1dd..c067aae 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -304,6 +304,7 @@ config EZNPS_GIC
config STM32_EXTI
bool
select IRQ_DOMAIN
+ select GENERIC_IRQ_CHIP
config QCOM_IRQ_COMBINER
bool "QCOM IRQ combiner support"
--
2.7.4
From 1583479467990440959@xxx Wed Nov 08 06:48:19 +0000 2017
X-GM-THRID: 1583460541419970691
X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread
From: Ludovic Barre <[email protected]>
This patch adds support of external interrupt (exti)
for stm32h743.
Signed-off-by: Ludovic Barre <[email protected]>
---
arch/arm/boot/dts/stm32h743.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index 58ec227..6b2fb4c 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -193,6 +193,14 @@
status = "disabled";
};
};
+
+ exti: interrupt-controller@58000000 {
+ compatible = "st,stm32h7-exti";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x58000000 0x400>;
+ interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
+ };
};
};
--
2.7.4
From 1583328928128197602@xxx Mon Nov 06 14:55:33 +0000 2017
X-GM-THRID: 1582827644895169780
X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread
From: Ludovic Barre <[email protected]>
-After cold boot, imr default value depends on hardware configuration.
-After hot reboot the registers must be cleared to avoid residue.
Signed-off-by: Ludovic Barre <[email protected]>
---
drivers/irqchip/irq-stm32-exti.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index 8f409a9..477d0fa 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -258,7 +258,16 @@ __init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks,
writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst);
irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst);
nr_exti = fls(readl_relaxed(base + stm32_bank->rtsr_ofst));
+
+ /*
+ * This IP has no reset, so after hot reboot we should
+ * clear registers to avoid residue
+ */
+ writel_relaxed(0, base + stm32_bank->imr_ofst);
+ writel_relaxed(0, base + stm32_bank->emr_ofst);
writel_relaxed(0, base + stm32_bank->rtsr_ofst);
+ writel_relaxed(0, base + stm32_bank->ftsr_ofst);
+ writel_relaxed(~0UL, base + stm32_bank->pr_ofst);
pr_info("%s: bank%d, External IRQs available:%#x\n",
node->full_name, i, irqs_mask);
--
2.7.4
From 1583328053775027291@xxx Mon Nov 06 14:41:39 +0000 2017
X-GM-THRID: 1583328053775027291
X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread
From: Ludovic Barre <[email protected]>
Move irq_set_wake on interrupt mask, needed to wake up from
low power mode as the event mask is not able to do so.
Signed-off-by: Ludovic Barre <[email protected]>
---
drivers/irqchip/irq-stm32-exti.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index 477d0fa..31ab0de 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -156,16 +156,16 @@ static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
const struct stm32_exti_bank *stm32_bank = gc->private;
int pin = data->hwirq % IRQS_PER_BANK;
- u32 emr;
+ u32 imr;
irq_gc_lock(gc);
- emr = irq_reg_readl(gc, stm32_bank->emr_ofst);
+ imr = irq_reg_readl(gc, stm32_bank->imr_ofst);
if (on)
- emr |= BIT(pin);
+ imr |= BIT(pin);
else
- emr &= ~BIT(pin);
- irq_reg_writel(gc, emr, stm32_bank->emr_ofst);
+ imr &= ~BIT(pin);
+ irq_reg_writel(gc, imr, stm32_bank->imr_ofst);
irq_gc_unlock(gc);
--
2.7.4
From 1588020977851551164@xxx Thu Dec 28 09:53:40 +0000 2017
X-GM-THRID: 1581037569615963952
X-Gmail-Labels: Inbox,Category Forums
From: Ludovic Barre <[email protected]>
This patch adds support of external interrupt (exti) on
all gpio ports of stm32h743.
Signed-off-by: Ludovic Barre <[email protected]>
---
arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
index 76bbd65..df0b441 100644
--- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
@@ -49,6 +49,8 @@
#size-cells = <1>;
compatible = "st,stm32h743-pinctrl";
ranges = <0 0x58020000 0x3000>;
+ interrupt-parent = <&exti>;
+ st,syscfg = <&syscfg 0x8>;
pins-are-numbered;
gpioa: gpio@58020000 {
@@ -57,6 +59,8 @@
reg = <0x0 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOA";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiob: gpio@58020400 {
@@ -65,6 +69,8 @@
reg = <0x400 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOB";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioc: gpio@58020800 {
@@ -73,6 +79,8 @@
reg = <0x800 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOC";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiod: gpio@58020c00 {
@@ -81,6 +89,8 @@
reg = <0xc00 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOD";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioe: gpio@58021000 {
@@ -89,6 +99,8 @@
reg = <0x1000 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOE";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiof: gpio@58021400 {
@@ -97,6 +109,8 @@
reg = <0x1400 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOF";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiog: gpio@58021800 {
@@ -105,6 +119,8 @@
reg = <0x1800 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOG";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioh: gpio@58021c00 {
@@ -113,6 +129,8 @@
reg = <0x1c00 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOH";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioi: gpio@58022000 {
@@ -121,6 +139,8 @@
reg = <0x2000 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOI";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioj: gpio@58022400 {
@@ -129,6 +149,8 @@
reg = <0x2400 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOJ";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiok: gpio@58022800 {
@@ -137,6 +159,8 @@
reg = <0x2800 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOK";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
usart1_pins: usart1@0 {
--
2.7.4
From 1583316228586603129@xxx Mon Nov 06 11:33:41 +0000 2017
X-GM-THRID: 1583309705565702287
X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread
From: Ludovic Barre <[email protected]>
-Prepare to manage multi-bank of external interrupts
(N banks of 32 inputs).
-Prepare to manage registers offsets by compatible
(registers offsets could be different follow per stm32 platform).
Signed-off-by: Ludovic Barre <[email protected]>
---
drivers/irqchip/irq-stm32-exti.c | 149 +++++++++++++++++++++++++++------------
1 file changed, 103 insertions(+), 46 deletions(-)
diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index 45363ff..ef37870 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -14,27 +14,66 @@
#include <linux/of_address.h>
#include <linux/of_irq.h>
-#define EXTI_IMR 0x0
-#define EXTI_EMR 0x4
-#define EXTI_RTSR 0x8
-#define EXTI_FTSR 0xc
-#define EXTI_SWIER 0x10
-#define EXTI_PR 0x14
+#define IRQS_PER_BANK 32
+
+struct stm32_exti_bank {
+ u32 imr_ofst;
+ u32 emr_ofst;
+ u32 rtsr_ofst;
+ u32 ftsr_ofst;
+ u32 swier_ofst;
+ u32 pr_ofst;
+};
+
+static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
+ .imr_ofst = 0x00,
+ .emr_ofst = 0x04,
+ .rtsr_ofst = 0x08,
+ .ftsr_ofst = 0x0C,
+ .swier_ofst = 0x10,
+ .pr_ofst = 0x14,
+};
+
+static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
+ &stm32f4xx_exti_b1,
+};
+
+static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
+{
+ const struct stm32_exti_bank *stm32_bank = gc->private;
+
+ return irq_reg_readl(gc, stm32_bank->pr_ofst);
+}
+
+static void stm32_exti_irq_ack(struct irq_chip_generic *gc, u32 mask)
+{
+ const struct stm32_exti_bank *stm32_bank = gc->private;
+
+ irq_reg_writel(gc, mask, stm32_bank->pr_ofst);
+}
static void stm32_irq_handler(struct irq_desc *desc)
{
struct irq_domain *domain = irq_desc_get_handler_data(desc);
- struct irq_chip_generic *gc = domain->gc->gc[0];
struct irq_chip *chip = irq_desc_get_chip(desc);
+ unsigned int virq, nbanks = domain->gc->num_chips;
+ struct irq_chip_generic *gc;
+ const struct stm32_exti_bank *stm32_bank;
unsigned long pending;
- int n;
+ int n, i, irq_base = 0;
chained_irq_enter(chip, desc);
- while ((pending = irq_reg_readl(gc, EXTI_PR))) {
- for_each_set_bit(n, &pending, BITS_PER_LONG) {
- generic_handle_irq(irq_find_mapping(domain, n));
- irq_reg_writel(gc, BIT(n), EXTI_PR);
+ for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
+ gc = irq_get_domain_generic_chip(domain, irq_base);
+ stm32_bank = gc->private;
+
+ while ((pending = stm32_exti_pending(gc))) {
+ for_each_set_bit(n, &pending, IRQS_PER_BANK) {
+ virq = irq_find_mapping(domain, irq_base + n);
+ generic_handle_irq(virq);
+ stm32_exti_irq_ack(gc, BIT(n));
+ }
}
}
@@ -44,13 +83,14 @@ static void stm32_irq_handler(struct irq_desc *desc)
static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
- int pin = data->hwirq;
+ const struct stm32_exti_bank *stm32_bank = gc->private;
+ int pin = data->hwirq % IRQS_PER_BANK;
u32 rtsr, ftsr;
irq_gc_lock(gc);
- rtsr = irq_reg_readl(gc, EXTI_RTSR);
- ftsr = irq_reg_readl(gc, EXTI_FTSR);
+ rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
+ ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
switch (type) {
case IRQ_TYPE_EDGE_RISING:
@@ -70,8 +110,8 @@ static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
return -EINVAL;
}
- irq_reg_writel(gc, rtsr, EXTI_RTSR);
- irq_reg_writel(gc, ftsr, EXTI_FTSR);
+ irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
+ irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
irq_gc_unlock(gc);
@@ -81,17 +121,18 @@ static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
- int pin = data->hwirq;
+ const struct stm32_exti_bank *stm32_bank = gc->private;
+ int pin = data->hwirq % IRQS_PER_BANK;
u32 emr;
irq_gc_lock(gc);
- emr = irq_reg_readl(gc, EXTI_EMR);
+ emr = irq_reg_readl(gc, stm32_bank->emr_ofst);
if (on)
emr |= BIT(pin);
else
emr &= ~BIT(pin);
- irq_reg_writel(gc, emr, EXTI_EMR);
+ irq_reg_writel(gc, emr, stm32_bank->emr_ofst);
irq_gc_unlock(gc);
@@ -101,11 +142,12 @@ static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
unsigned int nr_irqs, void *data)
{
- struct irq_chip_generic *gc = d->gc->gc[0];
+ struct irq_chip_generic *gc;
struct irq_fwspec *fwspec = data;
irq_hw_number_t hwirq;
hwirq = fwspec->param[0];
+ gc = irq_get_domain_generic_chip(d, hwirq);
irq_map_generic_chip(d, virq, hwirq);
irq_domain_set_info(d, virq, hwirq, &gc->chip_types->chip, gc,
@@ -129,8 +171,9 @@ struct irq_domain_ops irq_exti_domain_ops = {
.free = stm32_exti_free,
};
-static int __init stm32_exti_init(struct device_node *node,
- struct device_node *parent)
+static int
+__init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks,
+ int bank_nr, struct device_node *node)
{
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
int nr_irqs, nr_exti, ret, i;
@@ -144,23 +187,16 @@ static int __init stm32_exti_init(struct device_node *node,
return -ENOMEM;
}
- /* Determine number of irqs supported */
- writel_relaxed(~0UL, base + EXTI_RTSR);
- nr_exti = fls(readl_relaxed(base + EXTI_RTSR));
- writel_relaxed(0, base + EXTI_RTSR);
-
- pr_info("%pOF: %d External IRQs detected\n", node, nr_exti);
-
- domain = irq_domain_add_linear(node, nr_exti,
+ domain = irq_domain_add_linear(node, bank_nr * IRQS_PER_BANK,
&irq_exti_domain_ops, NULL);
if (!domain) {
pr_err("%s: Could not register interrupt domain.\n",
- node->name);
+ node->name);
ret = -ENOMEM;
goto out_unmap;
}
- ret = irq_alloc_domain_generic_chips(domain, nr_exti, 1, "exti",
+ ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
handle_edge_irq, clr, 0, 0);
if (ret) {
pr_err("%pOF: Could not allocate generic interrupt chip.\n",
@@ -168,18 +204,32 @@ static int __init stm32_exti_init(struct device_node *node,
goto out_free_domain;
}
- gc = domain->gc->gc[0];
- gc->reg_base = base;
- gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
- gc->chip_types->chip.name = gc->chip_types[0].chip.name;
- gc->chip_types->chip.irq_ack = irq_gc_ack_set_bit;
- gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
- gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
- gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
- gc->chip_types->chip.irq_set_wake = stm32_irq_set_wake;
- gc->chip_types->regs.ack = EXTI_PR;
- gc->chip_types->regs.mask = EXTI_IMR;
- gc->chip_types->handler = handle_edge_irq;
+ for (i = 0; i < bank_nr; i++) {
+ const struct stm32_exti_bank *stm32_bank = stm32_exti_banks[i];
+ u32 irqs_mask;
+
+ gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
+
+ gc->reg_base = base;
+ gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
+ gc->chip_types->chip.irq_ack = irq_gc_ack_set_bit;
+ gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
+ gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
+ gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
+ gc->chip_types->chip.irq_set_wake = stm32_irq_set_wake;
+ gc->chip_types->regs.ack = stm32_bank->pr_ofst;
+ gc->chip_types->regs.mask = stm32_bank->imr_ofst;
+ gc->private = (void *)stm32_bank;
+
+ /* Determine number of irqs supported */
+ writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst);
+ irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst);
+ nr_exti = fls(readl_relaxed(base + stm32_bank->rtsr_ofst));
+ writel_relaxed(0, base + stm32_bank->rtsr_ofst);
+
+ pr_info("%s: bank%d, External IRQs available:%#x\n",
+ node->full_name, i, irqs_mask);
+ }
nr_irqs = of_irq_count(node);
for (i = 0; i < nr_irqs; i++) {
@@ -198,4 +248,11 @@ static int __init stm32_exti_init(struct device_node *node,
return ret;
}
-IRQCHIP_DECLARE(stm32_exti, "st,stm32-exti", stm32_exti_init);
+static int __init stm32f4_exti_of_init(struct device_node *np,
+ struct device_node *parent)
+{
+ return stm32_exti_init(stm32f4xx_exti_banks,
+ ARRAY_SIZE(stm32f4xx_exti_banks), np);
+}
+
+IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
--
2.7.4
From 1583337373540756143@xxx Mon Nov 06 17:09:47 +0000 2017
X-GM-THRID: 1577868220909329273
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From: Ludovic Barre <[email protected]>
This patch updates stm32-exti documentation with stm32h7-exti
compatible string.
Signed-off-by: Ludovic Barre <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
.../devicetree/bindings/interrupt-controller/st,stm32-exti.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
index 6e7703d..edf03f0 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt
@@ -2,7 +2,9 @@ STM32 External Interrupt Controller
Required properties:
-- compatible: Should be "st,stm32-exti"
+- compatible: Should be:
+ "st,stm32-exti"
+ "st,stm32h7-exti"
- reg: Specifies base physical address and size of the registers
- interrupt-controller: Indentifies the node as an interrupt controller
- #interrupt-cells: Specifies the number of cells to encode an interrupt
--
2.7.4
From 1583306643518986832@xxx Mon Nov 06 09:01:20 +0000 2017
X-GM-THRID: 1583306643518986832
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From: Ludovic Barre <[email protected]>
This patch adds system config support for stm32h743.
Signed-off-by: Ludovic Barre <[email protected]>
---
arch/arm/boot/dts/stm32h743.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index 6b2fb4c..b17aa5c 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -194,6 +194,11 @@
};
};
+ syscfg: system-config@58000400 {
+ compatible = "syscon";
+ reg = <0x58000400 0x400>;
+ };
+
exti: interrupt-controller@58000000 {
compatible = "st,stm32h7-exti";
interrupt-controller;
--
2.7.4
From 1583306752483117020@xxx Mon Nov 06 09:03:04 +0000 2017
X-GM-THRID: 1583306752483117020
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