This series is the successor to
https://www.spinics.net/lists/platform-driver-x86/msg14524.html and adds
support for Intel Coffeelake and Cannonlake SoCs.
This also presents an alternative to https://lkml.org/lkml/2017/11/17/876
and introduces Cannonlake SoC to intel-family.h
The following patches,
'0003-ACPI-LPIT-Export-lpit_read_residency_count_address.patch' and
'0006-x86-cpu-Add-Cannonlake-to-Intel-family.patch'
do not belong to platform-drivers-x86 subsystem but the other patches in the
series depend on them so, requesting the respective MAINTAINERS for their
review and ACK so that these two patches can also go through the
platform-drivers-x86 subsystem.
Cc: Rafael J. Wysocki <[email protected]>
Cc: Len Brown <[email protected]>
Cc: [email protected]
Cc: Dave Hansen <[email protected]>
Cc: Thomas Gleixner <[email protected]>
cc: Ingo Molnar <[email protected]>
Cc: "H. Peter Anvin" <[email protected]>
Cc: [email protected]
Tested on Coffeelake, Cannonlake and Kabylake with 4.15-rc8 kernel.
Rajneesh Bhardwaj (5):
platform/x86: intel_pmc_core: Refactor debugfs entries
platform/x86: intel_pmc_core: Convert to ICPU macro
x86/cpu: Add Cannonlake to Intel family
platform/x86: intel_pmc_core: Add CannonLake PCH support
platform/x86: intel_pmc_core: Special case for Coffeelake
Srinivas Pandruvada (3):
platform/x86: intel_pmc_core: Substitute PCI with CPUID enumeration
ACPI / LPIT: Export lpit_read_residency_count_address()
platform/x86: intel_pmc_core: Read base address from LPIT
arch/x86/include/asm/intel-family.h | 6 +
drivers/acpi/acpi_lpit.c | 1 +
drivers/platform/x86/intel_pmc_core.c | 242 +++++++++++++++++++++-------------
drivers/platform/x86/intel_pmc_core.h | 14 +-
4 files changed, 174 insertions(+), 89 deletions(-)
--
2.7.4
From: Srinivas Pandruvada <[email protected]>
Export lpit_read_residency_count_address(), so that it can be used from
drivers built as module. With the recent changes, the builtin_pci
functionality of the intel_pmc_core driver is removed and now it can be
built as a module to read this exported interface to calculate the PMC base
address.
Cc: Rafael J. Wysocki <[email protected]>
Cc: Len Brown <[email protected]>
Cc: [email protected]
Tested-by: Rajneesh Bhardwaj <[email protected]>
Signed-off-by: Srinivas Pandruvada <[email protected]>
---
drivers/acpi/acpi_lpit.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/acpi/acpi_lpit.c b/drivers/acpi/acpi_lpit.c
index e94e478dd18b..cf4fc0161164 100644
--- a/drivers/acpi/acpi_lpit.c
+++ b/drivers/acpi/acpi_lpit.c
@@ -100,6 +100,7 @@ int lpit_read_residency_count_address(u64 *address)
return 0;
}
+EXPORT_SYMBOL_GPL(lpit_read_residency_count_address);
static void lpit_update_residency(struct lpit_residency_info *info,
struct acpi_lpit_native *lpit_native)
--
2.7.4
From: Srinivas Pandruvada <[email protected]>
Read SLP_S0 address from ACPI LPIT table when present and use PMC
specific SLP_S0 offset to get the base address of PMC MMIO.
Signed-off-by: Rajneesh Bhardwaj <[email protected]>
Signed-off-by: Srinivas Pandruvada <[email protected]>
---
drivers/platform/x86/intel_pmc_core.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index f7616600e8ab..549ee5852d4f 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -20,6 +20,7 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+#include <linux/acpi.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/io.h>
@@ -455,6 +456,7 @@ static int __init pmc_core_probe(void)
{
const struct x86_cpu_id *cpu_id;
struct pmc_dev *pmcdev = &pmc;
+ u64 slp_s0_addr;
int err;
cpu_id = x86_match_cpu(intel_pmc_core_ids);
@@ -462,7 +464,12 @@ static int __init pmc_core_probe(void)
return -ENODEV;
pmcdev->map = (struct pmc_reg_map *)cpu_id->driver_data;
- pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT;
+
+ if (lpit_read_residency_count_address(&slp_s0_addr))
+ pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT;
+ else
+ pmcdev->base_addr = slp_s0_addr - pmcdev->map->slp_s0_offset;
+
pmcdev->regbase = ioremap(pmcdev->base_addr,
pmcdev->map->regmap_length);
if (!pmcdev->regbase)
--
2.7.4
When on a platform if we can't show MPHY and PLL status, don't even bother
to create a debugfs entry as it will fail anyway. In fact unless OEM builds
a special BIOS for test, it will fail on every production system.
This will help to add future platform support where we can't support these
entries.
Suggested-by: Andriy Shevchenko <[email protected]>
Signed-off-by: Srinivas Pandruvada <[email protected]>
Signed-off-by: Rajneesh Bhardwaj <[email protected]>
---
drivers/platform/x86/intel_pmc_core.c | 44 +++++++++++++----------------------
1 file changed, 16 insertions(+), 28 deletions(-)
diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index cf8b3b34a979..43cee8877ee3 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -407,43 +407,31 @@ static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
{
- struct dentry *dir, *file;
- dir = debugfs_create_dir("pmc_core", NULL);
- if (!dir)
- return -ENOMEM;
+ pmcdev->dbgfs_dir = debugfs_create_dir("pmc_core", NULL);
- pmcdev->dbgfs_dir = dir;
- file = debugfs_create_file("slp_s0_residency_usec", 0444,
- dir, pmcdev, &pmc_core_dev_state);
- if (!file)
- goto err;
+ if (!pmcdev->dbgfs_dir)
+ return -ENOMEM;
- file = debugfs_create_file("pch_ip_power_gating_status", 0444,
- dir, pmcdev, &pmc_core_ppfear_ops);
- if (!file)
- goto err;
+ debugfs_create_file("slp_s0_residency_usec", 0444, pmcdev->dbgfs_dir,
+ pmcdev, &pmc_core_dev_state);
- file = debugfs_create_file("mphy_core_lanes_power_gating_status", 0444,
- dir, pmcdev, &pmc_core_mphy_pg_ops);
- if (!file)
- goto err;
+ debugfs_create_file("pch_ip_power_gating_status", 0444,
+ pmcdev->dbgfs_dir, pmcdev, &pmc_core_ppfear_ops);
- file = debugfs_create_file("pll_status", 0444, dir, pmcdev,
- &pmc_core_pll_ops);
- if (!file)
- goto err;
+ debugfs_create_file("ltr_ignore", 0644, pmcdev->dbgfs_dir, pmcdev,
+ &pmc_core_ltr_ignore_ops);
- file = debugfs_create_file("ltr_ignore", 0644, dir, pmcdev,
- &pmc_core_ltr_ignore_ops);
+ if (pmcdev->map->pll_sts)
+ debugfs_create_file("pll_status", 0444, pmcdev->dbgfs_dir,
+ pmcdev, &pmc_core_pll_ops);
- if (!file)
- goto err;
+ if (pmcdev->map->mphy_sts)
+ debugfs_create_file("mphy_core_lanes_power_gating_status",
+ 0444, pmcdev->dbgfs_dir, pmcdev,
+ &pmc_core_mphy_pg_ops);
return 0;
-err:
- pmc_core_dbgfs_unregister(pmcdev);
- return -ENODEV;
}
#else
static inline int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
--
2.7.4
From: Srinivas Pandruvada <[email protected]>
The Only use of PCI device enumeration here is to get the PMC base address
which is a fixed value i.e. 0xFE000000. On some platforms this can be read
through a non standard PCI BAR. But after Kabylake, PMC is not exposed as a
PCI device anymore. There are other non standard methods like ACPI LPIT
which can also be used for obtaining this value.
For simplicity, this value can be hardcoded as it won't change.
Since we don't have a PMC PCI device on any platform after Kabylake, this
creates a foundation for future SoC support.
Signed-off-by: Rajneesh Bhardwaj <[email protected]>
Signed-off-by: Srinivas Pandruvada <[email protected]>
---
drivers/platform/x86/intel_pmc_core.c | 91 ++++++++++++-----------------------
drivers/platform/x86/intel_pmc_core.h | 3 +-
2 files changed, 33 insertions(+), 61 deletions(-)
diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index 43cee8877ee3..f7616600e8ab 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -18,12 +18,12 @@
*
*/
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
#include <linux/debugfs.h>
#include <linux/delay.h>
-#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
-#include <linux/pci.h>
#include <linux/uaccess.h>
#include <asm/cpu_device_id.h>
@@ -119,13 +119,6 @@ static const struct pmc_reg_map spt_reg_map = {
.pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
};
-static const struct pci_device_id pmc_pci_ids[] = {
- { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID),
- (kernel_ulong_t)&spt_reg_map },
- { 0, },
-};
-MODULE_DEVICE_TABLE(pci, pmc_pci_ids);
-
static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
{
return readb(pmcdev->regbase + offset);
@@ -446,79 +439,59 @@ static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
static const struct x86_cpu_id intel_pmc_core_ids[] = {
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_MOBILE, X86_FEATURE_MWAIT,
- (kernel_ulong_t)NULL},
+ (kernel_ulong_t)&spt_reg_map},
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_DESKTOP, X86_FEATURE_MWAIT,
- (kernel_ulong_t)NULL},
+ (kernel_ulong_t)&spt_reg_map},
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_KABYLAKE_MOBILE, X86_FEATURE_MWAIT,
- (kernel_ulong_t)NULL},
+ (kernel_ulong_t)&spt_reg_map},
{ X86_VENDOR_INTEL, 6, INTEL_FAM6_KABYLAKE_DESKTOP, X86_FEATURE_MWAIT,
- (kernel_ulong_t)NULL},
+ (kernel_ulong_t)&spt_reg_map},
{}
};
-static int pmc_core_probe(struct pci_dev *dev, const struct pci_device_id *id)
+MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_ids);
+
+static int __init pmc_core_probe(void)
{
- struct device *ptr_dev = &dev->dev;
- struct pmc_dev *pmcdev = &pmc;
const struct x86_cpu_id *cpu_id;
- const struct pmc_reg_map *map = (struct pmc_reg_map *)id->driver_data;
+ struct pmc_dev *pmcdev = &pmc;
int err;
cpu_id = x86_match_cpu(intel_pmc_core_ids);
- if (!cpu_id) {
- dev_dbg(&dev->dev, "PMC Core: cpuid mismatch.\n");
- return -EINVAL;
- }
-
- err = pcim_enable_device(dev);
- if (err < 0) {
- dev_dbg(&dev->dev, "PMC Core: failed to enable Power Management Controller.\n");
- return err;
- }
-
- err = pci_read_config_dword(dev,
- SPT_PMC_BASE_ADDR_OFFSET,
- &pmcdev->base_addr);
- if (err < 0) {
- dev_dbg(&dev->dev, "PMC Core: failed to read PCI config space.\n");
- return err;
- }
- pmcdev->base_addr &= PMC_BASE_ADDR_MASK;
- dev_dbg(&dev->dev, "PMC Core: PWRMBASE is %#x\n", pmcdev->base_addr);
-
- pmcdev->regbase = devm_ioremap_nocache(ptr_dev,
- pmcdev->base_addr,
- SPT_PMC_MMIO_REG_LEN);
- if (!pmcdev->regbase) {
- dev_dbg(&dev->dev, "PMC Core: ioremap failed.\n");
+ if (!cpu_id)
+ return -ENODEV;
+
+ pmcdev->map = (struct pmc_reg_map *)cpu_id->driver_data;
+ pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT;
+ pmcdev->regbase = ioremap(pmcdev->base_addr,
+ pmcdev->map->regmap_length);
+ if (!pmcdev->regbase)
return -ENOMEM;
- }
mutex_init(&pmcdev->lock);
- pmcdev->map = map;
pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit();
err = pmc_core_dbgfs_register(pmcdev);
- if (err < 0)
- dev_warn(&dev->dev, "PMC Core: debugfs register failed.\n");
+ if (err < 0) {
+ pr_warn(" debugfs register failed.\n");
+ iounmap(pmcdev->regbase);
+ return err;
+ }
+ pr_info(" initialized\n");
return 0;
}
+module_init(pmc_core_probe)
-static void pmc_core_remove(struct pci_dev *dev)
+static void __exit pmc_core_remove(void)
{
- pmc_core_dbgfs_unregister(&pmc);
- mutex_destroy(&pmc.lock);
-}
-
-static struct pci_driver intel_pmc_core_driver = {
- .name = "intel_pmc_core",
- .id_table = pmc_pci_ids,
- .probe = pmc_core_probe,
- .remove = pmc_core_remove,
-};
+ struct pmc_dev *pmcdev = &pmc;
-module_pci_driver(intel_pmc_core_driver);
+ pmc_core_dbgfs_unregister(pmcdev);
+ mutex_destroy(&pmcdev->lock);
+ iounmap(pmcdev->regbase);
+}
+module_exit(pmc_core_remove)
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Intel PMC Core Driver");
diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h
index e3be1d2b08cd..9df4a60a179f 100644
--- a/drivers/platform/x86/intel_pmc_core.h
+++ b/drivers/platform/x86/intel_pmc_core.h
@@ -21,8 +21,7 @@
#ifndef PMC_CORE_H
#define PMC_CORE_H
-/* Sunrise Point Power Management Controller PCI Device ID */
-#define SPT_PMC_PCI_DEVICE_ID 0x9d21
+#define PMC_BASE_ADDR_DEFAULT 0xFE000000
#define SPT_PMC_BASE_ADDR_OFFSET 0x48
#define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET 0x13c
--
2.7.4
Use ICPU macro to refactor code related to x86_cpu_id for better
readability.
Suggested-by: Andriy Shevchenko <[email protected]>
Signed-off-by: Srinivas Pandruvada <[email protected]>
Signed-off-by: Rajneesh Bhardwaj <[email protected]>
---
drivers/platform/x86/intel_pmc_core.c | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index 549ee5852d4f..da9326740647 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -33,6 +33,9 @@
#include "intel_pmc_core.h"
+#define ICPU(cpu, data) \
+ { X86_VENDOR_INTEL, 6, cpu, X86_FEATURE_MWAIT, (kernel_ulong_t)data }
+
static struct pmc_dev pmc;
static const struct pmc_bit_map spt_pll_map[] = {
@@ -439,14 +442,10 @@ static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
#endif /* CONFIG_DEBUG_FS */
static const struct x86_cpu_id intel_pmc_core_ids[] = {
- { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_MOBILE, X86_FEATURE_MWAIT,
- (kernel_ulong_t)&spt_reg_map},
- { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_DESKTOP, X86_FEATURE_MWAIT,
- (kernel_ulong_t)&spt_reg_map},
- { X86_VENDOR_INTEL, 6, INTEL_FAM6_KABYLAKE_MOBILE, X86_FEATURE_MWAIT,
- (kernel_ulong_t)&spt_reg_map},
- { X86_VENDOR_INTEL, 6, INTEL_FAM6_KABYLAKE_DESKTOP, X86_FEATURE_MWAIT,
- (kernel_ulong_t)&spt_reg_map},
+ ICPU(INTEL_FAM6_SKYLAKE_MOBILE, &spt_reg_map),
+ ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, &spt_reg_map),
+ ICPU(INTEL_FAM6_KABYLAKE_MOBILE, &spt_reg_map),
+ ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, &spt_reg_map),
{}
};
--
2.7.4
Intel CoffeeLake SoC uses CPU ID of KabyLake but has Cannonlake PCH, so in
this case PMC register details from Cannonlake PCH must be used.
In order to identify whether the given platform is Coffeelake, scan for the
Sunrisepoint PMC PCI Id.
KBL CPUID SPT PCIID
-------------------------------------
KBL | Y | Y |
-------------------------------------
CFL | Y | N |
-------------------------------------
Signed-off-by: Srinivas Pandruvada <[email protected]>
Signed-off-by: Rajneesh Bhardwaj <[email protected]>
---
drivers/platform/x86/intel_pmc_core.c | 14 ++++++++++++++
drivers/platform/x86/intel_pmc_core.h | 2 ++
2 files changed, 16 insertions(+)
diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index f0d067a33a56..67e85ee4ab32 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -25,6 +25,7 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
+#include <linux/pci.h>
#include <linux/uaccess.h>
#include <asm/cpu_device_id.h>
@@ -536,6 +537,11 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = {
MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_ids);
+static const struct pci_device_id pmc_pci_ids[] = {
+ { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID), 0},
+ { 0, },
+};
+
static int __init pmc_core_probe(void)
{
const struct x86_cpu_id *cpu_id;
@@ -549,6 +555,14 @@ static int __init pmc_core_probe(void)
pmcdev->map = (struct pmc_reg_map *)cpu_id->driver_data;
+ /*
+ * Coffeelake has CPU ID of Kabylake and Cannonlake PCH. So here
+ * Sunrisepoint PCH regmap can't be used. Use Cannonlake PCH regmap
+ * in this case.
+ */
+ if (!pci_dev_present(pmc_pci_ids))
+ pmcdev->map = (struct pmc_reg_map *)&cnp_reg_map;
+
if (lpit_read_residency_count_address(&slp_s0_addr))
pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT;
else
diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h
index 8b7731e6dea2..5fa5f97870aa 100644
--- a/drivers/platform/x86/intel_pmc_core.h
+++ b/drivers/platform/x86/intel_pmc_core.h
@@ -23,6 +23,8 @@
#define PMC_BASE_ADDR_DEFAULT 0xFE000000
+/* Sunrise Point Power Management Controller PCI Device ID */
+#define SPT_PMC_PCI_DEVICE_ID 0x9d21
#define SPT_PMC_BASE_ADDR_OFFSET 0x48
#define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET 0x13c
#define SPT_PMC_PM_CFG_OFFSET 0x18
--
2.7.4
Add CPUID of Cannonlake (CNL) processors to Intel family list.
Cc: Dave Hansen <[email protected]>
Cc: Thomas Gleixner <[email protected]>
cc: Ingo Molnar <[email protected]>
Cc: "H. Peter Anvin" <[email protected]>
Cc: [email protected]
Suggested-by: Tony Luck <[email protected]>
Signed-off-by: Megha Dey <[email protected]>
Signed-off-by: Rajneesh Bhardwaj <[email protected]>
---
arch/x86/include/asm/intel-family.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
index 35a6bc4da8ad..cf090e584202 100644
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -10,6 +10,10 @@
*
* Things ending in "2" are usually because we have no better
* name for them. There's no processor called "SILVERMONT2".
+ *
+ * While adding a new CPUID for a new microarchitecture, add a new
+ * group to keep logically sorted out in chronological order. Within
+ * that group keep the CPUID for the variants sorted by model number.
*/
#define INTEL_FAM6_CORE_YONAH 0x0E
@@ -49,6 +53,8 @@
#define INTEL_FAM6_KABYLAKE_MOBILE 0x8E
#define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E
+#define INTEL_FAM6_CANNONLAKE_MOBILE 0x66
+
/* "Small Core" Processors (Atom) */
#define INTEL_FAM6_ATOM_PINEVIEW 0x1C
--
2.7.4
This adds support for Cannonlake PCH which is used by Cannonlake and
Coffeelake SoCs.
Signed-off-by: Srinivas Pandruvada <[email protected]>
Signed-off-by: Rajneesh Bhardwaj <[email protected]>
---
drivers/platform/x86/intel_pmc_core.c | 85 +++++++++++++++++++++++++++++++++++
drivers/platform/x86/intel_pmc_core.h | 11 +++++
2 files changed, 96 insertions(+)
diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index da9326740647..f0d067a33a56 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -123,6 +123,90 @@ static const struct pmc_reg_map spt_reg_map = {
.pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
};
+/* Cannonlake: PGD PFET Enable Ack Status Register(s) bitmap */
+static const struct pmc_bit_map cnp_pfear_map[] = {
+ {"PMC", BIT(0)},
+ {"OPI-DMI", BIT(1)},
+ {"SPI/eSPI", BIT(2)},
+ {"XHCI", BIT(3)},
+ {"SPA", BIT(4)},
+ {"SPB", BIT(5)},
+ {"SPC", BIT(6)},
+ {"GBE", BIT(7)},
+
+ {"SATA", BIT(0)},
+ {"HDA_PGD0", BIT(1)},
+ {"HDA_PGD1", BIT(2)},
+ {"HDA_PGD2", BIT(3)},
+ {"HDA_PGD3", BIT(4)},
+ {"SPD", BIT(5)},
+ {"LPSS", BIT(6)},
+ {"LPC", BIT(7)},
+
+ {"SMB", BIT(0)},
+ {"ISH", BIT(1)},
+ {"P2SB", BIT(2)},
+ {"NPK_VNN", BIT(3)},
+ {"SDX", BIT(4)},
+ {"SPE", BIT(5)},
+ {"Fuse", BIT(6)},
+ {"Res_23", BIT(7)},
+
+ {"CSME_FSC", BIT(0)},
+ {"USB3_OTG", BIT(1)},
+ {"EXI", BIT(2)},
+ {"CSE", BIT(3)},
+ {"csme_kvm", BIT(4)},
+ {"csme_pmt", BIT(5)},
+ {"csme_clink", BIT(6)},
+ {"csme_ptio", BIT(7)},
+
+ {"csme_usbr", BIT(0)},
+ {"csme_susram", BIT(1)},
+ {"csme_smt1", BIT(2)},
+ {"CSME_SMT4", BIT(3)},
+ {"csme_sms2", BIT(4)},
+ {"csme_sms1", BIT(5)},
+ {"csme_rtc", BIT(6)},
+ {"csme_psf", BIT(7)},
+
+ {"SBR0", BIT(0)},
+ {"SBR1", BIT(1)},
+ {"SBR2", BIT(2)},
+ {"SBR3", BIT(3)},
+ {"SBR4", BIT(4)},
+ {"SBR5", BIT(5)},
+ {"CSME_PECI", BIT(6)},
+ {"PSF1", BIT(7)},
+
+ {"PSF2", BIT(0)},
+ {"PSF3", BIT(1)},
+ {"PSF4", BIT(2)},
+ {"CNVI", BIT(3)},
+ {"UFS0", BIT(4)},
+ {"EMMC", BIT(5)},
+ {"Res_6", BIT(6)},
+ {"SBR6", BIT(7)},
+
+ {"SBR7", BIT(0)},
+ {"NPK_AON", BIT(1)},
+ {"HDA_PGD4", BIT(2)},
+ {"HDA_PGD5", BIT(3)},
+ {"HDA_PGD6", BIT(4)},
+ {}
+};
+
+static const struct pmc_reg_map cnp_reg_map = {
+ .pfear_sts = cnp_pfear_map,
+ .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
+ .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
+ .regmap_length = CNP_PMC_MMIO_REG_LEN,
+ .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
+ .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
+ .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
+ .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
+};
+
static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
{
return readb(pmcdev->regbase + offset);
@@ -446,6 +530,7 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = {
ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, &spt_reg_map),
ICPU(INTEL_FAM6_KABYLAKE_MOBILE, &spt_reg_map),
ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, &spt_reg_map),
+ ICPU(INTEL_FAM6_CANNONLAKE_MOBILE, &cnp_reg_map),
{}
};
diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h
index 9df4a60a179f..8b7731e6dea2 100644
--- a/drivers/platform/x86/intel_pmc_core.h
+++ b/drivers/platform/x86/intel_pmc_core.h
@@ -121,6 +121,17 @@ enum ppfear_regs {
#define SPT_PMC_BIT_MPHY_CMN_LANE2 BIT(2)
#define SPT_PMC_BIT_MPHY_CMN_LANE3 BIT(3)
+/* Cannonlake Power Management Controller register offsets */
+#define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET 0x193C
+#define CNP_PMC_LTR_IGNORE_OFFSET 0x1B0C
+#define CNP_PMC_PM_CFG_OFFSET 0x1818
+/* Cannonlake: PGD PFET Enable Ack Status Register(s) start */
+#define CNP_PMC_HOST_PPFEAR0A 0x1D90
+
+#define CNP_PMC_MMIO_REG_LEN 0x2000
+#define CNP_PPFEAR_NUM_ENTRIES 8
+#define CNP_PMC_READ_DISABLE_BIT 22
+
struct pmc_bit_map {
const char *name;
u32 bit_mask;
--
2.7.4
On Fri, Jan 19, 2018 at 10:58 AM, Rajneesh Bhardwaj
<[email protected]> wrote:
> From: Srinivas Pandruvada <[email protected]>
>
> Export lpit_read_residency_count_address(), so that it can be used from
> drivers built as module. With the recent changes, the builtin_pci
> functionality of the intel_pmc_core driver is removed and now it can be
> built as a module to read this exported interface to calculate the PMC base
> address.
>
This needs Ack from ACPI maintainer(s).
Rafael, are you OK with exporting this method?
> Cc: Rafael J. Wysocki <[email protected]>
> Cc: Len Brown <[email protected]>
> Cc: [email protected]
>
> Tested-by: Rajneesh Bhardwaj <[email protected]>
> Signed-off-by: Srinivas Pandruvada <[email protected]>
> ---
>
> drivers/acpi/acpi_lpit.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/acpi/acpi_lpit.c b/drivers/acpi/acpi_lpit.c
> index e94e478dd18b..cf4fc0161164 100644
> --- a/drivers/acpi/acpi_lpit.c
> +++ b/drivers/acpi/acpi_lpit.c
> @@ -100,6 +100,7 @@ int lpit_read_residency_count_address(u64 *address)
>
> return 0;
> }
> +EXPORT_SYMBOL_GPL(lpit_read_residency_count_address);
>
> static void lpit_update_residency(struct lpit_residency_info *info,
> struct acpi_lpit_native *lpit_native)
> --
> 2.7.4
>
--
With Best Regards,
Andy Shevchenko
On Fri, Jan 19, 2018 at 10:58 AM, Rajneesh Bhardwaj
<[email protected]> wrote:
> Add CPUID of Cannonlake (CNL) processors to Intel family list.
>
> Cc: Dave Hansen <[email protected]>
> Cc: Thomas Gleixner <[email protected]>
> cc: Ingo Molnar <[email protected]>
> Cc: "H. Peter Anvin" <[email protected]>
> Cc: [email protected]
Thomas, can you Ack this patch?
> Suggested-by: Tony Luck <[email protected]>
> Signed-off-by: Megha Dey <[email protected]>
> Signed-off-by: Rajneesh Bhardwaj <[email protected]>
> ---
> arch/x86/include/asm/intel-family.h | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
> index 35a6bc4da8ad..cf090e584202 100644
> --- a/arch/x86/include/asm/intel-family.h
> +++ b/arch/x86/include/asm/intel-family.h
> @@ -10,6 +10,10 @@
> *
> * Things ending in "2" are usually because we have no better
> * name for them. There's no processor called "SILVERMONT2".
> + *
> + * While adding a new CPUID for a new microarchitecture, add a new
> + * group to keep logically sorted out in chronological order. Within
> + * that group keep the CPUID for the variants sorted by model number.
> */
>
> #define INTEL_FAM6_CORE_YONAH 0x0E
> @@ -49,6 +53,8 @@
> #define INTEL_FAM6_KABYLAKE_MOBILE 0x8E
> #define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E
>
> +#define INTEL_FAM6_CANNONLAKE_MOBILE 0x66
> +
> /* "Small Core" Processors (Atom) */
>
> #define INTEL_FAM6_ATOM_PINEVIEW 0x1C
> --
> 2.7.4
>
--
With Best Regards,
Andy Shevchenko
On Fri, Jan 19, 2018 at 10:58 AM, Rajneesh Bhardwaj
<[email protected]> wrote:
> This series is the successor to
> https://www.spinics.net/lists/platform-driver-x86/msg14524.html and adds
> support for Intel Coffeelake and Cannonlake SoCs.
>
> This also presents an alternative to https://lkml.org/lkml/2017/11/17/876
> and introduces Cannonlake SoC to intel-family.h
>
> The following patches,
>
> '0003-ACPI-LPIT-Export-lpit_read_residency_count_address.patch' and
> '0006-x86-cpu-Add-Cannonlake-to-Intel-family.patch'
>
> do not belong to platform-drivers-x86 subsystem but the other patches in the
> series depend on them so, requesting the respective MAINTAINERS for their
> review and ACK so that these two patches can also go through the
> platform-drivers-x86 subsystem.
I have applied 1,2, and 5 to my review and testing queue, thanks!
P.S. Please, rebase and sent new version when patches 3 and 6 will get ACKa
> Cc: Rafael J. Wysocki <[email protected]>
> Cc: Len Brown <[email protected]>
> Cc: [email protected]
>
> Cc: Dave Hansen <[email protected]>
> Cc: Thomas Gleixner <[email protected]>
> cc: Ingo Molnar <[email protected]>
> Cc: "H. Peter Anvin" <[email protected]>
> Cc: [email protected]
>
> Tested on Coffeelake, Cannonlake and Kabylake with 4.15-rc8 kernel.
>
> Rajneesh Bhardwaj (5):
> platform/x86: intel_pmc_core: Refactor debugfs entries
> platform/x86: intel_pmc_core: Convert to ICPU macro
> x86/cpu: Add Cannonlake to Intel family
> platform/x86: intel_pmc_core: Add CannonLake PCH support
> platform/x86: intel_pmc_core: Special case for Coffeelake
>
> Srinivas Pandruvada (3):
> platform/x86: intel_pmc_core: Substitute PCI with CPUID enumeration
> ACPI / LPIT: Export lpit_read_residency_count_address()
> platform/x86: intel_pmc_core: Read base address from LPIT
>
> arch/x86/include/asm/intel-family.h | 6 +
> drivers/acpi/acpi_lpit.c | 1 +
> drivers/platform/x86/intel_pmc_core.c | 242 +++++++++++++++++++++-------------
> drivers/platform/x86/intel_pmc_core.h | 14 +-
> 4 files changed, 174 insertions(+), 89 deletions(-)
--
With Best Regards,
Andy Shevchenko
On Fri, Jan 26, 2018 at 10:48 AM, Andy Shevchenko
<[email protected]> wrote:
> On Fri, Jan 19, 2018 at 10:58 AM, Rajneesh Bhardwaj
> <[email protected]> wrote:
>> From: Srinivas Pandruvada <[email protected]>
>>
>> Export lpit_read_residency_count_address(), so that it can be used from
>> drivers built as module. With the recent changes, the builtin_pci
>> functionality of the intel_pmc_core driver is removed and now it can be
>> built as a module to read this exported interface to calculate the PMC base
>> address.
>>
>
> This needs Ack from ACPI maintainer(s).
>
> Rafael, are you OK with exporting this method?
I have no particular objection at this point.
On Mon, Jan 29, 2018 at 5:09 AM, Rafael J. Wysocki <[email protected]> wrote:
> On Fri, Jan 26, 2018 at 10:48 AM, Andy Shevchenko
> <[email protected]> wrote:
>> On Fri, Jan 19, 2018 at 10:58 AM, Rajneesh Bhardwaj
>> <[email protected]> wrote:
>>> From: Srinivas Pandruvada <[email protected]>
>>>
>>> Export lpit_read_residency_count_address(), so that it can be used from
>>> drivers built as module. With the recent changes, the builtin_pci
>>> functionality of the intel_pmc_core driver is removed and now it can be
>>> built as a module to read this exported interface to calculate the PMC base
>>> address.
>>>
>>
>> This needs Ack from ACPI maintainer(s).
>>
>> Rafael, are you OK with exporting this method?
>
> I have no particular objection at this point.
I took it as an ACK.
Tell me if I'm wrong.
--
With Best Regards,
Andy Shevchenko
On Wed, 31 Jan 2018, Rajneesh Bhardwaj wrote:
> On Fri, Jan 26, 2018 at 02:39:47PM +0200, Andy Shevchenko wrote:
> > On Fri, Jan 19, 2018 at 10:58 AM, Rajneesh Bhardwaj
> > <[email protected]> wrote:
> > > Add CPUID of Cannonlake (CNL) processors to Intel family list.
> > >
> > > Cc: Dave Hansen <[email protected]>
> > > Cc: Thomas Gleixner <[email protected]>
> > > cc: Ingo Molnar <[email protected]>
> > > Cc: "H. Peter Anvin" <[email protected]>
> > > Cc: [email protected]
> >
> > Thomas, can you Ack this patch?
>
> Sorry to bug you again, MAINTAINERS. The series depends on this patch for
> enabling Cannonlake support. Requesting your ACK / Feedback for this one.
Reviewed-by: Thomas Gleixner <[email protected]>
On Fri, Jan 26, 2018 at 02:39:47PM +0200, Andy Shevchenko wrote:
> On Fri, Jan 19, 2018 at 10:58 AM, Rajneesh Bhardwaj
> <[email protected]> wrote:
> > Add CPUID of Cannonlake (CNL) processors to Intel family list.
> >
> > Cc: Dave Hansen <[email protected]>
> > Cc: Thomas Gleixner <[email protected]>
> > cc: Ingo Molnar <[email protected]>
> > Cc: "H. Peter Anvin" <[email protected]>
> > Cc: [email protected]
>
> Thomas, can you Ack this patch?
Sorry to bug you again, MAINTAINERS. The series depends on this patch for
enabling Cannonlake support. Requesting your ACK / Feedback for this one.
Thank you.
>
> > Suggested-by: Tony Luck <[email protected]>
> > Signed-off-by: Megha Dey <[email protected]>
> > Signed-off-by: Rajneesh Bhardwaj <[email protected]>
> > ---
> > arch/x86/include/asm/intel-family.h | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
> > index 35a6bc4da8ad..cf090e584202 100644
> > --- a/arch/x86/include/asm/intel-family.h
> > +++ b/arch/x86/include/asm/intel-family.h
> > @@ -10,6 +10,10 @@
> > *
> > * Things ending in "2" are usually because we have no better
> > * name for them. There's no processor called "SILVERMONT2".
> > + *
> > + * While adding a new CPUID for a new microarchitecture, add a new
> > + * group to keep logically sorted out in chronological order. Within
> > + * that group keep the CPUID for the variants sorted by model number.
> > */
> >
> > #define INTEL_FAM6_CORE_YONAH 0x0E
> > @@ -49,6 +53,8 @@
> > #define INTEL_FAM6_KABYLAKE_MOBILE 0x8E
> > #define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E
> >
> > +#define INTEL_FAM6_CANNONLAKE_MOBILE 0x66
> > +
> > /* "Small Core" Processors (Atom) */
> >
> > #define INTEL_FAM6_ATOM_PINEVIEW 0x1C
> > --
> > 2.7.4
> >
>
> --
> With Best Regards,
> Andy Shevchenko
--
Best Regards,
Rajneesh
On Wed, Jan 31, 2018 at 7:44 PM, Thomas Gleixner <[email protected]> wrote:
> Reviewed-by: Thomas Gleixner <[email protected]>
Thank you, Thomas!
Rajneesh, please, rebase the not-yet-applied patches on top of my
testing branch, add tags (Rafael's and Thomas') and resend.
--
With Best Regards,
Andy Shevchenko