From the SD host controller version 4.0 on, SDHCI implementation either
is version 3 compatible or version 4 mode. This patch-set covers those
changes which are common for SDHCI 4.0 version, regardless of whether
they are used with SD or eMMC storage devices.
Chunyan Zhang (3):
mmc: sdhci: add sd host v4 mode
mmc: sdhci: made changes for System Address register of SDMA
mmc: sdhci: add ADMA2 64-bit addressing support for V4 mode
drivers/mmc/host/sdhci.c | 66 +++++++++++++++++++++++++++++++++++++-----------
drivers/mmc/host/sdhci.h | 29 +++++++++++++++++----
2 files changed, 75 insertions(+), 20 deletions(-)
--
2.7.4
For SD host controller version 4.00 or later ones, there're two
modes of implementation - Version 3.00 compatible mode or
Version 4 mode. This patch introduces a flag to record this.
Signed-off-by: Chunyan Zhang <[email protected]>
---
drivers/mmc/host/sdhci.c | 6 ++++++
drivers/mmc/host/sdhci.h | 6 ++++++
2 files changed, 12 insertions(+)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 2020e57..da4d91e 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -3289,6 +3289,12 @@ void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
+ if (host->version >= SDHCI_SPEC_400) {
+ if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
+ SDHCI_CTRL_V4_MODE)
+ host->v4_mode = true;
+ }
+
if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
return;
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index c95b0a4..128b0ba 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -184,6 +184,7 @@
#define SDHCI_CTRL_DRV_TYPE_D 0x0030
#define SDHCI_CTRL_EXEC_TUNING 0x0040
#define SDHCI_CTRL_TUNED_CLK 0x0080
+#define SDHCI_CTRL_V4_MODE 0x1000
#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
#define SDHCI_CAPABILITIES 0x40
@@ -270,6 +271,8 @@
#define SDHCI_SPEC_100 0
#define SDHCI_SPEC_200 1
#define SDHCI_SPEC_300 2
+#define SDHCI_SPEC_400 3
+#define SDHCI_SPEC_410 4
/*
* End of controller registers.
@@ -551,6 +554,9 @@ struct sdhci_host {
u32 sdma_boundary;
unsigned long private[0] ____cacheline_aligned;
+
+ /* Host Version 4 Enable */
+ bool v4_mode;
};
struct sdhci_ops {
--
2.7.4
ADMA2 64-bit addressing support is divided into V3 mode and V4 mode.
There are two kinds of descriptors for ADMA2 64-bit addressing
i.e. 96-bit Descriptor for V3 mode, and 128-bit Descriptor for V4
mode. 128-bit Descriptor is aligned to 8-byte.
For V4 mode, ADMA2 64-bit addressing is enabled via Host Control 2
register.
Signed-off-by: Chunyan Zhang <[email protected]>
---
drivers/mmc/host/sdhci.c | 50 +++++++++++++++++++++++++++++++++++-------------
drivers/mmc/host/sdhci.h | 23 +++++++++++++++++-----
2 files changed, 55 insertions(+), 18 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 748a3a3..137905c 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -585,6 +585,8 @@ static void sdhci_adma_table_pre(struct sdhci_host *host,
void *desc, *align;
char *buffer;
int len, offset, i;
+ unsigned int adma2_align = SDHCI_ADMA2_ALIGN(host);
+ unsigned int adma2_mask = SDHCI_ADMA2_MASK(host);
/*
* The spec does not specify endianness of descriptor table.
@@ -608,8 +610,8 @@ static void sdhci_adma_table_pre(struct sdhci_host *host,
* buffer for the (up to three) bytes that screw up the
* alignment.
*/
- offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
- SDHCI_ADMA2_MASK;
+ offset = (adma2_align - (addr & adma2_align)) &
+ adma2_mask;
if (offset) {
if (data->flags & MMC_DATA_WRITE) {
buffer = sdhci_kmap_atomic(sg, &flags);
@@ -623,8 +625,8 @@ static void sdhci_adma_table_pre(struct sdhci_host *host,
BUG_ON(offset > 65536);
- align += SDHCI_ADMA2_ALIGN;
- align_addr += SDHCI_ADMA2_ALIGN;
+ align += adma2_align;
+ align_addr += adma2_align;
desc += host->desc_sz;
@@ -668,13 +670,15 @@ static void sdhci_adma_table_post(struct sdhci_host *host,
void *align;
char *buffer;
unsigned long flags;
+ unsigned int adma2_align = SDHCI_ADMA2_ALIGN(host);
+ unsigned int adma2_mask = SDHCI_ADMA2_MASK(host);
if (data->flags & MMC_DATA_READ) {
bool has_unaligned = false;
/* Do a quick scan of the SG list for any unaligned mappings */
for_each_sg(data->sg, sg, host->sg_count, i)
- if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
+ if (sg_dma_address(sg) & adma2_mask) {
has_unaligned = true;
break;
}
@@ -686,15 +690,15 @@ static void sdhci_adma_table_post(struct sdhci_host *host,
align = host->align_buffer;
for_each_sg(data->sg, sg, host->sg_count, i) {
- if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
- size = SDHCI_ADMA2_ALIGN -
- (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
+ if (sg_dma_address(sg) & adma2_mask) {
+ size = adma2_align -
+ (sg_dma_address(sg) & adma2_mask);
buffer = sdhci_kmap_atomic(sg, &flags);
memcpy(buffer, align, size);
sdhci_kunmap_atomic(buffer, &flags);
- align += SDHCI_ADMA2_ALIGN;
+ align += adma2_align;
}
}
}
@@ -3387,6 +3391,26 @@ static int sdhci_allocate_bounce_buffer(struct sdhci_host *host)
return 0;
}
+static inline bool sdhci_use_64bit_dma(struct sdhci_host *host)
+{
+ u32 addr64bit_en;
+
+ /*
+ * According to SD Host Controller spec v4.10, bit[27] added from
+ * version 4.10 in Capabilities Register is used as 64-bit System
+ * Address support for V4 mode, 64-bit DMA Addressing for V4 mode
+ * is enabled only if 64-bit Addressing =1 in the Host Control 2
+ * register.
+ */
+ if (host->version == SDHCI_SPEC_410 && host->v4_mode) {
+ addr64bit_en = (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
+ SDHCI_CTRL_64BIT_ADDR);
+ return addr64bit_en && (host->caps & SDHCI_CAN_64BIT_V4);
+ }
+
+ return host->caps & SDHCI_CAN_64BIT;
+}
+
int sdhci_setup_host(struct sdhci_host *host)
{
struct mmc_host *mmc;
@@ -3458,7 +3482,7 @@ int sdhci_setup_host(struct sdhci_host *host)
* SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
* implement.
*/
- if (host->caps & SDHCI_CAN_64BIT)
+ if (sdhci_use_64bit_dma(host))
host->flags |= SDHCI_USE_64_BIT_DMA;
if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
@@ -3492,15 +3516,15 @@ int sdhci_setup_host(struct sdhci_host *host)
*/
if (host->flags & SDHCI_USE_64_BIT_DMA) {
host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
- SDHCI_ADMA2_64_DESC_SZ;
- host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
+ SDHCI_ADMA2_64_DESC_SZ(host);
+ host->desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
} else {
host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
SDHCI_ADMA2_32_DESC_SZ;
host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
}
- host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
+ host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN(host);
buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
host->adma_table_sz, &dma, GFP_KERNEL);
if (!buf) {
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 128b0ba..820a863 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -185,6 +185,7 @@
#define SDHCI_CTRL_EXEC_TUNING 0x0040
#define SDHCI_CTRL_TUNED_CLK 0x0080
#define SDHCI_CTRL_V4_MODE 0x1000
+#define SDHCI_CTRL_64BIT_ADDR 0x2000
#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
#define SDHCI_CAPABILITIES 0x40
@@ -206,6 +207,7 @@
#define SDHCI_CAN_VDD_300 0x02000000
#define SDHCI_CAN_VDD_180 0x04000000
#define SDHCI_CAN_64BIT 0x10000000
+#define SDHCI_CAN_64BIT_V4 0x8000000
#define SDHCI_SUPPORT_SDR50 0x00000001
#define SDHCI_SUPPORT_SDR104 0x00000002
@@ -297,9 +299,14 @@ struct sdhci_adma2_32_desc {
__le32 addr;
} __packed __aligned(4);
-/* ADMA2 data alignment */
-#define SDHCI_ADMA2_ALIGN 4
-#define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1)
+/*
+ * ADMA2 data alignment
+ * According to SD Host Controller spec v4.10, if Host Version 4 Enable is set
+ * in the Host Control 2 register, 128-bit Descriptor will be selected which
+ * shall be aligned 8-byte address boundary.
+ */
+#define SDHCI_ADMA2_ALIGN(host) ((host)->v4_mode ? 8 : 4)
+#define SDHCI_ADMA2_MASK(host) (SDHCI_ADMA2_ALIGN(host) - 1)
/*
* ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte
@@ -308,8 +315,14 @@ struct sdhci_adma2_32_desc {
*/
#define SDHCI_ADMA2_DESC_ALIGN 8
-/* ADMA2 64-bit DMA descriptor size */
-#define SDHCI_ADMA2_64_DESC_SZ 12
+/*
+ * ADMA2 64-bit DMA descriptor size
+ * According to SD Host Controller spec v4.10, there are two kinds of
+ * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit
+ * Descriptor, if Host Version 4 Enable is set in the Host Control 2
+ * register, 128-bit Descriptor will be selected.
+ */
+#define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12)
/*
* ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
--
2.7.4
According to the SD host controller specification version 4.10, when
Host Version 4 is enabled, SDMA uses ADMA System Address register
(05Fh-058h) instead of using SDMA System Address register to
support both 32-bit and 64-bit addressing.
Signed-off-by: Chunyan Zhang <[email protected]>
---
drivers/mmc/host/sdhci.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index da4d91e..748a3a3 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -805,6 +805,7 @@ static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
{
u8 ctrl;
+ u32 reg;
struct mmc_data *data = cmd->data;
if (sdhci_data_line_cmd(cmd))
@@ -894,8 +895,10 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
SDHCI_ADMA_ADDRESS_HI);
} else {
WARN_ON(sg_cnt != 1);
+ reg = host->v4_mode ? SDHCI_ADMA_ADDRESS :
+ SDHCI_DMA_ADDRESS;
sdhci_writel(host, sdhci_sdma_address(host),
- SDHCI_DMA_ADDRESS);
+ reg);
}
}
@@ -2721,6 +2724,7 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
*/
if (intmask & SDHCI_INT_DMA_END) {
u32 dmastart, dmanow;
+ u32 reg;
dmastart = sdhci_sdma_address(host);
dmanow = dmastart + host->data->bytes_xfered;
@@ -2733,7 +2737,9 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
host->data->bytes_xfered = dmanow - dmastart;
DBG("DMA base 0x%08x, transferred 0x%06x bytes, next 0x%08x\n",
dmastart, host->data->bytes_xfered, dmanow);
- sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
+ reg = host->v4_mode ? SDHCI_ADMA_ADDRESS :
+ SDHCI_DMA_ADDRESS;
+ sdhci_writel(host, dmanow, reg);
}
if (intmask & SDHCI_INT_DATA_END) {
--
2.7.4
On 20/03/18 10:36, Chunyan Zhang wrote:
>>From the SD host controller version 4.0 on, SDHCI implementation either
> is version 3 compatible or version 4 mode. This patch-set covers those
> changes which are common for SDHCI 4.0 version, regardless of whether
> they are used with SD or eMMC storage devices.
Why use v4 mode?
What driver is using v4 mode? Can you also post those changes?
Are you planning on adding UHS-II support also?
>
> Chunyan Zhang (3):
> mmc: sdhci: add sd host v4 mode
> mmc: sdhci: made changes for System Address register of SDMA
> mmc: sdhci: add ADMA2 64-bit addressing support for V4 mode
>
> drivers/mmc/host/sdhci.c | 66 +++++++++++++++++++++++++++++++++++++-----------
> drivers/mmc/host/sdhci.h | 29 +++++++++++++++++----
> 2 files changed, 75 insertions(+), 20 deletions(-)
>
Hi Adrian,
On 20 March 2018 at 17:18, Adrian Hunter <[email protected]> wrote:
> On 20/03/18 10:36, Chunyan Zhang wrote:
>>>From the SD host controller version 4.0 on, SDHCI implementation either
>> is version 3 compatible or version 4 mode. This patch-set covers those
>> changes which are common for SDHCI 4.0 version, regardless of whether
>> they are used with SD or eMMC storage devices.
>
> Why use v4 mode?
>
> What driver is using v4 mode? Can you also post those changes?
I believe there must be some out-of-tree driver using v4 mode, at
least Spreadtrum's sd host controller is, as I know, and they're
planning on upstreaming that driver.
Those changes which this patch-set covers are just in the subject of
each patch in this series :)
>
> Are you planning on adding UHS-II support also?
Yes, that's my preliminary plan.
BTW, this patchset should have prefix "RFC", I just forgot to add that.
Thanks for your comments,
Chunyan
>
>>
>> Chunyan Zhang (3):
>> mmc: sdhci: add sd host v4 mode
>> mmc: sdhci: made changes for System Address register of SDMA
>> mmc: sdhci: add ADMA2 64-bit addressing support for V4 mode
>>
>> drivers/mmc/host/sdhci.c | 66 +++++++++++++++++++++++++++++++++++++-----------
>> drivers/mmc/host/sdhci.h | 29 +++++++++++++++++----
>> 2 files changed, 75 insertions(+), 20 deletions(-)
>>
>
Hi Ulf,
Do you have some comments on this patch-set?
Thanks,
Chunyan
On 20 March 2018 at 16:36, Chunyan Zhang <[email protected]> wrote:
> From the SD host controller version 4.0 on, SDHCI implementation either
> is version 3 compatible or version 4 mode. This patch-set covers those
> changes which are common for SDHCI 4.0 version, regardless of whether
> they are used with SD or eMMC storage devices.
>
> Chunyan Zhang (3):
> mmc: sdhci: add sd host v4 mode
> mmc: sdhci: made changes for System Address register of SDMA
> mmc: sdhci: add ADMA2 64-bit addressing support for V4 mode
>
> drivers/mmc/host/sdhci.c | 66 +++++++++++++++++++++++++++++++++++++-----------
> drivers/mmc/host/sdhci.h | 29 +++++++++++++++++----
> 2 files changed, 75 insertions(+), 20 deletions(-)
>
> --
> 2.7.4
>
On 4 April 2018 at 11:05, Chunyan Zhang <[email protected]> wrote:
> Hi Ulf,
>
> Do you have some comments on this patch-set?
No objections from my side of the series, however I am relying on
Adrian's ack before I pick any of the patches.
Kind regards
Uffe
>
> Thanks,
> Chunyan
>
> On 20 March 2018 at 16:36, Chunyan Zhang <[email protected]> wrote:
>> From the SD host controller version 4.0 on, SDHCI implementation either
>> is version 3 compatible or version 4 mode. This patch-set covers those
>> changes which are common for SDHCI 4.0 version, regardless of whether
>> they are used with SD or eMMC storage devices.
>>
>> Chunyan Zhang (3):
>> mmc: sdhci: add sd host v4 mode
>> mmc: sdhci: made changes for System Address register of SDMA
>> mmc: sdhci: add ADMA2 64-bit addressing support for V4 mode
>>
>> drivers/mmc/host/sdhci.c | 66 +++++++++++++++++++++++++++++++++++++-----------
>> drivers/mmc/host/sdhci.h | 29 +++++++++++++++++----
>> 2 files changed, 75 insertions(+), 20 deletions(-)
>>
>> --
>> 2.7.4
>>
On 04/04/18 13:17, Ulf Hansson wrote:
> On 4 April 2018 at 11:05, Chunyan Zhang <[email protected]> wrote:
>> Hi Ulf,
>>
>> Do you have some comments on this patch-set?
>
> No objections from my side of the series, however I am relying on
> Adrian's ack before I pick any of the patches.
We don't have any drivers that enable v4 mode. Really we need that, so that
we are supporting features that are actually in use. Equally some evidence
of testing would be expected.
>
> Kind regards
> Uffe
>
>>
>> Thanks,
>> Chunyan
>>
>> On 20 March 2018 at 16:36, Chunyan Zhang <[email protected]> wrote:
>>> From the SD host controller version 4.0 on, SDHCI implementation either
>>> is version 3 compatible or version 4 mode. This patch-set covers those
>>> changes which are common for SDHCI 4.0 version, regardless of whether
>>> they are used with SD or eMMC storage devices.
>>>
>>> Chunyan Zhang (3):
>>> mmc: sdhci: add sd host v4 mode
>>> mmc: sdhci: made changes for System Address register of SDMA
>>> mmc: sdhci: add ADMA2 64-bit addressing support for V4 mode
>>>
>>> drivers/mmc/host/sdhci.c | 66 +++++++++++++++++++++++++++++++++++++-----------
>>> drivers/mmc/host/sdhci.h | 29 +++++++++++++++++----
>>> 2 files changed, 75 insertions(+), 20 deletions(-)
>>>
>>> --
>>> 2.7.4
>>>
>
On 4 April 2018 at 13:43, Adrian Hunter <[email protected]> wrote:
> On 04/04/18 13:17, Ulf Hansson wrote:
>> On 4 April 2018 at 11:05, Chunyan Zhang <[email protected]> wrote:
>>> Hi Ulf,
>>>
>>> Do you have some comments on this patch-set?
>>
>> No objections from my side of the series, however I am relying on
>> Adrian's ack before I pick any of the patches.
>
> We don't have any drivers that enable v4 mode. Really we need that, so that
> we are supporting features that are actually in use. Equally some evidence
> of testing would be expected.
Right, this makes perfect sense to me as well!
Kind regards
Uffe