This patch set include modifications to the NPCM7xx
device tree according latest sent modules patches:
1. add watchdog device to NPCM750 device tree
- https://patchwork.kernel.org/patch/10269679/
2. modify UART compatible name in NPCM750 device tree
- https://patchwork.kernel.org/patch/10220251/
3. modify timer register size in NPCM750 device tree
- https://patchwork.ozlabs.org/patch/883180/
4. modify clock binding in NPCM750 device tree
- https://patchwork.kernel.org/patch/10307601/
5. modify Makefile NPCM750 configuration name
- https://patchwork.kernel.org/patch/10285929/
6. modify Nuvoton NPCM7xx device tree structure
The NPCM7xx are a family of BMC's that include several chips as:
NPCM750, NPCM730 etc.
All of the NPCM7xx BMC's have the common modules like Cortex-A9,
WDT, timers, etc, and there are a optional modules that can be added.
NPCM750 device tree already pushed to arm-soc.git:
https://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git/commit/?h=for-next&id=d6bdd009c21db3f677dd1d1bbb8c20bc819074bc
After discussion with Rob Herring we have modified the structure
of the NPCM7xx device tree as follow:
nuvoton-common-npcm7xx device tree include all common modules
nuvoton-npcm750 device tree include specific npcm750 modules,
the nuvoton-npcm750 device tree include nuvoton-common-npcm7xx device tree
I will like to replace the device tree that pushed to arm-soc.git with
this patch set.
Please review it, sorry if it cause more work after pushing
NPCM750 device tree.
Thanks a lot,
Tomer
Tomer Maimon (6):
arm: dts: add watchdog device to NPCM750 device tree
arm: dts: modify UART compatible name in NPCM750 device tree
arm: dts: modify timer register size in NPCM750 device tree
arm: dts: modify clock binding in NPCM750 device tree
arm: dts: modify Makefile NPCM750 configuration name
arm: dts: modify Nuvoton NPCM7xx device tree structure
arch/arm/boot/dts/Makefile | 2 +-
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 187 ++++++++++++++++++++++++++
arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 6 +-
arch/arm/boot/dts/nuvoton-npcm750.dtsi | 131 +-----------------
4 files changed, 198 insertions(+), 128 deletions(-)
create mode 100644 arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
--
2.14.1
Modify clock binding in a common device tree for all Nuvoton
NPCM750 BMCs.
Modify NPCM750 modules clock numbers accourding the new
clock driver.
Signed-off-by: Tomer Maimon <[email protected]>
---
arch/arm/boot/dts/nuvoton-npcm750.dtsi | 58 ++++++++++++++++++++++++++--------
1 file changed, 44 insertions(+), 14 deletions(-)
diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
index c7d80d2152ae..d53eccfe44cb 100644
--- a/arch/arm/boot/dts/nuvoton-npcm750.dtsi
+++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
@@ -17,7 +17,7 @@
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
- clocks = <&clk 10>;
+ clocks = <&clk 0>;
clock-names = "clk_cpu";
reg = <0>;
next-level-cache = <&l2>;
@@ -26,31 +26,58 @@
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
- clocks = <&clk 10>;
+ clocks = <&clk 0>;
clock-names = "clk_cpu";
reg = <1>;
next-level-cache = <&l2>;
};
};
- /* external clock signal rg1refck, supplied by the phy */
- clk-rg1refck {
+ /* external reference clock */
+ clk-refclk: clk-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ clock-output-names = "refclk";
+ };
+
+ /* external reference clock for cpu. float in normal operation */
+ clk-sysbypck: clk-sysbypck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <800000000>;
+ clock-output-names = "sysbypck";
+ };
+
+ /* external reference clock for MC. float in normal operation */
+ clk-mcbypck: clk-mcbypck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <800000000>;
+ clock-output-names = "mcbypck";
+ };
+
+ /* external clock signal rg1refck, supplied by the phy */
+ clk-rg1refck: clk-rg1refck {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
+ clock-output-names = "clk-rg1refck";
};
/* external clock signal rg2refck, supplied by the phy */
- clk-rg2refck {
+ clk-rg2refck: clk-rg2refck {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
+ clock-output-names = "clk-rg2refck";
};
- clk-xin {
+ clk-xin: clk-xin {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
+ clock-output-names = "clk-xin";
};
soc {
@@ -77,7 +104,7 @@
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-level = <2>;
- clocks = <&clk 22>;
+ clocks = <&clk 10>;
arm,shared-override;
};
@@ -94,7 +121,7 @@
reg = <0x3fe600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&clk 15>;
+ clocks = <&clk 5>;
};
};
@@ -106,9 +133,12 @@
ranges;
clk: clock-controller@f0801000 {
- compatible = "nuvoton,npcm750-clk";
+ compatible = "nuvoton,npcm750-clk", "syscon";
#clock-cells = <1>;
+ clock-controller;
reg = <0xf0801000 0x1000>;
+ clock-names = "refclk", "sysbypck", "mcbypck";
+ clocks = <&clk-refclk>, <&clk-sysbypck>, <&clk-mcbypck>;
};
apb {
@@ -122,7 +152,7 @@
compatible = "nuvoton,npcm750-timer";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x8000 0x50>;
- clocks = <&clk 15>;
+ clocks = <&clk 5>;
};
watchdog0: watchdog@801C {
@@ -152,7 +182,7 @@
serial0: serial@1000 {
compatible = "nuvoton,npcm750-uart";
reg = <0x1000 0x1000>;
- clocks = <&clk 14>;
+ clocks = <&clk 6>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
status = "disabled";
@@ -161,7 +191,7 @@
serial1: serial@2000 {
compatible = "nuvoton,npcm750-uart";
reg = <0x2000 0x1000>;
- clocks = <&clk 14>;
+ clocks = <&clk 6>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
status = "disabled";
@@ -170,7 +200,7 @@
serial2: serial@3000 {
compatible = "nuvoton,npcm750-uart";
reg = <0x3000 0x1000>;
- clocks = <&clk 14>;
+ clocks = <&clk 6>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
status = "disabled";
@@ -179,7 +209,7 @@
serial3: serial@4000 {
compatible = "nuvoton,npcm750-uart";
reg = <0x4000 0x1000>;
- clocks = <&clk 14>;
+ clocks = <&clk 6>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
status = "disabled";
--
2.14.1
Modify timer register size in a common device tree for all Nuvoton
NPCM750 BMCs.
Signed-off-by: Tomer Maimon <[email protected]>
---
arch/arm/boot/dts/nuvoton-npcm750.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
index 286f139fdc7c..c7d80d2152ae 100644
--- a/arch/arm/boot/dts/nuvoton-npcm750.dtsi
+++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
@@ -121,7 +121,7 @@
timer0: timer@8000 {
compatible = "nuvoton,npcm750-timer";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x8000 0x1000>;
+ reg = <0x8000 0x50>;
clocks = <&clk 15>;
};
--
2.14.1
Add watchdog device node to a common device tree for all Nuvoton
NPCM750 BMCs and a board specific device tree for the NPCM750 (Poleg)
evaluation board.
Signed-off-by: Tomer Maimon <[email protected]>
---
arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 4 ++++
arch/arm/boot/dts/nuvoton-npcm750.dtsi | 24 ++++++++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
index cabde3d5be8a..4416dd6c7c17 100644
--- a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
+++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
@@ -18,6 +18,10 @@
};
};
+&watchdog1 {
+ status = "okay";
+};
+
&serial0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
index 839e45cfd695..cacd0fde5914 100644
--- a/arch/arm/boot/dts/nuvoton-npcm750.dtsi
+++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
@@ -125,6 +125,30 @@
clocks = <&clk 15>;
};
+ watchdog0: watchdog@801C {
+ compatible = "nuvoton,npcm750-wdt";
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x801C 0x4>;
+ status = "disabled";
+ clocks = <&clk 5>;
+ };
+
+ watchdog1: watchdog@901C {
+ compatible = "nuvoton,npcm750-wdt";
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x901C 0x4>;
+ status = "disabled";
+ clocks = <&clk 5>;
+ };
+
+ watchdog2: watchdog@a01C {
+ compatible = "nuvoton,npcm750-wdt";
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xa01C 0x4>;
+ status = "disabled";
+ clocks = <&clk 5>;
+ };
+
serial0: serial@1000 {
compatible = "ns16550a";
reg = <0x1000 0x1000>;
--
2.14.1
Modify UART compatible name in a common device tree for all Nuvoton
NPCM750 BMCs.
Signed-off-by: Tomer Maimon <[email protected]>
---
arch/arm/boot/dts/nuvoton-npcm750.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
index cacd0fde5914..286f139fdc7c 100644
--- a/arch/arm/boot/dts/nuvoton-npcm750.dtsi
+++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
@@ -150,7 +150,7 @@
};
serial0: serial@1000 {
- compatible = "ns16550a";
+ compatible = "nuvoton,npcm750-uart";
reg = <0x1000 0x1000>;
clocks = <&clk 14>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -159,7 +159,7 @@
};
serial1: serial@2000 {
- compatible = "ns16550a";
+ compatible = "nuvoton,npcm750-uart";
reg = <0x2000 0x1000>;
clocks = <&clk 14>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
@@ -168,7 +168,7 @@
};
serial2: serial@3000 {
- compatible = "ns16550a";
+ compatible = "nuvoton,npcm750-uart";
reg = <0x3000 0x1000>;
clocks = <&clk 14>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
@@ -177,7 +177,7 @@
};
serial3: serial@4000 {
- compatible = "ns16550a";
+ compatible = "nuvoton,npcm750-uart";
reg = <0x4000 0x1000>;
clocks = <&clk 14>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
--
2.14.1
Modify Nuvoton NPCM7xx device tree structure by adding
nuvoton common nNPCM7xx device tree structure that
include all common modules.
Signed-off-by: Tomer Maimon <[email protected]>
---
arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 187 ++++++++++++++++++++++++++
arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 2 +-
arch/arm/boot/dts/nuvoton-npcm750.dtsi | 179 +-----------------------
3 files changed, 190 insertions(+), 178 deletions(-)
create mode 100644 arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
new file mode 100644
index 000000000000..d2d0761295a4
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Nuvoton Technology [email protected]
+// Copyright 2018 Google, Inc.
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+
+ /* external reference clock */
+ clk_refclk: clk_refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ clock-output-names = "refclk";
+ };
+
+ /* external reference clock for cpu. float in normal operation */
+ clk_sysbypck: clk_sysbypck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <800000000>;
+ clock-output-names = "sysbypck";
+ };
+
+ /* external reference clock for MC. float in normal operation */
+ clk_mcbypck: clk_mcbypck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <800000000>;
+ clock-output-names = "mcbypck";
+ };
+
+ /* external clock signal rg1refck, supplied by the phy */
+ clk_rg1refck: clk_rg1refck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ clock-output-names = "clk_rg1refck";
+ };
+
+ /* external clock signal rg2refck, supplied by the phy */
+ clk_rg2refck: clk_rg2refck {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ clock-output-names = "clk_rg2refck";
+ };
+
+ clk_xin: clk_xin {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ clock-output-names = "clk_xin";
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges = <0x0 0xf0000000 0x00900000>;
+
+ gcr: gcr@800000 {
+ compatible = "nuvoton,npcm750-gcr", "syscon",
+ "simple-mfd";
+ reg = <0x800000 0x1000>;
+ };
+
+ scu: scu@3fe000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0x3fe000 0x1000>;
+ };
+
+ l2: cache-controller@3fc000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x3fc000 0x1000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ cache-unified;
+ cache-level = <2>;
+ clocks = <&clk 10>;
+ arm,shared-override;
+ };
+
+ gic: interrupt-controller@3ff000 {
+ compatible = "arm,cortex-a9-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x3ff000 0x1000>,
+ <0x3fe100 0x100>;
+ };
+ };
+
+ ahb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ clk: clock-controller@f0801000 {
+ compatible = "nuvoton,npcm750-clk", "syscon";
+ #clock-cells = <1>;
+ clock-controller;
+ reg = <0xf0801000 0x1000>;
+ clock-names = "refclk", "sysbypck", "mcbypck";
+ clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
+ };
+
+ apb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges = <0x0 0xf0000000 0x00300000>;
+
+ timer0: timer@8000 {
+ compatible = "nuvoton,npcm750-timer";
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x8000 0x50>;
+ clocks = <&clk 5>;
+ };
+
+ watchdog0: watchdog@801C {
+ compatible = "nuvoton,npcm750-wdt";
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x801C 0x4>;
+ status = "disabled";
+ clocks = <&clk 5>;
+ };
+
+ watchdog1: watchdog@901C {
+ compatible = "nuvoton,npcm750-wdt";
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x901C 0x4>;
+ status = "disabled";
+ clocks = <&clk 5>;
+ };
+
+ watchdog2: watchdog@a01C {
+ compatible = "nuvoton,npcm750-wdt";
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xa01C 0x4>;
+ status = "disabled";
+ clocks = <&clk 5>;
+ };
+
+ serial0: serial@1000 {
+ compatible = "nuvoton,npcm750-uart";
+ reg = <0x1000 0x1000>;
+ clocks = <&clk 6>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ serial1: serial@2000 {
+ compatible = "nuvoton,npcm750-uart";
+ reg = <0x2000 0x1000>;
+ clocks = <&clk 6>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ serial2: serial@3000 {
+ compatible = "nuvoton,npcm750-uart";
+ reg = <0x3000 0x1000>;
+ clocks = <&clk 6>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ serial3: serial@4000 {
+ compatible = "nuvoton,npcm750-uart";
+ reg = <0x4000 0x1000>;
+ clocks = <&clk 6>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
index 4416dd6c7c17..15f744f1beea 100644
--- a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
+++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
-// Copyright (c) 2018 Nuvoton Technology corporation.
+// Copyright (c) 2018 Nuvoton Technology [email protected]
// Copyright 2018 Google, Inc.
/dts-v1/;
diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
index d53eccfe44cb..6ac340533587 100644
--- a/arch/arm/boot/dts/nuvoton-npcm750.dtsi
+++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
-// Copyright (c) 2018 Nuvoton Technology corporation.
+// Copyright (c) 2018 Nuvoton Technology [email protected]
// Copyright 2018 Google, Inc.
-#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "nuvoton-common-npcm7xx.dtsi"
/ {
#address-cells = <1>;
@@ -32,90 +32,7 @@
next-level-cache = <&l2>;
};
};
-
- /* external reference clock */
- clk-refclk: clk-refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- clock-output-names = "refclk";
- };
-
- /* external reference clock for cpu. float in normal operation */
- clk-sysbypck: clk-sysbypck {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <800000000>;
- clock-output-names = "sysbypck";
- };
-
- /* external reference clock for MC. float in normal operation */
- clk-mcbypck: clk-mcbypck {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <800000000>;
- clock-output-names = "mcbypck";
- };
-
- /* external clock signal rg1refck, supplied by the phy */
- clk-rg1refck: clk-rg1refck {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <125000000>;
- clock-output-names = "clk-rg1refck";
- };
-
- /* external clock signal rg2refck, supplied by the phy */
- clk-rg2refck: clk-rg2refck {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <125000000>;
- clock-output-names = "clk-rg2refck";
- };
-
- clk-xin: clk-xin {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <50000000>;
- clock-output-names = "clk-xin";
- };
-
soc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- ranges = <0x0 0xf0000000 0x00900000>;
-
- gcr: gcr@800000 {
- compatible = "nuvoton,npcm750-gcr", "syscon",
- "simple-mfd";
- reg = <0x800000 0x1000>;
- };
-
- scu: scu@3fe000 {
- compatible = "arm,cortex-a9-scu";
- reg = <0x3fe000 0x1000>;
- };
-
- l2: cache-controller@3fc000 {
- compatible = "arm,pl310-cache";
- reg = <0x3fc000 0x1000>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- cache-unified;
- cache-level = <2>;
- clocks = <&clk 10>;
- arm,shared-override;
- };
-
- gic: interrupt-controller@3ff000 {
- compatible = "arm,cortex-a9-gic";
- interrupt-controller;
- #interrupt-cells = <3>;
- reg = <0x3ff000 0x1000>,
- <0x3fe100 0x100>;
- };
-
timer@3fe600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x3fe600 0x20>;
@@ -124,96 +41,4 @@
clocks = <&clk 5>;
};
};
-
- ahb {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- ranges;
-
- clk: clock-controller@f0801000 {
- compatible = "nuvoton,npcm750-clk", "syscon";
- #clock-cells = <1>;
- clock-controller;
- reg = <0xf0801000 0x1000>;
- clock-names = "refclk", "sysbypck", "mcbypck";
- clocks = <&clk-refclk>, <&clk-sysbypck>, <&clk-mcbypck>;
- };
-
- apb {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- ranges = <0x0 0xf0000000 0x00300000>;
-
- timer0: timer@8000 {
- compatible = "nuvoton,npcm750-timer";
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x8000 0x50>;
- clocks = <&clk 5>;
- };
-
- watchdog0: watchdog@801C {
- compatible = "nuvoton,npcm750-wdt";
- interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x801C 0x4>;
- status = "disabled";
- clocks = <&clk 5>;
- };
-
- watchdog1: watchdog@901C {
- compatible = "nuvoton,npcm750-wdt";
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x901C 0x4>;
- status = "disabled";
- clocks = <&clk 5>;
- };
-
- watchdog2: watchdog@a01C {
- compatible = "nuvoton,npcm750-wdt";
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0xa01C 0x4>;
- status = "disabled";
- clocks = <&clk 5>;
- };
-
- serial0: serial@1000 {
- compatible = "nuvoton,npcm750-uart";
- reg = <0x1000 0x1000>;
- clocks = <&clk 6>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- serial1: serial@2000 {
- compatible = "nuvoton,npcm750-uart";
- reg = <0x2000 0x1000>;
- clocks = <&clk 6>;
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- serial2: serial@3000 {
- compatible = "nuvoton,npcm750-uart";
- reg = <0x3000 0x1000>;
- clocks = <&clk 6>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- status = "disabled";
- };
-
- serial3: serial@4000 {
- compatible = "nuvoton,npcm750-uart";
- reg = <0x4000 0x1000>;
- clocks = <&clk 6>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- status = "disabled";
- };
- };
- };
};
--
2.14.1
Signed-off-by: Tomer Maimon <[email protected]>
---
arch/arm/boot/dts/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8164c1294226..7e2424957809 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -307,7 +307,7 @@ dtb-$(CONFIG_ARCH_LPC18XX) += \
dtb-$(CONFIG_ARCH_LPC32XX) += \
lpc3250-ea3250.dtb \
lpc3250-phy3250.dtb
-dtb-$(CONFIG_ARCH_NPCM750) += \
+dtb-$(CONFIG_ARCH_NPCM7XX) += \
nuvoton-npcm750-evb.dtb
dtb-$(CONFIG_MACH_MESON6) += \
meson6-atv1200.dtb
--
2.14.1