2018-12-03 13:35:55

by Qii Wang (王琪)

Subject: [PATCH 0/5] add i2c support for mt7629 and mt8183

This series are based on 4.20-rc1 and provide five patches to support
mt7629 and mt8183 IC.

qii wang (5):
dt-bindings: i2c: Add Mediatek MT7629 i2c binding
i2c: mediatek: remove useless code and replace definitions
i2c: mediatek: Add offsets array for new i2c registers
dt-bindings: i2c: Add Mediatek MT8183 i2c binding
i2c: mediatek: Add i2c compatible for MediaTek MT8183

Documentation/devicetree/bindings/i2c/i2c-mtk.txt | 8 +-
drivers/i2c/busses/i2c-mt65xx.c | 299 ++++++++++++++++-----
2 files changed, 239 insertions(+), 68 deletions(-)

--
1.7.9.5

2018-12-03 13:34:56

by Qii Wang (王琪)

Subject: [PATCH 5/5] i2c: mediatek: Add i2c compatible for MediaTek MT8183

From: qii wang <[email protected]>

Add i2c compatible for MT8183. Compare to 2712 i2c controller, MT8183 has
different registers, offsets, clock, and multi-user function.

Signed-off-by: qii wang <[email protected]>
---
drivers/i2c/busses/i2c-mt65xx.c | 136 +++++++++++++++++++++++++++++++++++++--
1 file changed, 130 insertions(+), 6 deletions(-)

diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 428ac99..6b979ab 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -35,17 +35,23 @@
#include <linux/slab.h>

#define I2C_RS_TRANSFER (1 << 4)
+#define I2C_ARB_LOST (1 << 3)
#define I2C_HS_NACKERR (1 << 2)
#define I2C_ACKERR (1 << 1)
#define I2C_TRANSAC_COMP (1 << 0)
#define I2C_TRANSAC_START (1 << 0)
+#define I2C_RESUME_ARBIT (1 << 1)
#define I2C_RS_MUL_CNFG (1 << 15)
#define I2C_RS_MUL_TRIG (1 << 14)
+#define I2C_HS_TIME_EN (1 << 7)
#define I2C_DCM_DISABLE 0x0000
#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
#define I2C_IO_CONFIG_PUSH_PULL 0x0000
#define I2C_SOFT_RST 0x0001
#define I2C_FIFO_ADDR_CLR 0x0001
+#define I2C_FIFO_ADDR_CLRH 0x0002
+#define I2C_FIFO_ADDR_CLR_MCH 0x0004
+#define I2C_HFIFO_DATA 0x8208
#define I2C_DELAY_LEN 0x0002
#define I2C_ST_START_CON 0x8001
#define I2C_FS_START_CON 0x1800
@@ -76,6 +82,8 @@
#define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
#define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
#define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
+#define I2C_CONTROL_DMAACK_EN (0x1 << 8)
+#define I2C_CONTROL_ASYNC_MODE (0x1 << 9)
#define I2C_CONTROL_WRAPPER (0x1 << 0)

#define I2C_DRV_NAME "i2c-mt65xx"
@@ -130,6 +138,15 @@ enum I2C_REGS_OFFSET {
OFFSET_DEBUGCTRL,
OFFSET_TRANSFER_LEN_AUX,
OFFSET_CLOCK_DIV,
+ /* MT8183 only regs */
+ OFFSET_LTIMING,
+ OFFSET_DATA_TIMING,
+ OFFSET_MCU_INTR,
+ OFFSET_HW_TIMEOUT,
+ OFFSET_HFIFO_DATA,
+ OFFSET_HFIFO_STAT,
+ OFFSET_MULTI_DMA,
+ OFFSET_ROLLBACK,
};

static const u16 mt_i2c_regs_v1[] = {
@@ -159,6 +176,39 @@ enum I2C_REGS_OFFSET {
[OFFSET_CLOCK_DIV] = 0x70,
};

+static const u16 mt_i2c_regs_v2[] = {
+ [OFFSET_DATA_PORT] = 0x0,
+ [OFFSET_SLAVE_ADDR] = 0x4,
+ [OFFSET_INTR_MASK] = 0x8,
+ [OFFSET_INTR_STAT] = 0xc,
+ [OFFSET_CONTROL] = 0x10,
+ [OFFSET_TRANSFER_LEN] = 0x14,
+ [OFFSET_TRANSAC_LEN] = 0x18,
+ [OFFSET_DELAY_LEN] = 0x1c,
+ [OFFSET_TIMING] = 0x20,
+ [OFFSET_START] = 0x24,
+ [OFFSET_EXT_CONF] = 0x28,
+ [OFFSET_LTIMING] = 0x2c,
+ [OFFSET_HS] = 0x30,
+ [OFFSET_IO_CONFIG] = 0x34,
+ [OFFSET_FIFO_ADDR_CLR] = 0x38,
+ [OFFSET_DATA_TIMING] = 0x3c,
+ [OFFSET_MCU_INTR] = 0x40,
+ [OFFSET_TRANSFER_LEN_AUX] = 0x44,
+ [OFFSET_CLOCK_DIV] = 0x48,
+ [OFFSET_HW_TIMEOUT] = 0x4c,
+ [OFFSET_SOFTRESET] = 0x50,
+ [OFFSET_HFIFO_DATA] = 0x70,
+ [OFFSET_DEBUGSTAT] = 0xe0,
+ [OFFSET_DEBUGCTRL] = 0xe8,
+ [OFFSET_FIFO_STAT] = 0xf4,
+ [OFFSET_FIFO_THRESH] = 0xf8,
+ [OFFSET_HFIFO_STAT] = 0xfc,
+ [OFFSET_DCM_EN] = 0xf88,
+ [OFFSET_MULTI_DMA] = 0xf8c,
+ [OFFSET_ROLLBACK] = 0xf98,
+};
+
struct mtk_i2c_compatible {
const struct i2c_adapter_quirks *quirks;
const u16 *regs;
@@ -168,6 +218,7 @@ struct mtk_i2c_compatible {
unsigned char aux_len_reg: 1;
unsigned char support_33bits: 1;
unsigned char timing_adjust: 1;
+ unsigned char dma_sync: 1;
};

struct mtk_i2c {
@@ -181,8 +232,11 @@ struct mtk_i2c {
struct clk *clk_main; /* main clock for i2c bus */
struct clk *clk_dma; /* DMA clock for i2c via DMA */
struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */
+ struct clk *clk_arb; /* Arbitrator clock for i2c */
bool have_pmic; /* can use i2c pins from PMIC */
bool use_push_pull; /* IO config push-pull mode */
+ bool share_i3c; /* share i3c IP*/
+ u32 ch_offset; /* i2c multi-user channel offset */

u16 irq_stat; /* interrupt status */
unsigned int clk_src_div;
@@ -190,6 +244,7 @@ struct mtk_i2c {
enum mtk_trans_op op;
u16 timing_reg;
u16 high_speed_reg;
+ u16 ltiming_reg;
unsigned char auto_restart;
bool ignore_restart_irq;
const struct mtk_i2c_compatible *dev_comp;
@@ -216,6 +271,7 @@ struct mtk_i2c {
.aux_len_reg = 1,
.support_33bits = 1,
.timing_adjust = 1,
+ .dma_sync = 0,
};

static const struct mtk_i2c_compatible mt6577_compat = {
@@ -227,6 +283,7 @@ struct mtk_i2c {
.aux_len_reg = 0,
.support_33bits = 0,
.timing_adjust = 0,
+ .dma_sync = 0,
};

static const struct mtk_i2c_compatible mt6589_compat = {
@@ -238,6 +295,7 @@ struct mtk_i2c {
.aux_len_reg = 0,
.support_33bits = 0,
.timing_adjust = 0,
+ .dma_sync = 0,
};

static const struct mtk_i2c_compatible mt7622_compat = {
@@ -249,6 +307,7 @@ struct mtk_i2c {
.aux_len_reg = 1,
.support_33bits = 0,
.timing_adjust = 0,
+ .dma_sync = 0,
};

static const struct mtk_i2c_compatible mt8173_compat = {
@@ -259,6 +318,18 @@ struct mtk_i2c {
.aux_len_reg = 1,
.support_33bits = 1,
.timing_adjust = 0,
+ .dma_sync = 0,
+};
+
+static const struct mtk_i2c_compatible mt8183_compat = {
+ .regs = mt_i2c_regs_v2,
+ .pmic_i2c = 0,
+ .dcm = 0,
+ .auto_restart = 1,
+ .aux_len_reg = 1,
+ .support_33bits = 1,
+ .timing_adjust = 1,
+ .dma_sync = 1,
};

static const struct of_device_id mtk_i2c_of_match[] = {
@@ -267,19 +338,20 @@ struct mtk_i2c {
{ .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
{ .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
{ .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
+ { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
{}
};
MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);

static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg)
{
- return readw(i2c->base + i2c->dev_comp->regs[reg]);
+ return readw(i2c->base + i2c->ch_offset + i2c->dev_comp->regs[reg]);
}

static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val,
enum I2C_REGS_OFFSET reg)
{
- writew(val, i2c->base + i2c->dev_comp->regs[reg]);
+ writew(val, i2c->base + i2c->ch_offset + i2c->dev_comp->regs[reg]);
}

static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
@@ -299,8 +371,18 @@ static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
if (ret)
goto err_pmic;
}
+
+ if (i2c->clk_arb) {
+ ret = clk_prepare_enable(i2c->clk_arb);
+ if (ret)
+ goto err_arb;
+ }
+
return 0;

+err_arb:
+ if (i2c->have_pmic)
+ clk_disable_unprepare(i2c->clk_pmic);
err_pmic:
clk_disable_unprepare(i2c->clk_main);
err_main:
@@ -311,6 +393,9 @@ static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)

static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
{
+ if (i2c->clk_arb)
+ clk_disable_unprepare(i2c->clk_arb);
+
if (i2c->have_pmic)
clk_disable_unprepare(i2c->clk_pmic);

@@ -333,11 +418,23 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
if (i2c->dev_comp->dcm)
mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN);

- if (i2c->dev_comp->timing_adjust)
+ if (i2c->ch_offset)
+ writew(I2C_RESUME_ARBIT, i2c->base +
+ i2c->dev_comp->regs[OFFSET_START]);
+
+ if (i2c->dev_comp->timing_adjust && i2c->share_i3c) {
+ mtk_i2c_writew(i2c, (I2C_DEFAULT_CLK_DIV - 1) |
+ (I2C_DEFAULT_CLK_DIV - 1) << 8,
+ OFFSET_CLOCK_DIV);
+ i2c->high_speed_reg |= I2C_HS_TIME_EN;
+ } else {
mtk_i2c_writew(i2c, I2C_DEFAULT_CLK_DIV - 1, OFFSET_CLOCK_DIV);
+ }

mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING);
mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS);
+ if (i2c->dev_comp->regs == mt_i2c_regs_v2)
+ mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING);

/* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
if (i2c->have_pmic)
@@ -345,6 +442,9 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)

control_reg = I2C_CONTROL_ACKERR_DET_EN |
I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
+ if (i2c->dev_comp->dma_sync)
+ control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE;
+
mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN);

@@ -434,6 +534,8 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
unsigned int clk_src;
unsigned int step_cnt;
unsigned int sample_cnt;
+ unsigned int l_step_cnt;
+ unsigned int l_sample_cnt;
unsigned int target_speed;
int ret;

@@ -443,11 +545,11 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
if (target_speed > MAX_FS_MODE_SPEED) {
/* Set master code speed register */
ret = mtk_i2c_calculate_speed(i2c, clk_src, MAX_FS_MODE_SPEED,
- &step_cnt, &sample_cnt);
+ &l_step_cnt, &l_sample_cnt);
if (ret < 0)
return ret;

- i2c->timing_reg = (sample_cnt << 8) | step_cnt;
+ i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;

/* Set the high speed mode register */
ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
@@ -457,6 +559,8 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)

i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
(sample_cnt << 12) | (step_cnt << 8);
+ i2c->ltiming_reg = (l_sample_cnt << 6) | l_step_cnt |
+ (sample_cnt << 12) | (step_cnt << 9);
} else {
ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
&step_cnt, &sample_cnt);
@@ -467,6 +571,8 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)

/* Disable the high speed transaction */
i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
+
+ i2c->ltiming_reg = (sample_cnt << 6) | step_cnt;
}

return 0;
@@ -483,6 +589,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
u16 addr_reg;
u16 start_reg;
u16 control_reg;
+ u16 fifo_clr_reg;
u16 restart_flag = 0;
u32 reg_4g_mode;
u8 *dma_rd_buf = NULL;
@@ -521,7 +628,15 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
I2C_TRANSAC_COMP, OFFSET_INTR_STAT);

- mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR);
+ if (i2c->share_i3c)
+ fifo_clr_reg = I2C_FIFO_ADDR_CLR | I2C_FIFO_ADDR_CLRH;
+ if (i2c->ch_offset)
+ fifo_clr_reg = I2C_FIFO_ADDR_CLR | I2C_FIFO_ADDR_CLR_MCH;
+
+ mtk_i2c_writew(i2c, fifo_clr_reg, OFFSET_FIFO_ADDR_CLR);
+
+ if ((i2c->speed_hz > MAX_FS_MODE_SPEED) && i2c->share_i3c)
+ mtk_i2c_writew(i2c, I2C_HFIFO_DATA, OFFSET_HFIFO_DATA);

/* Enable interrupt */
mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
@@ -817,6 +932,11 @@ static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c)
if (i2c->clk_src_div == 0)
return -EINVAL;

+ ret = of_property_read_u32(np, "ch-offset", &i2c->ch_offset);
+ if (ret < 0)
+ i2c->ch_offset = 0;
+
+ i2c->share_i3c = of_property_read_bool(np, "mediatek,share-i3c");
i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
i2c->use_push_pull =
of_property_read_bool(np, "mediatek,use-push-pull");
@@ -884,6 +1004,10 @@ static int mtk_i2c_probe(struct platform_device *pdev)
return PTR_ERR(i2c->clk_dma);
}

+ i2c->clk_arb = devm_clk_get(&pdev->dev, "arb");
+ if (IS_ERR(i2c->clk_arb))
+ i2c->clk_arb = NULL;
+
clk = i2c->clk_main;
if (i2c->have_pmic) {
i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
--
1.7.9.5

2018-12-03 13:35:07

by Qii Wang (王琪)

Subject: [PATCH 1/5] dt-bindings: i2c: Add Mediatek MT7629 i2c binding

From: qii wang <[email protected]>

Add MT7629 i2c binding to i2c-mt2712.txt and there is no need to
modify i2c driver.

Signed-off-by: qii wang <[email protected]>
---
Documentation/devicetree/bindings/i2c/i2c-mtk.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt b/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
index e199695..7729e57 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
@@ -10,6 +10,7 @@ Required properties:
"mediatek,mt6589-i2c": for MediaTek MT6589
"mediatek,mt7622-i2c": for MediaTek MT7622
"mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
+ "mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek mt7629
"mediatek,mt8173-i2c": for MediaTek MT8173
- reg: physical base address of the controller and dma base, length of memory
mapped region.
--
1.7.9.5

2018-12-03 13:35:13

by Qii Wang (王琪)

Subject: [PATCH 2/5] i2c: mediatek: remove useless code and replace definitions

From: qii wang <[email protected]>

Completion_done is useless when we don't use its return value,
so we remove it. Different speeds have been defined by macros,
so we use macros definitions.

Signed-off-by: qii wang <[email protected]>
---
drivers/i2c/busses/i2c-mt65xx.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index a74ef76..660de1e 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -456,7 +456,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,

control_reg = readw(i2c->base + OFFSET_CONTROL) &
~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
- if ((i2c->speed_hz > 400000) || (left_num >= 1))
+ if ((i2c->speed_hz > MAX_FS_MODE_SPEED) || (left_num >= 1))
control_reg |= I2C_CONTROL_RS;

if (i2c->op == I2C_MASTER_WRRD)
@@ -465,7 +465,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
writew(control_reg, i2c->base + OFFSET_CONTROL);

/* set start condition */
- if (i2c->speed_hz <= 100000)
+ if (i2c->speed_hz <= I2C_DEFAULT_SPEED)
writew(I2C_ST_START_CON, i2c->base + OFFSET_EXT_CONF);
else
writew(I2C_FS_START_CON, i2c->base + OFFSET_EXT_CONF);
@@ -642,8 +642,6 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
return -ETIMEDOUT;
}

- completion_done(&i2c->msg_complete);
-
if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
mtk_i2c_init_hw(i2c);
--
1.7.9.5

2018-12-03 13:36:39

by Qii Wang (王琪)

Subject: [PATCH 4/5] dt-bindings: i2c: Add Mediatek MT8183 i2c binding

From: qii wang <[email protected]>

Add MT8183 i2c binding to binding file. Compare to 2712 i2c
controller, MT8183 has different registers, offsets, clock,
and multi-user function.

Signed-off-by: qii wang <[email protected]>
---
Documentation/devicetree/bindings/i2c/i2c-mtk.txt | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt b/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
index 7729e57..dfde624 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
@@ -12,14 +12,15 @@ Required properties:
"mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
"mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek mt7629
"mediatek,mt8173-i2c": for MediaTek MT8173
+ "mediatek,mt8183-i2c": for MediaTek MT8183
- reg: physical base address of the controller and dma base, length of memory
mapped region.
- interrupts: interrupt number to the cpu.
- clock-div: the fixed value for frequency divider of clock source in i2c
module. Each IC may be different.
- clocks: clock name from clock manager
- - clock-names: Must include "main" and "dma", if enable have-pmic need include
- "pmic" extra.
+ - clock-names: Must include "main" and "dma", "arb" is optional, if enable
+ have-pmic need include "pmic" extra.

Optional properties:
- clock-frequency: Frequency in Hz of the bus when transfer, the default value
@@ -27,6 +28,8 @@ Optional properties:
- mediatek,have-pmic: platform can control i2c form special pmic side.
Only mt6589 and mt8135 support this feature.
- mediatek,use-push-pull: IO config use push-pull mode.
+ - ch-offset: base reg offset for multi-user.
+ - mediatek,share-i3c: i3c controller can share i2c function.

Example:

--
1.7.9.5

2018-12-03 13:36:53

by Qii Wang (王琪)

Subject: [PATCH 3/5] i2c: mediatek: Add offsets array for new i2c registers

From: qii wang <[email protected]>

New i2c registers would have different offsets, so we use different
offsets array to distinguish different i2c registers version.

Signed-off-by: qii wang <[email protected]>
---
drivers/i2c/busses/i2c-mt65xx.c | 163 +++++++++++++++++++++++++--------------
1 file changed, 104 insertions(+), 59 deletions(-)

diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 660de1e..428ac99 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -106,34 +106,62 @@ enum mtk_trans_op {
};

enum I2C_REGS_OFFSET {
- OFFSET_DATA_PORT = 0x0,
- OFFSET_SLAVE_ADDR = 0x04,
- OFFSET_INTR_MASK = 0x08,
- OFFSET_INTR_STAT = 0x0c,
- OFFSET_CONTROL = 0x10,
- OFFSET_TRANSFER_LEN = 0x14,
- OFFSET_TRANSAC_LEN = 0x18,
- OFFSET_DELAY_LEN = 0x1c,
- OFFSET_TIMING = 0x20,
- OFFSET_START = 0x24,
- OFFSET_EXT_CONF = 0x28,
- OFFSET_FIFO_STAT = 0x30,
- OFFSET_FIFO_THRESH = 0x34,
- OFFSET_FIFO_ADDR_CLR = 0x38,
- OFFSET_IO_CONFIG = 0x40,
- OFFSET_RSV_DEBUG = 0x44,
- OFFSET_HS = 0x48,
- OFFSET_SOFTRESET = 0x50,
- OFFSET_DCM_EN = 0x54,
- OFFSET_PATH_DIR = 0x60,
- OFFSET_DEBUGSTAT = 0x64,
- OFFSET_DEBUGCTRL = 0x68,
- OFFSET_TRANSFER_LEN_AUX = 0x6c,
- OFFSET_CLOCK_DIV = 0x70,
+ OFFSET_DATA_PORT,
+ OFFSET_SLAVE_ADDR,
+ OFFSET_INTR_MASK,
+ OFFSET_INTR_STAT,
+ OFFSET_CONTROL,
+ OFFSET_TRANSFER_LEN,
+ OFFSET_TRANSAC_LEN,
+ OFFSET_DELAY_LEN,
+ OFFSET_TIMING,
+ OFFSET_START,
+ OFFSET_EXT_CONF,
+ OFFSET_FIFO_STAT,
+ OFFSET_FIFO_THRESH,
+ OFFSET_FIFO_ADDR_CLR,
+ OFFSET_IO_CONFIG,
+ OFFSET_RSV_DEBUG,
+ OFFSET_HS,
+ OFFSET_SOFTRESET,
+ OFFSET_DCM_EN,
+ OFFSET_PATH_DIR,
+ OFFSET_DEBUGSTAT,
+ OFFSET_DEBUGCTRL,
+ OFFSET_TRANSFER_LEN_AUX,
+ OFFSET_CLOCK_DIV,
+};
+
+static const u16 mt_i2c_regs_v1[] = {
+ [OFFSET_DATA_PORT] = 0x0,
+ [OFFSET_SLAVE_ADDR] = 0x4,
+ [OFFSET_INTR_MASK] = 0x8,
+ [OFFSET_INTR_STAT] = 0xc,
+ [OFFSET_CONTROL] = 0x10,
+ [OFFSET_TRANSFER_LEN] = 0x14,
+ [OFFSET_TRANSAC_LEN] = 0x18,
+ [OFFSET_DELAY_LEN] = 0x1c,
+ [OFFSET_TIMING] = 0x20,
+ [OFFSET_START] = 0x24,
+ [OFFSET_EXT_CONF] = 0x28,
+ [OFFSET_FIFO_STAT] = 0x30,
+ [OFFSET_FIFO_THRESH] = 0x34,
+ [OFFSET_FIFO_ADDR_CLR] = 0x38,
+ [OFFSET_IO_CONFIG] = 0x40,
+ [OFFSET_RSV_DEBUG] = 0x44,
+ [OFFSET_HS] = 0x48,
+ [OFFSET_SOFTRESET] = 0x50,
+ [OFFSET_DCM_EN] = 0x54,
+ [OFFSET_PATH_DIR] = 0x60,
+ [OFFSET_DEBUGSTAT] = 0x64,
+ [OFFSET_DEBUGCTRL] = 0x68,
+ [OFFSET_TRANSFER_LEN_AUX] = 0x6c,
+ [OFFSET_CLOCK_DIV] = 0x70,
};

struct mtk_i2c_compatible {
const struct i2c_adapter_quirks *quirks;
+ const u16 *regs;
unsigned char pmic_i2c: 1;
unsigned char dcm: 1;
unsigned char auto_restart: 1;
@@ -181,6 +209,7 @@ struct mtk_i2c {
};

static const struct mtk_i2c_compatible mt2712_compat = {
+ .regs = mt_i2c_regs_v1,
.pmic_i2c = 0,
.dcm = 1,
.auto_restart = 1,
@@ -191,6 +220,7 @@ struct mtk_i2c {

static const struct mtk_i2c_compatible mt6577_compat = {
.quirks = &mt6577_i2c_quirks,
+ .regs = mt_i2c_regs_v1,
.pmic_i2c = 0,
.dcm = 1,
.auto_restart = 0,
@@ -201,6 +231,7 @@ struct mtk_i2c {

static const struct mtk_i2c_compatible mt6589_compat = {
.quirks = &mt6577_i2c_quirks,
+ .regs = mt_i2c_regs_v1,
.pmic_i2c = 1,
.dcm = 0,
.auto_restart = 0,
@@ -211,6 +242,7 @@ struct mtk_i2c {

static const struct mtk_i2c_compatible mt7622_compat = {
.quirks = &mt7622_i2c_quirks,
+ .regs = mt_i2c_regs_v1,
.pmic_i2c = 0,
.dcm = 1,
.auto_restart = 1,
@@ -220,6 +252,7 @@ struct mtk_i2c {
};

static const struct mtk_i2c_compatible mt8173_compat = {
+ .regs = mt_i2c_regs_v1,
.pmic_i2c = 0,
.dcm = 1,
.auto_restart = 1,
@@ -238,6 +271,17 @@ struct mtk_i2c {
};
MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);

+static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg)
+{
+ return readw(i2c->base + i2c->dev_comp->regs[reg]);
+}
+
+static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val,
+ enum I2C_REGS_OFFSET reg)
+{
+ writew(val, i2c->base + i2c->dev_comp->regs[reg]);
+}
+
static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
{
int ret;
@@ -278,31 +322,31 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
{
u16 control_reg;

- writew(I2C_SOFT_RST, i2c->base + OFFSET_SOFTRESET);
+ mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET);

/* Set ioconfig */
if (i2c->use_push_pull)
- writew(I2C_IO_CONFIG_PUSH_PULL, i2c->base + OFFSET_IO_CONFIG);
+ mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG);
else
- writew(I2C_IO_CONFIG_OPEN_DRAIN, i2c->base + OFFSET_IO_CONFIG);
+ mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG);

if (i2c->dev_comp->dcm)
- writew(I2C_DCM_DISABLE, i2c->base + OFFSET_DCM_EN);
+ mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN);

if (i2c->dev_comp->timing_adjust)
- writew(I2C_DEFAULT_CLK_DIV - 1, i2c->base + OFFSET_CLOCK_DIV);
+ mtk_i2c_writew(i2c, I2C_DEFAULT_CLK_DIV - 1, OFFSET_CLOCK_DIV);

- writew(i2c->timing_reg, i2c->base + OFFSET_TIMING);
- writew(i2c->high_speed_reg, i2c->base + OFFSET_HS);
+ mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING);
+ mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS);

/* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
if (i2c->have_pmic)
- writew(I2C_CONTROL_WRAPPER, i2c->base + OFFSET_PATH_DIR);
+ mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR);

control_reg = I2C_CONTROL_ACKERR_DET_EN |
I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
- writew(control_reg, i2c->base + OFFSET_CONTROL);
- writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN);
+ mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
+ mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN);

writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
udelay(50);
@@ -454,7 +498,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,

reinit_completion(&i2c->msg_complete);

- control_reg = readw(i2c->base + OFFSET_CONTROL) &
+ control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
if ((i2c->speed_hz > MAX_FS_MODE_SPEED) || (left_num >= 1))
control_reg |= I2C_CONTROL_RS;
@@ -462,40 +506,41 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
if (i2c->op == I2C_MASTER_WRRD)
control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;

- writew(control_reg, i2c->base + OFFSET_CONTROL);
+ mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);

/* set start condition */
if (i2c->speed_hz <= I2C_DEFAULT_SPEED)
- writew(I2C_ST_START_CON, i2c->base + OFFSET_EXT_CONF);
+ mtk_i2c_writew(i2c, I2C_ST_START_CON, OFFSET_EXT_CONF);
else
- writew(I2C_FS_START_CON, i2c->base + OFFSET_EXT_CONF);
+ mtk_i2c_writew(i2c, I2C_FS_START_CON, OFFSET_EXT_CONF);

addr_reg = i2c_8bit_addr_from_msg(msgs);
- writew(addr_reg, i2c->base + OFFSET_SLAVE_ADDR);
+ mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR);

/* Clear interrupt status */
- writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
- I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT);
- writew(I2C_FIFO_ADDR_CLR, i2c->base + OFFSET_FIFO_ADDR_CLR);
+ mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
+ I2C_TRANSAC_COMP, OFFSET_INTR_STAT);
+
+ mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR);

/* Enable interrupt */
- writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
- I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_MASK);
+ mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
+ I2C_TRANSAC_COMP, OFFSET_INTR_MASK);

/* Set transfer and transaction len */
if (i2c->op == I2C_MASTER_WRRD) {
if (i2c->dev_comp->aux_len_reg) {
- writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN);
- writew((msgs + 1)->len, i2c->base +
- OFFSET_TRANSFER_LEN_AUX);
+ mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
+ mtk_i2c_writew(i2c, (msgs + 1)->len,
+ OFFSET_TRANSFER_LEN_AUX);
} else {
- writew(msgs->len | ((msgs + 1)->len) << 8,
- i2c->base + OFFSET_TRANSFER_LEN);
+ mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8,
+ OFFSET_TRANSFER_LEN);
}
- writew(I2C_WRRD_TRANAC_VALUE, i2c->base + OFFSET_TRANSAC_LEN);
+ mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN);
} else {
- writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN);
- writew(num, i2c->base + OFFSET_TRANSAC_LEN);
+ mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
+ mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
}

/* Prepare buffer data to start transfer */
@@ -607,14 +652,14 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
if (left_num >= 1)
start_reg |= I2C_RS_MUL_CNFG;
}
- writew(start_reg, i2c->base + OFFSET_START);
+ mtk_i2c_writew(i2c, start_reg, OFFSET_START);

ret = wait_for_completion_timeout(&i2c->msg_complete,
i2c->adap.timeout);

/* Clear interrupt mask */
- writew(~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
- I2C_TRANSAC_COMP), i2c->base + OFFSET_INTR_MASK);
+ mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
+ I2C_TRANSAC_COMP), OFFSET_INTR_MASK);

if (i2c->op == I2C_MASTER_WR) {
dma_unmap_single(i2c->dev, wpaddr,
@@ -724,8 +769,8 @@ static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
if (i2c->auto_restart)
restart_flag = I2C_RS_TRANSFER;

- intr_stat = readw(i2c->base + OFFSET_INTR_STAT);
- writew(intr_stat, i2c->base + OFFSET_INTR_STAT);
+ intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
+ mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT);

/*
* when occurs ack error, i2c controller generate two interrupts
@@ -737,8 +782,8 @@ static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) {
i2c->ignore_restart_irq = false;
i2c->irq_stat = 0;
- writew(I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | I2C_TRANSAC_START,
- i2c->base + OFFSET_START);
+ mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG |
+ I2C_TRANSAC_START, OFFSET_START);
} else {
if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
complete(&i2c->msg_complete);
--
1.7.9.5

2018-12-04 05:50:29

by Sean Wang

Subject: Re: [PATCH 5/5] i2c: mediatek: Add i2c compatible for MediaTek MT8183

<[email protected]> 於 2018年12月3日 週一 上午5:34寫道：
>
> From: qii wang <[email protected]>
>
> Add i2c compatible for MT8183. Compare to 2712 i2c controller, MT8183 has
> different registers, offsets, clock, and multi-user function.
>
> Signed-off-by: qii wang <[email protected]>
> ---
> drivers/i2c/busses/i2c-mt65xx.c | 136 +++++++++++++++++++++++++++++++++++++--
> 1 file changed, 130 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
> index 428ac99..6b979ab 100644
> --- a/drivers/i2c/busses/i2c-mt65xx.c
> +++ b/drivers/i2c/busses/i2c-mt65xx.c
> @@ -35,17 +35,23 @@
> #include <linux/slab.h>
>
> #define I2C_RS_TRANSFER (1 << 4)
> +#define I2C_ARB_LOST (1 << 3)

it seems no one refers to the macro in the patch so it should be
better to be removed

> #define I2C_HS_NACKERR (1 << 2)
> #define I2C_ACKERR (1 << 1)
> #define I2C_TRANSAC_COMP (1 << 0)
> #define I2C_TRANSAC_START (1 << 0)
> +#define I2C_RESUME_ARBIT (1 << 1)
> #define I2C_RS_MUL_CNFG (1 << 15)
> #define I2C_RS_MUL_TRIG (1 << 14)
> +#define I2C_HS_TIME_EN (1 << 7)
> #define I2C_DCM_DISABLE 0x0000
> #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
> #define I2C_IO_CONFIG_PUSH_PULL 0x0000
> #define I2C_SOFT_RST 0x0001
> #define I2C_FIFO_ADDR_CLR 0x0001
> +#define I2C_FIFO_ADDR_CLRH 0x0002
> +#define I2C_FIFO_ADDR_CLR_MCH 0x0004
> +#define I2C_HFIFO_DATA 0x8208
> #define I2C_DELAY_LEN 0x0002
> #define I2C_ST_START_CON 0x8001
> #define I2C_FS_START_CON 0x1800
> @@ -76,6 +82,8 @@
> #define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
> #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
> #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
> +#define I2C_CONTROL_DMAACK_EN (0x1 << 8)
> +#define I2C_CONTROL_ASYNC_MODE (0x1 << 9)
> #define I2C_CONTROL_WRAPPER (0x1 << 0)
>
> #define I2C_DRV_NAME "i2c-mt65xx"
> @@ -130,6 +138,15 @@ enum I2C_REGS_OFFSET {
> OFFSET_DEBUGCTRL,
> OFFSET_TRANSFER_LEN_AUX,
> OFFSET_CLOCK_DIV,
> + /* MT8183 only regs */
> + OFFSET_LTIMING,
> + OFFSET_DATA_TIMING,
> + OFFSET_MCU_INTR,
> + OFFSET_HW_TIMEOUT,
> + OFFSET_HFIFO_DATA,
> + OFFSET_HFIFO_STAT,
> + OFFSET_MULTI_DMA,
> + OFFSET_ROLLBACK,
> };
>
> static const u16 mt_i2c_regs_v1[] = {
> @@ -159,6 +176,39 @@ enum I2C_REGS_OFFSET {
> [OFFSET_CLOCK_DIV] = 0x70,
> };
>
> +static const u16 mt_i2c_regs_v2[] = {
> + [OFFSET_DATA_PORT] = 0x0,
> + [OFFSET_SLAVE_ADDR] = 0x4,
> + [OFFSET_INTR_MASK] = 0x8,
> + [OFFSET_INTR_STAT] = 0xc,
> + [OFFSET_CONTROL] = 0x10,
> + [OFFSET_TRANSFER_LEN] = 0x14,
> + [OFFSET_TRANSAC_LEN] = 0x18,
> + [OFFSET_DELAY_LEN] = 0x1c,
> + [OFFSET_TIMING] = 0x20,
> + [OFFSET_START] = 0x24,
> + [OFFSET_EXT_CONF] = 0x28,
> + [OFFSET_LTIMING] = 0x2c,
> + [OFFSET_HS] = 0x30,
> + [OFFSET_IO_CONFIG] = 0x34,
> + [OFFSET_FIFO_ADDR_CLR] = 0x38,
> + [OFFSET_DATA_TIMING] = 0x3c,
> + [OFFSET_MCU_INTR] = 0x40,
> + [OFFSET_TRANSFER_LEN_AUX] = 0x44,
> + [OFFSET_CLOCK_DIV] = 0x48,
> + [OFFSET_HW_TIMEOUT] = 0x4c,
> + [OFFSET_SOFTRESET] = 0x50,
> + [OFFSET_HFIFO_DATA] = 0x70,
> + [OFFSET_DEBUGSTAT] = 0xe0,
> + [OFFSET_DEBUGCTRL] = 0xe8,
> + [OFFSET_FIFO_STAT] = 0xf4,
> + [OFFSET_FIFO_THRESH] = 0xf8,
> + [OFFSET_HFIFO_STAT] = 0xfc,
> + [OFFSET_DCM_EN] = 0xf88,
> + [OFFSET_MULTI_DMA] = 0xf8c,
> + [OFFSET_ROLLBACK] = 0xf98,
> +};
> +
> struct mtk_i2c_compatible {
> const struct i2c_adapter_quirks *quirks;
> const u16 *regs;
> @@ -168,6 +218,7 @@ struct mtk_i2c_compatible {
> unsigned char aux_len_reg: 1;
> unsigned char support_33bits: 1;
> unsigned char timing_adjust: 1;
> + unsigned char dma_sync: 1;
> };
>
> struct mtk_i2c {
> @@ -181,8 +232,11 @@ struct mtk_i2c {
> struct clk *clk_main; /* main clock for i2c bus */
> struct clk *clk_dma; /* DMA clock for i2c via DMA */
> struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */
> + struct clk *clk_arb; /* Arbitrator clock for i2c */
> bool have_pmic; /* can use i2c pins from PMIC */
> bool use_push_pull; /* IO config push-pull mode */
> + bool share_i3c; /* share i3c IP*/
> + u32 ch_offset; /* i2c multi-user channel offset */
>
> u16 irq_stat; /* interrupt status */
> unsigned int clk_src_div;
> @@ -190,6 +244,7 @@ struct mtk_i2c {
> enum mtk_trans_op op;
> u16 timing_reg;
> u16 high_speed_reg;
> + u16 ltiming_reg;
> unsigned char auto_restart;
> bool ignore_restart_irq;
> const struct mtk_i2c_compatible *dev_comp;
> @@ -216,6 +271,7 @@ struct mtk_i2c {
> .aux_len_reg = 1,
> .support_33bits = 1,
> .timing_adjust = 1,
> + .dma_sync = 0,
> };
>
> static const struct mtk_i2c_compatible mt6577_compat = {
> @@ -227,6 +283,7 @@ struct mtk_i2c {
> .aux_len_reg = 0,
> .support_33bits = 0,
> .timing_adjust = 0,
> + .dma_sync = 0,
> };
>
> static const struct mtk_i2c_compatible mt6589_compat = {
> @@ -238,6 +295,7 @@ struct mtk_i2c {
> .aux_len_reg = 0,
> .support_33bits = 0,
> .timing_adjust = 0,
> + .dma_sync = 0,
> };
>
> static const struct mtk_i2c_compatible mt7622_compat = {
> @@ -249,6 +307,7 @@ struct mtk_i2c {
> .aux_len_reg = 1,
> .support_33bits = 0,
> .timing_adjust = 0,
> + .dma_sync = 0,
> };
>
> static const struct mtk_i2c_compatible mt8173_compat = {
> @@ -259,6 +318,18 @@ struct mtk_i2c {
> .aux_len_reg = 1,
> .support_33bits = 1,
> .timing_adjust = 0,
> + .dma_sync = 0,
> +};
> +
> +static const struct mtk_i2c_compatible mt8183_compat = {
> + .regs = mt_i2c_regs_v2,
> + .pmic_i2c = 0,
> + .dcm = 0,
> + .auto_restart = 1,
> + .aux_len_reg = 1,
> + .support_33bits = 1,
> + .timing_adjust = 1,
> + .dma_sync = 1,
> };
>
> static const struct of_device_id mtk_i2c_of_match[] = {
> @@ -267,19 +338,20 @@ struct mtk_i2c {
> { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
> { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
> { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
> + { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
> {}
> };
> MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
>
> static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg)
> {
> - return readw(i2c->base + i2c->dev_comp->regs[reg]);
> + return readw(i2c->base + i2c->ch_offset + i2c->dev_comp->regs[reg]);
> }
>
> static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val,
> enum I2C_REGS_OFFSET reg)
> {
> - writew(val, i2c->base + i2c->dev_comp->regs[reg]);
> + writew(val, i2c->base + i2c->ch_offset + i2c->dev_comp->regs[reg]);
> }
>
> static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
> @@ -299,8 +371,18 @@ static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
> if (ret)
> goto err_pmic;
> }
> +
> + if (i2c->clk_arb) {
> + ret = clk_prepare_enable(i2c->clk_arb);
> + if (ret)
> + goto err_arb;
> + }
> +
> return 0;
>
> +err_arb:
> + if (i2c->have_pmic)
> + clk_disable_unprepare(i2c->clk_pmic);
> err_pmic:
> clk_disable_unprepare(i2c->clk_main);
> err_main:
> @@ -311,6 +393,9 @@ static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
>
> static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
> {
> + if (i2c->clk_arb)
> + clk_disable_unprepare(i2c->clk_arb);
> +
> if (i2c->have_pmic)
> clk_disable_unprepare(i2c->clk_pmic);
>
> @@ -333,11 +418,23 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
> if (i2c->dev_comp->dcm)
> mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN);
>
> - if (i2c->dev_comp->timing_adjust)
> + if (i2c->ch_offset)
> + writew(I2C_RESUME_ARBIT, i2c->base +
> + i2c->dev_comp->regs[OFFSET_START]);
> +
> + if (i2c->dev_comp->timing_adjust && i2c->share_i3c) {
> + mtk_i2c_writew(i2c, (I2C_DEFAULT_CLK_DIV - 1) |
> + (I2C_DEFAULT_CLK_DIV - 1) << 8,
> + OFFSET_CLOCK_DIV);
> + i2c->high_speed_reg |= I2C_HS_TIME_EN;
> + } else {
> mtk_i2c_writew(i2c, I2C_DEFAULT_CLK_DIV - 1, OFFSET_CLOCK_DIV);
> + }
>
> mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING);
> mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS);
> + if (i2c->dev_comp->regs == mt_i2c_regs_v2)
> + mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING);
>
> /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
> if (i2c->have_pmic)
> @@ -345,6 +442,9 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
>
> control_reg = I2C_CONTROL_ACKERR_DET_EN |
> I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
> + if (i2c->dev_comp->dma_sync)
> + control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE;
> +
> mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
> mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN);
>
> @@ -434,6 +534,8 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
> unsigned int clk_src;
> unsigned int step_cnt;
> unsigned int sample_cnt;
> + unsigned int l_step_cnt;
> + unsigned int l_sample_cnt;
> unsigned int target_speed;
> int ret;
>
> @@ -443,11 +545,11 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
> if (target_speed > MAX_FS_MODE_SPEED) {
> /* Set master code speed register */
> ret = mtk_i2c_calculate_speed(i2c, clk_src, MAX_FS_MODE_SPEED,
> - &step_cnt, &sample_cnt);
> + &l_step_cnt, &l_sample_cnt);
> if (ret < 0)
> return ret;
>
> - i2c->timing_reg = (sample_cnt << 8) | step_cnt;
> + i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
>
> /* Set the high speed mode register */
> ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
> @@ -457,6 +559,8 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
>
> i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
> (sample_cnt << 12) | (step_cnt << 8);
> + i2c->ltiming_reg = (l_sample_cnt << 6) | l_step_cnt |
> + (sample_cnt << 12) | (step_cnt << 9);
> } else {
> ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
> &step_cnt, &sample_cnt);
> @@ -467,6 +571,8 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
>
> /* Disable the high speed transaction */
> i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
> +
> + i2c->ltiming_reg = (sample_cnt << 6) | step_cnt;
> }
>
> return 0;
> @@ -483,6 +589,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> u16 addr_reg;
> u16 start_reg;
> u16 control_reg;
> + u16 fifo_clr_reg;
> u16 restart_flag = 0;
> u32 reg_4g_mode;
> u8 *dma_rd_buf = NULL;
> @@ -521,7 +628,15 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
> I2C_TRANSAC_COMP, OFFSET_INTR_STAT);
>
> - mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR);

There's a missing initialization to fifo_clr_reg here, I guess
fifo_clr_reg = I2C_FIFO_ADDR_CLR should be necessarily made here;

> + if (i2c->share_i3c)
> + fifo_clr_reg = I2C_FIFO_ADDR_CLR | I2C_FIFO_ADDR_CLRH;

fifo_clr_reg |= I2C_FIFO_ADDR_CLRH baed on initialized value

> + if (i2c->ch_offset)
> + fifo_clr_reg = I2C_FIFO_ADDR_CLR | I2C_FIFO_ADDR_CLR_MCH;

and then fifo_clr_reg |= I2C_FIFO_ADDR_CLR_MCH;

> +
> + mtk_i2c_writew(i2c, fifo_clr_reg, OFFSET_FIFO_ADDR_CLR);
> +
> + if ((i2c->speed_hz > MAX_FS_MODE_SPEED) && i2c->share_i3c)
> + mtk_i2c_writew(i2c, I2C_HFIFO_DATA, OFFSET_HFIFO_DATA);
>
> /* Enable interrupt */
> mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
> @@ -817,6 +932,11 @@ static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c)
> if (i2c->clk_src_div == 0)
> return -EINVAL;
>
> + ret = of_property_read_u32(np, "ch-offset", &i2c->ch_offset);

if ch-offset is a vendor-specific property, it should be better to add
a vendor prefix

> + if (ret < 0)
> + i2c->ch_offset = 0;
> +
> + i2c->share_i3c = of_property_read_bool(np, "mediatek,share-i3c");
> i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
> i2c->use_push_pull =
> of_property_read_bool(np, "mediatek,use-push-pull");
> @@ -884,6 +1004,10 @@ static int mtk_i2c_probe(struct platform_device *pdev)
> return PTR_ERR(i2c->clk_dma);
> }
>
> + i2c->clk_arb = devm_clk_get(&pdev->dev, "arb");
> + if (IS_ERR(i2c->clk_arb))
> + i2c->clk_arb = NULL;
> +
> clk = i2c->clk_main;
> if (i2c->have_pmic) {
> i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
> --
> 1.7.9.5
>
>
> _______________________________________________
> Linux-mediatek mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

2018-12-04 20:20:39

by Sean Wang

Subject: Re: [PATCH 1/5] dt-bindings: i2c: Add Mediatek MT7629 i2c binding

<[email protected]> 於 2018年12月3日 週一 上午5:34寫道：
>
> From: qii wang <[email protected]>
>
> Add MT7629 i2c binding to i2c-mt2712.txt and there is no need to

where's i2c-mt2712.txt mentioned here?

> modify i2c driver.

suggest not to mention driver in any dt-binding, dt-binding self
should be os-agnostic

>
> Signed-off-by: qii wang <[email protected]>
> ---
> Documentation/devicetree/bindings/i2c/i2c-mtk.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt b/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
> index e199695..7729e57 100644
> --- a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
> +++ b/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
> @@ -10,6 +10,7 @@ Required properties:
> "mediatek,mt6589-i2c": for MediaTek MT6589
> "mediatek,mt7622-i2c": for MediaTek MT7622
> "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
> + "mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek mt7629

change mt7629 to MT7629 to align to the others

> "mediatek,mt8173-i2c": for MediaTek MT8173
> - reg: physical base address of the controller and dma base, length of memory
> mapped region.
> --
> 1.7.9.5
>
>
> _______________________________________________
> Linux-mediatek mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

2018-12-04 20:38:28

by Sean Wang

Subject: Re: [PATCH 2/5] i2c: mediatek: remove useless code and replace definitions

<[email protected]> 於 2018年12月3日 週一 上午5:40寫道：
>
> From: qii wang <[email protected]>
>
> Completion_done is useless when we don't use its return value,
> so we remove it. Different speeds have been defined by macros,
> so we use macros definitions.
>
> Signed-off-by: qii wang <[email protected]>
Reviewed-by: Sean Wang <[email protected]>

> ---
> drivers/i2c/busses/i2c-mt65xx.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
> index a74ef76..660de1e 100644
> --- a/drivers/i2c/busses/i2c-mt65xx.c
> +++ b/drivers/i2c/busses/i2c-mt65xx.c
> @@ -456,7 +456,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
>
> control_reg = readw(i2c->base + OFFSET_CONTROL) &
> ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
> - if ((i2c->speed_hz > 400000) || (left_num >= 1))
> + if ((i2c->speed_hz > MAX_FS_MODE_SPEED) || (left_num >= 1))
> control_reg |= I2C_CONTROL_RS;
>
> if (i2c->op == I2C_MASTER_WRRD)
> @@ -465,7 +465,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> writew(control_reg, i2c->base + OFFSET_CONTROL);
>
> /* set start condition */
> - if (i2c->speed_hz <= 100000)
> + if (i2c->speed_hz <= I2C_DEFAULT_SPEED)
> writew(I2C_ST_START_CON, i2c->base + OFFSET_EXT_CONF);
> else
> writew(I2C_FS_START_CON, i2c->base + OFFSET_EXT_CONF);
> @@ -642,8 +642,6 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> return -ETIMEDOUT;
> }
>
> - completion_done(&i2c->msg_complete);
> -
> if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
> dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
> mtk_i2c_init_hw(i2c);
> --
> 1.7.9.5
>
>
> _______________________________________________
> Linux-mediatek mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

2018-12-04 20:46:30

by Sean Wang

Subject: Re: [PATCH 3/5] i2c: mediatek: Add offsets array for new i2c registers

<[email protected]> 於 2018年12月3日 週一 上午5:35寫道：
>
> From: qii wang <[email protected]>
>
> New i2c registers would have different offsets, so we use different
> offsets array to distinguish different i2c registers version.
>
> Signed-off-by: qii wang <[email protected]>

They are almost 1 to 1 function translation being taken here, so
Reviewed-by: Sean Wang <[email protected]>

> ---
> drivers/i2c/busses/i2c-mt65xx.c | 163 +++++++++++++++++++++++++--------------
> 1 file changed, 104 insertions(+), 59 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
> index 660de1e..428ac99 100644
> --- a/drivers/i2c/busses/i2c-mt65xx.c
> +++ b/drivers/i2c/busses/i2c-mt65xx.c
> @@ -106,34 +106,62 @@ enum mtk_trans_op {
> };
>
> enum I2C_REGS_OFFSET {
> - OFFSET_DATA_PORT = 0x0,
> - OFFSET_SLAVE_ADDR = 0x04,
> - OFFSET_INTR_MASK = 0x08,
> - OFFSET_INTR_STAT = 0x0c,
> - OFFSET_CONTROL = 0x10,
> - OFFSET_TRANSFER_LEN = 0x14,
> - OFFSET_TRANSAC_LEN = 0x18,
> - OFFSET_DELAY_LEN = 0x1c,
> - OFFSET_TIMING = 0x20,
> - OFFSET_START = 0x24,
> - OFFSET_EXT_CONF = 0x28,
> - OFFSET_FIFO_STAT = 0x30,
> - OFFSET_FIFO_THRESH = 0x34,
> - OFFSET_FIFO_ADDR_CLR = 0x38,
> - OFFSET_IO_CONFIG = 0x40,
> - OFFSET_RSV_DEBUG = 0x44,
> - OFFSET_HS = 0x48,
> - OFFSET_SOFTRESET = 0x50,
> - OFFSET_DCM_EN = 0x54,
> - OFFSET_PATH_DIR = 0x60,
> - OFFSET_DEBUGSTAT = 0x64,
> - OFFSET_DEBUGCTRL = 0x68,
> - OFFSET_TRANSFER_LEN_AUX = 0x6c,
> - OFFSET_CLOCK_DIV = 0x70,
> + OFFSET_DATA_PORT,
> + OFFSET_SLAVE_ADDR,
> + OFFSET_INTR_MASK,
> + OFFSET_INTR_STAT,
> + OFFSET_CONTROL,
> + OFFSET_TRANSFER_LEN,
> + OFFSET_TRANSAC_LEN,
> + OFFSET_DELAY_LEN,
> + OFFSET_TIMING,
> + OFFSET_START,
> + OFFSET_EXT_CONF,
> + OFFSET_FIFO_STAT,
> + OFFSET_FIFO_THRESH,
> + OFFSET_FIFO_ADDR_CLR,
> + OFFSET_IO_CONFIG,
> + OFFSET_RSV_DEBUG,
> + OFFSET_HS,
> + OFFSET_SOFTRESET,
> + OFFSET_DCM_EN,
> + OFFSET_PATH_DIR,
> + OFFSET_DEBUGSTAT,
> + OFFSET_DEBUGCTRL,
> + OFFSET_TRANSFER_LEN_AUX,
> + OFFSET_CLOCK_DIV,
> +};
> +
> +static const u16 mt_i2c_regs_v1[] = {
> + [OFFSET_DATA_PORT] = 0x0,
> + [OFFSET_SLAVE_ADDR] = 0x4,
> + [OFFSET_INTR_MASK] = 0x8,
> + [OFFSET_INTR_STAT] = 0xc,
> + [OFFSET_CONTROL] = 0x10,
> + [OFFSET_TRANSFER_LEN] = 0x14,
> + [OFFSET_TRANSAC_LEN] = 0x18,
> + [OFFSET_DELAY_LEN] = 0x1c,
> + [OFFSET_TIMING] = 0x20,
> + [OFFSET_START] = 0x24,
> + [OFFSET_EXT_CONF] = 0x28,
> + [OFFSET_FIFO_STAT] = 0x30,
> + [OFFSET_FIFO_THRESH] = 0x34,
> + [OFFSET_FIFO_ADDR_CLR] = 0x38,
> + [OFFSET_IO_CONFIG] = 0x40,
> + [OFFSET_RSV_DEBUG] = 0x44,
> + [OFFSET_HS] = 0x48,
> + [OFFSET_SOFTRESET] = 0x50,
> + [OFFSET_DCM_EN] = 0x54,
> + [OFFSET_PATH_DIR] = 0x60,
> + [OFFSET_DEBUGSTAT] = 0x64,
> + [OFFSET_DEBUGCTRL] = 0x68,
> + [OFFSET_TRANSFER_LEN_AUX] = 0x6c,
> + [OFFSET_CLOCK_DIV] = 0x70,
> };
>
> struct mtk_i2c_compatible {
> const struct i2c_adapter_quirks *quirks;
> + const u16 *regs;
> unsigned char pmic_i2c: 1;
> unsigned char dcm: 1;
> unsigned char auto_restart: 1;
> @@ -181,6 +209,7 @@ struct mtk_i2c {
> };
>
> static const struct mtk_i2c_compatible mt2712_compat = {
> + .regs = mt_i2c_regs_v1,
> .pmic_i2c = 0,
> .dcm = 1,
> .auto_restart = 1,
> @@ -191,6 +220,7 @@ struct mtk_i2c {
>
> static const struct mtk_i2c_compatible mt6577_compat = {
> .quirks = &mt6577_i2c_quirks,
> + .regs = mt_i2c_regs_v1,
> .pmic_i2c = 0,
> .dcm = 1,
> .auto_restart = 0,
> @@ -201,6 +231,7 @@ struct mtk_i2c {
>
> static const struct mtk_i2c_compatible mt6589_compat = {
> .quirks = &mt6577_i2c_quirks,
> + .regs = mt_i2c_regs_v1,
> .pmic_i2c = 1,
> .dcm = 0,
> .auto_restart = 0,
> @@ -211,6 +242,7 @@ struct mtk_i2c {
>
> static const struct mtk_i2c_compatible mt7622_compat = {
> .quirks = &mt7622_i2c_quirks,
> + .regs = mt_i2c_regs_v1,
> .pmic_i2c = 0,
> .dcm = 1,
> .auto_restart = 1,
> @@ -220,6 +252,7 @@ struct mtk_i2c {
> };
>
> static const struct mtk_i2c_compatible mt8173_compat = {
> + .regs = mt_i2c_regs_v1,
> .pmic_i2c = 0,
> .dcm = 1,
> .auto_restart = 1,
> @@ -238,6 +271,17 @@ struct mtk_i2c {
> };
> MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
>
> +static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg)
> +{
> + return readw(i2c->base + i2c->dev_comp->regs[reg]);
> +}
> +
> +static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val,
> + enum I2C_REGS_OFFSET reg)
> +{
> + writew(val, i2c->base + i2c->dev_comp->regs[reg]);
> +}
> +
> static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
> {
> int ret;
> @@ -278,31 +322,31 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
> {
> u16 control_reg;
>
> - writew(I2C_SOFT_RST, i2c->base + OFFSET_SOFTRESET);
> + mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET);
>
> /* Set ioconfig */
> if (i2c->use_push_pull)
> - writew(I2C_IO_CONFIG_PUSH_PULL, i2c->base + OFFSET_IO_CONFIG);
> + mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG);
> else
> - writew(I2C_IO_CONFIG_OPEN_DRAIN, i2c->base + OFFSET_IO_CONFIG);
> + mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG);
>
> if (i2c->dev_comp->dcm)
> - writew(I2C_DCM_DISABLE, i2c->base + OFFSET_DCM_EN);
> + mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN);
>
> if (i2c->dev_comp->timing_adjust)
> - writew(I2C_DEFAULT_CLK_DIV - 1, i2c->base + OFFSET_CLOCK_DIV);
> + mtk_i2c_writew(i2c, I2C_DEFAULT_CLK_DIV - 1, OFFSET_CLOCK_DIV);
>
> - writew(i2c->timing_reg, i2c->base + OFFSET_TIMING);
> - writew(i2c->high_speed_reg, i2c->base + OFFSET_HS);
> + mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING);
> + mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS);
>
> /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
> if (i2c->have_pmic)
> - writew(I2C_CONTROL_WRAPPER, i2c->base + OFFSET_PATH_DIR);
> + mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR);
>
> control_reg = I2C_CONTROL_ACKERR_DET_EN |
> I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
> - writew(control_reg, i2c->base + OFFSET_CONTROL);
> - writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN);
> + mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
> + mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN);
>
> writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
> udelay(50);
> @@ -454,7 +498,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
>
> reinit_completion(&i2c->msg_complete);
>
> - control_reg = readw(i2c->base + OFFSET_CONTROL) &
> + control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
> ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
> if ((i2c->speed_hz > MAX_FS_MODE_SPEED) || (left_num >= 1))
> control_reg |= I2C_CONTROL_RS;
> @@ -462,40 +506,41 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> if (i2c->op == I2C_MASTER_WRRD)
> control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
>
> - writew(control_reg, i2c->base + OFFSET_CONTROL);
> + mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
>
> /* set start condition */
> if (i2c->speed_hz <= I2C_DEFAULT_SPEED)
> - writew(I2C_ST_START_CON, i2c->base + OFFSET_EXT_CONF);
> + mtk_i2c_writew(i2c, I2C_ST_START_CON, OFFSET_EXT_CONF);
> else
> - writew(I2C_FS_START_CON, i2c->base + OFFSET_EXT_CONF);
> + mtk_i2c_writew(i2c, I2C_FS_START_CON, OFFSET_EXT_CONF);
>
> addr_reg = i2c_8bit_addr_from_msg(msgs);
> - writew(addr_reg, i2c->base + OFFSET_SLAVE_ADDR);
> + mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR);
>
> /* Clear interrupt status */
> - writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
> - I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT);
> - writew(I2C_FIFO_ADDR_CLR, i2c->base + OFFSET_FIFO_ADDR_CLR);
> + mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
> + I2C_TRANSAC_COMP, OFFSET_INTR_STAT);
> +
> + mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR);
>
> /* Enable interrupt */
> - writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
> - I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_MASK);
> + mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
> + I2C_TRANSAC_COMP, OFFSET_INTR_MASK);
>
> /* Set transfer and transaction len */
> if (i2c->op == I2C_MASTER_WRRD) {
> if (i2c->dev_comp->aux_len_reg) {
> - writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN);
> - writew((msgs + 1)->len, i2c->base +
> - OFFSET_TRANSFER_LEN_AUX);
> + mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
> + mtk_i2c_writew(i2c, (msgs + 1)->len,
> + OFFSET_TRANSFER_LEN_AUX);
> } else {
> - writew(msgs->len | ((msgs + 1)->len) << 8,
> - i2c->base + OFFSET_TRANSFER_LEN);
> + mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8,
> + OFFSET_TRANSFER_LEN);
> }
> - writew(I2C_WRRD_TRANAC_VALUE, i2c->base + OFFSET_TRANSAC_LEN);
> + mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN);
> } else {
> - writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN);
> - writew(num, i2c->base + OFFSET_TRANSAC_LEN);
> + mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
> + mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
> }
>
> /* Prepare buffer data to start transfer */
> @@ -607,14 +652,14 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> if (left_num >= 1)
> start_reg |= I2C_RS_MUL_CNFG;
> }
> - writew(start_reg, i2c->base + OFFSET_START);
> + mtk_i2c_writew(i2c, start_reg, OFFSET_START);
>
> ret = wait_for_completion_timeout(&i2c->msg_complete,
> i2c->adap.timeout);
>
> /* Clear interrupt mask */
> - writew(~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
> - I2C_TRANSAC_COMP), i2c->base + OFFSET_INTR_MASK);
> + mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
> + I2C_TRANSAC_COMP), OFFSET_INTR_MASK);
>
> if (i2c->op == I2C_MASTER_WR) {
> dma_unmap_single(i2c->dev, wpaddr,
> @@ -724,8 +769,8 @@ static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
> if (i2c->auto_restart)
> restart_flag = I2C_RS_TRANSFER;
>
> - intr_stat = readw(i2c->base + OFFSET_INTR_STAT);
> - writew(intr_stat, i2c->base + OFFSET_INTR_STAT);
> + intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
> + mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT);
>
> /*
> * when occurs ack error, i2c controller generate two interrupts
> @@ -737,8 +782,8 @@ static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
> if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) {
> i2c->ignore_restart_irq = false;
> i2c->irq_stat = 0;
> - writew(I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | I2C_TRANSAC_START,
> - i2c->base + OFFSET_START);
> + mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG |
> + I2C_TRANSAC_START, OFFSET_START);
> } else {
> if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
> complete(&i2c->msg_complete);
> --
> 1.7.9.5
>
>
> _______________________________________________
> Linux-mediatek mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

2018-12-04 21:02:53

by Sean Wang

Subject: Re: [PATCH 4/5] dt-bindings: i2c: Add Mediatek MT8183 i2c binding

On Mon, Dec 3, 2018 at 5:34 AM <[email protected]> wrote:
>
> From: qii wang <[email protected]>
>
> Add MT8183 i2c binding to binding file. Compare to 2712 i2c
> controller, MT8183 has different registers, offsets, clock,
> and multi-user function.
>
> Signed-off-by: qii wang <[email protected]>
> ---
> Documentation/devicetree/bindings/i2c/i2c-mtk.txt | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt b/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
> index 7729e57..dfde624 100644
> --- a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
> +++ b/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
> @@ -12,14 +12,15 @@ Required properties:
> "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
> "mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek mt7629
> "mediatek,mt8173-i2c": for MediaTek MT8173
> + "mediatek,mt8183-i2c": for MediaTek MT8183
> - reg: physical base address of the controller and dma base, length of memory
> mapped region.
> - interrupts: interrupt number to the cpu.
> - clock-div: the fixed value for frequency divider of clock source in i2c
> module. Each IC may be different.
> - clocks: clock name from clock manager
> - - clock-names: Must include "main" and "dma", if enable have-pmic need include
> - "pmic" extra.
> + - clock-names: Must include "main" and "dma", "arb" is optional, if enable

if arb is optional, the multi-user function still can work? arb seems
like the clock fed to arbitrating bus when multiple users are
accessing at the same time.

> + have-pmic need include "pmic" extra.
>
> Optional properties:
> - clock-frequency: Frequency in Hz of the bus when transfer, the default value
> @@ -27,6 +28,8 @@ Optional properties:
> - mediatek,have-pmic: platform can control i2c form special pmic side.
> Only mt6589 and mt8135 support this feature.
> - mediatek,use-push-pull: IO config use push-pull mode.
> + - ch-offset: base reg offset for multi-user.

add a vendor prefix if the property is vendor-specific one.

> + - mediatek,share-i3c: i3c controller can share i2c function.
>
> Example:
>
> --
> 1.7.9.5
>
>
> _______________________________________________
> Linux-mediatek mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

2018-12-11 06:40:13

by Qii Wang (王琪)

Subject: Re: [PATCH 1/5] dt-bindings: i2c: Add Mediatek MT7629 i2c binding

On Tue, 2018-12-04 at 12:19 -0800, Sean Wang wrote:
> <[email protected]> 於 2018年12月3日 週一 上午5:34寫道：
> >
> > From: qii wang <[email protected]>
> >
> > Add MT7629 i2c binding to i2c-mt2712.txt and there is no need to
>
> where's i2c-mt2712.txt mentioned here?
>

Sorry, I will rewrite this commit. Such as:

Add MT7629 i2c binding to binding file.

> > modify i2c driver.
>
> suggest not to mention driver in any dt-binding, dt-binding self
> should be os-agnostic
>

Yes, I will remove it.

> >
> > Signed-off-by: qii wang <[email protected]>
> > ---
> > Documentation/devicetree/bindings/i2c/i2c-mtk.txt | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt b/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
> > index e199695..7729e57 100644
> > --- a/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
> > +++ b/Documentation/devicetree/bindings/i2c/i2c-mtk.txt
> > @@ -10,6 +10,7 @@ Required properties:
> > "mediatek,mt6589-i2c": for MediaTek MT6589
> > "mediatek,mt7622-i2c": for MediaTek MT7622
> > "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
> > + "mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek mt7629
>
> change mt7629 to MT7629 to align to the others
>

OK.

> > "mediatek,mt8173-i2c": for MediaTek MT8173
> > - reg: physical base address of the controller and dma base, length of memory
> > mapped region.
> > --
> > 1.7.9.5
> >
> >
> > _______________________________________________
> > Linux-mediatek mailing list
> > [email protected]
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek

2018-12-11 20:22:09

by Wolfram Sang

Subject: Re: [PATCH 2/5] i2c: mediatek: remove useless code and replace definitions

On Mon, Dec 03, 2018 at 09:32:51PM +0800, [email protected] wrote:
> From: qii wang <[email protected]>
>
> Completion_done is useless when we don't use its return value,
> so we remove it. Different speeds have been defined by macros,
> so we use macros definitions.

Those are two seperate patches, or?

>
> Signed-off-by: qii wang <[email protected]>
> ---
> drivers/i2c/busses/i2c-mt65xx.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
> index a74ef76..660de1e 100644
> --- a/drivers/i2c/busses/i2c-mt65xx.c
> +++ b/drivers/i2c/busses/i2c-mt65xx.c
> @@ -456,7 +456,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
>
> control_reg = readw(i2c->base + OFFSET_CONTROL) &
> ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
> - if ((i2c->speed_hz > 400000) || (left_num >= 1))
> + if ((i2c->speed_hz > MAX_FS_MODE_SPEED) || (left_num >= 1))
> control_reg |= I2C_CONTROL_RS;
>
> if (i2c->op == I2C_MASTER_WRRD)
> @@ -465,7 +465,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> writew(control_reg, i2c->base + OFFSET_CONTROL);
>
> /* set start condition */
> - if (i2c->speed_hz <= 100000)
> + if (i2c->speed_hz <= I2C_DEFAULT_SPEED)
> writew(I2C_ST_START_CON, i2c->base + OFFSET_EXT_CONF);
> else
> writew(I2C_FS_START_CON, i2c->base + OFFSET_EXT_CONF);
> @@ -642,8 +642,6 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> return -ETIMEDOUT;
> }
>
> - completion_done(&i2c->msg_complete);
> -
> if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
> dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
> mtk_i2c_init_hw(i2c);
> --
> 1.7.9.5
>

Attachments:

2018-12-11 20:31:08

by Wolfram Sang

Subject: Re: [PATCH 4/5] dt-bindings: i2c: Add Mediatek MT8183 i2c binding

> + - ch-offset: base reg offset for multi-user.

What is "multi-user"? Why can't you add this offset to the reg-property
directly?

> + - mediatek,share-i3c: i3c controller can share i2c function.

Please explain in more detail? Is this an I3C controller?

Attachments:

2018-12-12 07:20:22

by Qii Wang (王琪)

Subject: Re: [PATCH 5/5] i2c: mediatek: Add i2c compatible for MediaTek MT8183

On Mon, 2018-12-03 at 21:49 -0800, Sean Wang wrote:
> <[email protected]> 於 2018年12月3日 週一 上午5:34寫道：
> >
> > From: qii wang <[email protected]>
> >
> > Add i2c compatible for MT8183. Compare to 2712 i2c controller, MT8183 has
> > different registers, offsets, clock, and multi-user function.
> >
> > Signed-off-by: qii wang <[email protected]>
> > ---
> > drivers/i2c/busses/i2c-mt65xx.c | 136 +++++++++++++++++++++++++++++++++++++--
> > 1 file changed, 130 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
> > index 428ac99..6b979ab 100644
> > --- a/drivers/i2c/busses/i2c-mt65xx.c
> > +++ b/drivers/i2c/busses/i2c-mt65xx.c
> > @@ -35,17 +35,23 @@
> > #include <linux/slab.h>
> >
> > #define I2C_RS_TRANSFER (1 << 4)
> > +#define I2C_ARB_LOST (1 << 3)
>
> it seems no one refers to the macro in the patch so it should be
> better to be removed
>

ok, I miss it, I will use it in the next patch.

> > #define I2C_HS_NACKERR (1 << 2)
> > #define I2C_ACKERR (1 << 1)
> > #define I2C_TRANSAC_COMP (1 << 0)
> > #define I2C_TRANSAC_START (1 << 0)
> > +#define I2C_RESUME_ARBIT (1 << 1)
> > #define I2C_RS_MUL_CNFG (1 << 15)
> > #define I2C_RS_MUL_TRIG (1 << 14)
> > +#define I2C_HS_TIME_EN (1 << 7)
> > #define I2C_DCM_DISABLE 0x0000
> > #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
> > #define I2C_IO_CONFIG_PUSH_PULL 0x0000
> > #define I2C_SOFT_RST 0x0001
> > #define I2C_FIFO_ADDR_CLR 0x0001
> > +#define I2C_FIFO_ADDR_CLRH 0x0002
> > +#define I2C_FIFO_ADDR_CLR_MCH 0x0004
> > +#define I2C_HFIFO_DATA 0x8208
> > #define I2C_DELAY_LEN 0x0002
> > #define I2C_ST_START_CON 0x8001
> > #define I2C_FS_START_CON 0x1800
> > @@ -76,6 +82,8 @@
> > #define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
> > #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
> > #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
> > +#define I2C_CONTROL_DMAACK_EN (0x1 << 8)
> > +#define I2C_CONTROL_ASYNC_MODE (0x1 << 9)
> > #define I2C_CONTROL_WRAPPER (0x1 << 0)
> >
> > #define I2C_DRV_NAME "i2c-mt65xx"
> > @@ -130,6 +138,15 @@ enum I2C_REGS_OFFSET {
> > OFFSET_DEBUGCTRL,
> > OFFSET_TRANSFER_LEN_AUX,
> > OFFSET_CLOCK_DIV,
> > + /* MT8183 only regs */
> > + OFFSET_LTIMING,
> > + OFFSET_DATA_TIMING,
> > + OFFSET_MCU_INTR,
> > + OFFSET_HW_TIMEOUT,
> > + OFFSET_HFIFO_DATA,
> > + OFFSET_HFIFO_STAT,
> > + OFFSET_MULTI_DMA,
> > + OFFSET_ROLLBACK,
> > };
> >
> > static const u16 mt_i2c_regs_v1[] = {
> > @@ -159,6 +176,39 @@ enum I2C_REGS_OFFSET {
> > [OFFSET_CLOCK_DIV] = 0x70,
> > };
> >
> > +static const u16 mt_i2c_regs_v2[] = {
> > + [OFFSET_DATA_PORT] = 0x0,
> > + [OFFSET_SLAVE_ADDR] = 0x4,
> > + [OFFSET_INTR_MASK] = 0x8,
> > + [OFFSET_INTR_STAT] = 0xc,
> > + [OFFSET_CONTROL] = 0x10,
> > + [OFFSET_TRANSFER_LEN] = 0x14,
> > + [OFFSET_TRANSAC_LEN] = 0x18,
> > + [OFFSET_DELAY_LEN] = 0x1c,
> > + [OFFSET_TIMING] = 0x20,
> > + [OFFSET_START] = 0x24,
> > + [OFFSET_EXT_CONF] = 0x28,
> > + [OFFSET_LTIMING] = 0x2c,
> > + [OFFSET_HS] = 0x30,
> > + [OFFSET_IO_CONFIG] = 0x34,
> > + [OFFSET_FIFO_ADDR_CLR] = 0x38,
> > + [OFFSET_DATA_TIMING] = 0x3c,
> > + [OFFSET_MCU_INTR] = 0x40,
> > + [OFFSET_TRANSFER_LEN_AUX] = 0x44,
> > + [OFFSET_CLOCK_DIV] = 0x48,
> > + [OFFSET_HW_TIMEOUT] = 0x4c,
> > + [OFFSET_SOFTRESET] = 0x50,
> > + [OFFSET_HFIFO_DATA] = 0x70,
> > + [OFFSET_DEBUGSTAT] = 0xe0,
> > + [OFFSET_DEBUGCTRL] = 0xe8,
> > + [OFFSET_FIFO_STAT] = 0xf4,
> > + [OFFSET_FIFO_THRESH] = 0xf8,
> > + [OFFSET_HFIFO_STAT] = 0xfc,
> > + [OFFSET_DCM_EN] = 0xf88,
> > + [OFFSET_MULTI_DMA] = 0xf8c,
> > + [OFFSET_ROLLBACK] = 0xf98,
> > +};
> > +
> > struct mtk_i2c_compatible {
> > const struct i2c_adapter_quirks *quirks;
> > const u16 *regs;
> > @@ -168,6 +218,7 @@ struct mtk_i2c_compatible {
> > unsigned char aux_len_reg: 1;
> > unsigned char support_33bits: 1;
> > unsigned char timing_adjust: 1;
> > + unsigned char dma_sync: 1;
> > };
> >
> > struct mtk_i2c {
> > @@ -181,8 +232,11 @@ struct mtk_i2c {
> > struct clk *clk_main; /* main clock for i2c bus */
> > struct clk *clk_dma; /* DMA clock for i2c via DMA */
> > struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */
> > + struct clk *clk_arb; /* Arbitrator clock for i2c */
> > bool have_pmic; /* can use i2c pins from PMIC */
> > bool use_push_pull; /* IO config push-pull mode */
> > + bool share_i3c; /* share i3c IP*/
> > + u32 ch_offset; /* i2c multi-user channel offset */
> >
> > u16 irq_stat; /* interrupt status */
> > unsigned int clk_src_div;
> > @@ -190,6 +244,7 @@ struct mtk_i2c {
> > enum mtk_trans_op op;
> > u16 timing_reg;
> > u16 high_speed_reg;
> > + u16 ltiming_reg;
> > unsigned char auto_restart;
> > bool ignore_restart_irq;
> > const struct mtk_i2c_compatible *dev_comp;
> > @@ -216,6 +271,7 @@ struct mtk_i2c {
> > .aux_len_reg = 1,
> > .support_33bits = 1,
> > .timing_adjust = 1,
> > + .dma_sync = 0,
> > };
> >
> > static const struct mtk_i2c_compatible mt6577_compat = {
> > @@ -227,6 +283,7 @@ struct mtk_i2c {
> > .aux_len_reg = 0,
> > .support_33bits = 0,
> > .timing_adjust = 0,
> > + .dma_sync = 0,
> > };
> >
> > static const struct mtk_i2c_compatible mt6589_compat = {
> > @@ -238,6 +295,7 @@ struct mtk_i2c {
> > .aux_len_reg = 0,
> > .support_33bits = 0,
> > .timing_adjust = 0,
> > + .dma_sync = 0,
> > };
> >
> > static const struct mtk_i2c_compatible mt7622_compat = {
> > @@ -249,6 +307,7 @@ struct mtk_i2c {
> > .aux_len_reg = 1,
> > .support_33bits = 0,
> > .timing_adjust = 0,
> > + .dma_sync = 0,
> > };
> >
> > static const struct mtk_i2c_compatible mt8173_compat = {
> > @@ -259,6 +318,18 @@ struct mtk_i2c {
> > .aux_len_reg = 1,
> > .support_33bits = 1,
> > .timing_adjust = 0,
> > + .dma_sync = 0,
> > +};
> > +
> > +static const struct mtk_i2c_compatible mt8183_compat = {
> > + .regs = mt_i2c_regs_v2,
> > + .pmic_i2c = 0,
> > + .dcm = 0,
> > + .auto_restart = 1,
> > + .aux_len_reg = 1,
> > + .support_33bits = 1,
> > + .timing_adjust = 1,
> > + .dma_sync = 1,
> > };
> >
> > static const struct of_device_id mtk_i2c_of_match[] = {
> > @@ -267,19 +338,20 @@ struct mtk_i2c {
> > { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
> > { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
> > { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
> > + { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
> > {}
> > };
> > MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
> >
> > static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg)
> > {
> > - return readw(i2c->base + i2c->dev_comp->regs[reg]);
> > + return readw(i2c->base + i2c->ch_offset + i2c->dev_comp->regs[reg]);
> > }
> >
> > static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val,
> > enum I2C_REGS_OFFSET reg)
> > {
> > - writew(val, i2c->base + i2c->dev_comp->regs[reg]);
> > + writew(val, i2c->base + i2c->ch_offset + i2c->dev_comp->regs[reg]);
> > }
> >
> > static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
> > @@ -299,8 +371,18 @@ static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
> > if (ret)
> > goto err_pmic;
> > }
> > +
> > + if (i2c->clk_arb) {
> > + ret = clk_prepare_enable(i2c->clk_arb);
> > + if (ret)
> > + goto err_arb;
> > + }
> > +
> > return 0;
> >
> > +err_arb:
> > + if (i2c->have_pmic)
> > + clk_disable_unprepare(i2c->clk_pmic);
> > err_pmic:
> > clk_disable_unprepare(i2c->clk_main);
> > err_main:
> > @@ -311,6 +393,9 @@ static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
> >
> > static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
> > {
> > + if (i2c->clk_arb)
> > + clk_disable_unprepare(i2c->clk_arb);
> > +
> > if (i2c->have_pmic)
> > clk_disable_unprepare(i2c->clk_pmic);
> >
> > @@ -333,11 +418,23 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
> > if (i2c->dev_comp->dcm)
> > mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN);
> >
> > - if (i2c->dev_comp->timing_adjust)
> > + if (i2c->ch_offset)
> > + writew(I2C_RESUME_ARBIT, i2c->base +
> > + i2c->dev_comp->regs[OFFSET_START]);
> > +
> > + if (i2c->dev_comp->timing_adjust && i2c->share_i3c) {
> > + mtk_i2c_writew(i2c, (I2C_DEFAULT_CLK_DIV - 1) |
> > + (I2C_DEFAULT_CLK_DIV - 1) << 8,
> > + OFFSET_CLOCK_DIV);
> > + i2c->high_speed_reg |= I2C_HS_TIME_EN;
> > + } else {
> > mtk_i2c_writew(i2c, I2C_DEFAULT_CLK_DIV - 1, OFFSET_CLOCK_DIV);
> > + }
> >
> > mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING);
> > mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS);
> > + if (i2c->dev_comp->regs == mt_i2c_regs_v2)
> > + mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING);
> >
> > /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
> > if (i2c->have_pmic)
> > @@ -345,6 +442,9 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
> >
> > control_reg = I2C_CONTROL_ACKERR_DET_EN |
> > I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
> > + if (i2c->dev_comp->dma_sync)
> > + control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE;
> > +
> > mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
> > mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN);
> >
> > @@ -434,6 +534,8 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
> > unsigned int clk_src;
> > unsigned int step_cnt;
> > unsigned int sample_cnt;
> > + unsigned int l_step_cnt;
> > + unsigned int l_sample_cnt;
> > unsigned int target_speed;
> > int ret;
> >
> > @@ -443,11 +545,11 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
> > if (target_speed > MAX_FS_MODE_SPEED) {
> > /* Set master code speed register */
> > ret = mtk_i2c_calculate_speed(i2c, clk_src, MAX_FS_MODE_SPEED,
> > - &step_cnt, &sample_cnt);
> > + &l_step_cnt, &l_sample_cnt);
> > if (ret < 0)
> > return ret;
> >
> > - i2c->timing_reg = (sample_cnt << 8) | step_cnt;
> > + i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
> >
> > /* Set the high speed mode register */
> > ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
> > @@ -457,6 +559,8 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
> >
> > i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
> > (sample_cnt << 12) | (step_cnt << 8);
> > + i2c->ltiming_reg = (l_sample_cnt << 6) | l_step_cnt |
> > + (sample_cnt << 12) | (step_cnt << 9);
> > } else {
> > ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
> > &step_cnt, &sample_cnt);
> > @@ -467,6 +571,8 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
> >
> > /* Disable the high speed transaction */
> > i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
> > +
> > + i2c->ltiming_reg = (sample_cnt << 6) | step_cnt;
> > }
> >
> > return 0;
> > @@ -483,6 +589,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> > u16 addr_reg;
> > u16 start_reg;
> > u16 control_reg;
> > + u16 fifo_clr_reg;
> > u16 restart_flag = 0;
> > u32 reg_4g_mode;
> > u8 *dma_rd_buf = NULL;
> > @@ -521,7 +628,15 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> > mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
> > I2C_TRANSAC_COMP, OFFSET_INTR_STAT);
> >
> > - mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR);
>
> There's a missing initialization to fifo_clr_reg here, I guess
> fifo_clr_reg = I2C_FIFO_ADDR_CLR should be necessarily made here;
>
> > + if (i2c->share_i3c)
> > + fifo_clr_reg = I2C_FIFO_ADDR_CLR | I2C_FIFO_ADDR_CLRH;
>
> fifo_clr_reg |= I2C_FIFO_ADDR_CLRH baed on initialized value
>
> > + if (i2c->ch_offset)
> > + fifo_clr_reg = I2C_FIFO_ADDR_CLR | I2C_FIFO_ADDR_CLR_MCH;
>
> and then fifo_clr_reg |= I2C_FIFO_ADDR_CLR_MCH;
>

ok, I will modify it. Thanks for your patient review.

> > +
> > + mtk_i2c_writew(i2c, fifo_clr_reg, OFFSET_FIFO_ADDR_CLR);
> > +
> > + if ((i2c->speed_hz > MAX_FS_MODE_SPEED) && i2c->share_i3c)
> > + mtk_i2c_writew(i2c, I2C_HFIFO_DATA, OFFSET_HFIFO_DATA);
> >
> > /* Enable interrupt */
> > mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
> > @@ -817,6 +932,11 @@ static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c)
> > if (i2c->clk_src_div == 0)
> > return -EINVAL;
> >
> > + ret = of_property_read_u32(np, "ch-offset", &i2c->ch_offset);
>
> if ch-offset is a vendor-specific property, it should be better to add
> a vendor prefix
>

ok, I will add a vendor-specific property if we need the ch-offset.

> > + if (ret < 0)
> > + i2c->ch_offset = 0;
> > +
> > + i2c->share_i3c = of_property_read_bool(np, "mediatek,share-i3c");
> > i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
> > i2c->use_push_pull =
> > of_property_read_bool(np, "mediatek,use-push-pull");
> > @@ -884,6 +1004,10 @@ static int mtk_i2c_probe(struct platform_device *pdev)
> > return PTR_ERR(i2c->clk_dma);
> > }
> >
> > + i2c->clk_arb = devm_clk_get(&pdev->dev, "arb");
> > + if (IS_ERR(i2c->clk_arb))
> > + i2c->clk_arb = NULL;
> > +
> > clk = i2c->clk_main;
> > if (i2c->have_pmic) {
> > i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
> > --
> > 1.7.9.5
> >
> >
> > _______________________________________________
> > Linux-mediatek mailing list
> > [email protected]
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek

2018-12-13 09:16:38

by Qii Wang (王琪)

Subject: Re: [PATCH 2/5] i2c: mediatek: remove useless code and replace definitions

On Tue, 2018-12-11 at 21:20 +0100, Wolfram Sang wrote:
> On Mon, Dec 03, 2018 at 09:32:51PM +0800, [email protected] wrote:
> > From: qii wang <[email protected]>
> >
> > Completion_done is useless when we don't use its return value,
> > so we remove it. Different speeds have been defined by macros,
> > so we use macros definitions.
>
> Those are two seperate patches, or?
>

These two changes are relatively small, but it seems better to be
divided into two seperate patches.

> >
> > Signed-off-by: qii wang <[email protected]>
> > ---
> > drivers/i2c/busses/i2c-mt65xx.c | 6 ++----
> > 1 file changed, 2 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
> > index a74ef76..660de1e 100644
> > --- a/drivers/i2c/busses/i2c-mt65xx.c
> > +++ b/drivers/i2c/busses/i2c-mt65xx.c
> > @@ -456,7 +456,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> >
> > control_reg = readw(i2c->base + OFFSET_CONTROL) &
> > ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
> > - if ((i2c->speed_hz > 400000) || (left_num >= 1))
> > + if ((i2c->speed_hz > MAX_FS_MODE_SPEED) || (left_num >= 1))
> > control_reg |= I2C_CONTROL_RS;
> >
> > if (i2c->op == I2C_MASTER_WRRD)
> > @@ -465,7 +465,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> > writew(control_reg, i2c->base + OFFSET_CONTROL);
> >
> > /* set start condition */
> > - if (i2c->speed_hz <= 100000)
> > + if (i2c->speed_hz <= I2C_DEFAULT_SPEED)
> > writew(I2C_ST_START_CON, i2c->base + OFFSET_EXT_CONF);
> > else
> > writew(I2C_FS_START_CON, i2c->base + OFFSET_EXT_CONF);
> > @@ -642,8 +642,6 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> > return -ETIMEDOUT;
> > }
> >
> > - completion_done(&i2c->msg_complete);
> > -
> > if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
> > dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
> > mtk_i2c_init_hw(i2c);
> > --
> > 1.7.9.5
> >

2018-12-13 09:33:54

by Qii Wang (王琪)

Subject: Re: [PATCH 4/5] dt-bindings: i2c: Add Mediatek MT8183 i2c binding

On Tue, 2018-12-11 at 21:29 +0100, Wolfram Sang wrote:
> > + - ch-offset: base reg offset for multi-user.
>
> What is "multi-user"? Why can't you add this offset to the reg-property
> directly?
>

Thanks for your comment.
There are 3 channel in one MT8183 I3C controller, and every channel can
be used as an I2C controller.
Take the following diagram as example:
If use I3C channels as I2C bus,
1. CH-A/B/C offset are different;
2. If use CH-B or CH-A as I2C, they must config registers which's
address are in CH-A.
____________________________________
| ________ |
| | |<--- offset:0x00 |
| | CH-A | |
| |________| |
| | |<--- offset:0x100 |
| | CH-B | |
| |________| |
| | |<--- offset:0x200 |
| | CH-C | |
| |________| |
|____________________________________|
one I3C controller

Because of CH-B/CH-C depend on CH-A's register, it can't add offset to
reg-property directly.

MT8183 doesn't need to support muti-user according to the latest project
information, and I'll remove this feature from patches.

> > + - mediatek,share-i3c: i3c controller can share i2c function.
>
> Please explain in more detail? Is this an I3C controller?
>

Yes, it is a i3c controller, and it is compatible with i2c. I only use
the feature of i2c, so I need a flag to do some extra settings.

2018-12-17 23:27:32

by Wolfram Sang

Subject: Re: [PATCH 4/5] dt-bindings: i2c: Add Mediatek MT8183 i2c binding

> > What is "multi-user"? Why can't you add this offset to the reg-property
> > directly?

...

> MT8183 doesn't need to support muti-user according to the latest project
> information, and I'll remove this feature from patches.

Okay. It will be dropped then, thanks for the heads up!

> > > + - mediatek,share-i3c: i3c controller can share i2c function.
> >
> > Please explain in more detail? Is this an I3C controller?
>
> Yes, it is a i3c controller, and it is compatible with i2c. I only use
> the feature of i2c, so I need a flag to do some extra settings.

Can't you derive this from the compatible? If it is
"mediatek,mt8183-i2c", then you know you need these extra settings?

Attachments:

2018-12-18 02:36:40

by Qii Wang (王琪)

Subject: Re: [PATCH 4/5] dt-bindings: i2c: Add Mediatek MT8183 i2c binding

On Tue, 2018-12-18 at 00:06 +0100, Wolfram Sang wrote:
> > > What is "multi-user"? Why can't you add this offset to the reg-property
> > > directly?
>
> ...
>
> > MT8183 doesn't need to support muti-user according to the latest project
> > information, and I'll remove this feature from patches.
>
> Okay. It will be dropped then, thanks for the heads up!
>
> > > > + - mediatek,share-i3c: i3c controller can share i2c function.
> > >
> > > Please explain in more detail? Is this an I3C controller?
> >
> > Yes, it is a i3c controller, and it is compatible with i2c. I only use
> > the feature of i2c, so I need a flag to do some extra settings.
>
> Can't you derive this from the compatible? If it is
> "mediatek,mt8183-i2c", then you know you need these extra settings?
>

Not all channels are i3c controllers in MT8183. only i3c controller need
some extra settings.