2019-01-09 08:25:15

by Seiya Wang

Subject: [PATCH v1 1/1] arm64: dts: mt8173: add pmu nodes for mt8173

This patch adds the device nodes of ARM Performance Monitor Uint
for mt8173.

Signed-off-by: Seiya Wang <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 412ffd4d426b..44374c506a1c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -216,6 +216,20 @@
};
};

+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ };
+
+ pmu_a72 {
+ compatible = "arm,cortex-a72-pmu";
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-affinity = <&cpu2>, <&cpu3>;
+ };
+
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
method = "smc";
--
2.14.1

2019-02-08 15:07:19

by Matthias Brugger

Subject: Re: [PATCH v1 1/1] arm64: dts: mt8173: add pmu nodes for mt8173

On 09/01/2019 09:21, Seiya Wang wrote:
> This patch adds the device nodes of ARM Performance Monitor Uint
> for mt8173.
>
> Signed-off-by: Seiya Wang <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 412ffd4d426b..44374c506a1c 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -216,6 +216,20 @@
> };
> };
>
> + pmu_a53 {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-affinity = <&cpu0>, <&cpu1>;
> + };
> +
> + pmu_a72 {
> + compatible = "arm,cortex-a72-pmu";
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-affinity = <&cpu2>, <&cpu3>;
> + };

There is no a72 but a a57 CPU present.
Typo?

Regards,
Matthias

> +
> psci {
> compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
> method = "smc";
>

2019-02-11 05:22:44

by Seiya Wang

Subject: Re: [PATCH v1 1/1] arm64: dts: mt8173: add pmu nodes for mt8173

On Fri, 2019-02-08 at 16:04 +0100, Matthias Brugger wrote:
>
> On 09/01/2019 09:21, Seiya Wang wrote:
> > This patch adds the device nodes of ARM Performance Monitor Uint
> > for mt8173.
> >
> > Signed-off-by: Seiya Wang <[email protected]>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 14 ++++++++++++++
> > 1 file changed, 14 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index 412ffd4d426b..44374c506a1c 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -216,6 +216,20 @@
> > };
> > };
> >
> > + pmu_a53 {
> > + compatible = "arm,cortex-a53-pmu";
> > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
> > + interrupt-affinity = <&cpu0>, <&cpu1>;
> > + };
> > +
> > + pmu_a72 {
> > + compatible = "arm,cortex-a72-pmu";
> > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>;
> > + interrupt-affinity = <&cpu2>, <&cpu3>;
> > + };
>
> There is no a72 but a a57 CPU present.
> Typo?
>
> Regards,
> Matthias

MT8173 is actually using a72, not a57.
I will submit another patch for fixing it.

Thanks.

> > +
> > psci {
> > compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
> > method = "smc";
> >

2019-04-16 08:38:07

by Seiya Wang

Subject: Re: [PATCH v1 1/1] arm64: dts: mt8173: add pmu nodes for mt8173

On Fri, 2019-02-08 at 16:04 +0100, Matthias Brugger wrote:
>
> On 09/01/2019 09:21, Seiya Wang wrote:
> > This patch adds the device nodes of ARM Performance Monitor Uint
> > for mt8173.
> >
> > Signed-off-by: Seiya Wang <[email protected]>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 14 ++++++++++++++
> > 1 file changed, 14 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index 412ffd4d426b..44374c506a1c 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -216,6 +216,20 @@
> > };
> > };
> >
> > + pmu_a53 {
> > + compatible = "arm,cortex-a53-pmu";
> > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
> > + interrupt-affinity = <&cpu0>, <&cpu1>;
> > + };
> > +
> > + pmu_a72 {
> > + compatible = "arm,cortex-a72-pmu";
> > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>;
> > + interrupt-affinity = <&cpu2>, <&cpu3>;
> > + };
>
> There is no a72 but a a57 CPU present.
> Typo?
>
> Regards,
> Matthias

Please also apply this (if no problems) since we have changed to ca72.
Thanks.

> > +
> > psci {
> > compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
> > method = "smc";
> >

2019-04-16 08:58:31

by Matthias Brugger

Subject: Re: [PATCH v1 1/1] arm64: dts: mt8173: add pmu nodes for mt8173

On 16/04/2019 10:35, Seiya Wang wrote:
> On Fri, 2019-02-08 at 16:04 +0100, Matthias Brugger wrote:
>>
>> On 09/01/2019 09:21, Seiya Wang wrote:
>>> This patch adds the device nodes of ARM Performance Monitor Uint
>>> for mt8173.
>>>
>>> Signed-off-by: Seiya Wang <[email protected]>
>>> ---
>>> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 14 ++++++++++++++
>>> 1 file changed, 14 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>>> index 412ffd4d426b..44374c506a1c 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>>> @@ -216,6 +216,20 @@
>>> };
>>> };
>>>
>>> + pmu_a53 {
>>> + compatible = "arm,cortex-a53-pmu";
>>> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
>>> + <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
>>> + interrupt-affinity = <&cpu0>, <&cpu1>;
>>> + };
>>> +
>>> + pmu_a72 {
>>> + compatible = "arm,cortex-a72-pmu";
>>> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>,
>>> + <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>;
>>> + interrupt-affinity = <&cpu2>, <&cpu3>;
>>> + };
>>
>> There is no a72 but a a57 CPU present.
>> Typo?
>>
>> Regards,
>> Matthias
>
> Please also apply this (if no problems) since we have changed to ca72.
> Thanks.
>

Pushed now to v5.1-next/dts64

Thanks for the heads up :)