From: Thor Thayer <[email protected]>
Newer versions (V2) of Altera/Intel FPGAs CvP have different PCI
Vendor Specific Capability offsets than the older (V1) Altera/FPGAs.
Most of the CvP registers and their bitfields remain the same
between both the older parts and the newer parts.
This patchset implements changes to discover the Vendor Specific
Capability offset and then add Stratix10 CvP support.
V2 Changes:
Remove inline designator from abstraction functions.
Reverse Christmas Tree format for local variables
Remove redundant mask from credit calculation
Add commment for the delay(1) function in wait_for_credit()
V3 Changes
Return int instead of void for abstraction functions
Check the return code from read in altera_cvp_chk_error()
Move reset of current_credit_byte to clear_state().
Check return codes of read/writes in added functions.
Thor Thayer (3):
fpga: altera-cvp: Discover Vendor Specific offset
fpga: altera-cvp: Preparation for V2 parts.
fpga: altera-cvp: Add Stratix10 (V2) Support
drivers/fpga/altera-cvp.c | 348 ++++++++++++++++++++++++++++++++++++----------
1 file changed, 277 insertions(+), 71 deletions(-)
--
2.7.4
From: Thor Thayer <[email protected]>
In preparation for adding newer V2 parts that use a FIFO,
reorganize altera_cvp_chk_error() and change the write
function to block based.
V2 parts have a block size matching the FIFO while older
V1 parts write a 32 bit word at a time.
Signed-off-by: Thor Thayer <[email protected]>
---
v2 Remove inline function declaration
Reverse Christmas Tree format for local variables
v3 Add return code check in altera_cvp_chk_error()
---
drivers/fpga/altera-cvp.c | 73 ++++++++++++++++++++++++++++++-----------------
1 file changed, 47 insertions(+), 26 deletions(-)
diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c
index 3297613722c3..b08c0fd353ba 100644
--- a/drivers/fpga/altera-cvp.c
+++ b/drivers/fpga/altera-cvp.c
@@ -142,6 +142,42 @@ static int altera_cvp_wait_status(struct altera_cvp_conf *conf, u32 status_mask,
return -ETIMEDOUT;
}
+static int altera_cvp_chk_error(struct fpga_manager *mgr, size_t bytes)
+{
+ struct altera_cvp_conf *conf = mgr->priv;
+ u32 val;
+ int ret;
+
+ /* STEP 10 (optional) - check CVP_CONFIG_ERROR flag */
+ ret = altera_read_config_dword(conf, VSE_CVP_STATUS, &val);
+ if (ret || (val & VSE_CVP_STATUS_CFG_ERR)) {
+ dev_err(&mgr->dev, "CVP_CONFIG_ERROR after %zu bytes!\n",
+ bytes);
+ return -EPROTO;
+ }
+ return 0;
+}
+
+static int altera_cvp_send_block(struct altera_cvp_conf *conf,
+ const u32 *data, size_t len)
+{
+ u32 mask, words = len / sizeof(u32);
+ int i, remainder;
+
+ for (i = 0; i < words; i++)
+ conf->write_data(conf, *data++);
+
+ /* write up to 3 trailing bytes, if any */
+ remainder = len % sizeof(u32);
+ if (remainder) {
+ mask = BIT(remainder * 8) - 1;
+ if (mask)
+ conf->write_data(conf, *data & mask);
+ }
+
+ return 0;
+}
+
static int altera_cvp_teardown(struct fpga_manager *mgr,
struct fpga_image_info *info)
{
@@ -264,39 +300,29 @@ static int altera_cvp_write_init(struct fpga_manager *mgr,
return 0;
}
-static inline int altera_cvp_chk_error(struct fpga_manager *mgr, size_t bytes)
-{
- struct altera_cvp_conf *conf = mgr->priv;
- u32 val;
-
- /* STEP 10 (optional) - check CVP_CONFIG_ERROR flag */
- altera_read_config_dword(conf, VSE_CVP_STATUS, &val);
- if (val & VSE_CVP_STATUS_CFG_ERR) {
- dev_err(&mgr->dev, "CVP_CONFIG_ERROR after %zu bytes!\n",
- bytes);
- return -EPROTO;
- }
- return 0;
-}
-
static int altera_cvp_write(struct fpga_manager *mgr, const char *buf,
size_t count)
{
struct altera_cvp_conf *conf = mgr->priv;
+ size_t done, remaining, len;
const u32 *data;
- size_t done, remaining;
int status = 0;
- u32 mask;
/* STEP 9 - write 32-bit data from RBF file to CVP data register */
data = (u32 *)buf;
remaining = count;
done = 0;
- while (remaining >= 4) {
- conf->write_data(conf, *data++);
- done += 4;
- remaining -= 4;
+ while (remaining) {
+ if (remaining >= sizeof(u32))
+ len = sizeof(u32);
+ else
+ len = remaining;
+
+ altera_cvp_send_block(conf, data, len);
+ data++;
+ done += len;
+ remaining -= len;
/*
* STEP 10 (optional) and STEP 11
@@ -314,11 +340,6 @@ static int altera_cvp_write(struct fpga_manager *mgr, const char *buf,
}
}
- /* write up to 3 trailing bytes, if any */
- mask = BIT(remaining * 8) - 1;
- if (mask)
- conf->write_data(conf, *data & mask);
-
if (altera_cvp_chkcfg)
status = altera_cvp_chk_error(mgr, count);
--
2.7.4
Hi Thor,
On Thu, Jul 25, 2019 at 10:16:45AM -0500, [email protected] wrote:
> From: Thor Thayer <[email protected]>
>
> Newer versions (V2) of Altera/Intel FPGAs CvP have different PCI
> Vendor Specific Capability offsets than the older (V1) Altera/FPGAs.
>
> Most of the CvP registers and their bitfields remain the same
> between both the older parts and the newer parts.
>
> This patchset implements changes to discover the Vendor Specific
> Capability offset and then add Stratix10 CvP support.
>
> V2 Changes:
> Remove inline designator from abstraction functions.
> Reverse Christmas Tree format for local variables
> Remove redundant mask from credit calculation
> Add commment for the delay(1) function in wait_for_credit()
>
> V3 Changes
> Return int instead of void for abstraction functions
> Check the return code from read in altera_cvp_chk_error()
> Move reset of current_credit_byte to clear_state().
> Check return codes of read/writes in added functions.
>
> Thor Thayer (3):
> fpga: altera-cvp: Discover Vendor Specific offset
> fpga: altera-cvp: Preparation for V2 parts.
> fpga: altera-cvp: Add Stratix10 (V2) Support
>
> drivers/fpga/altera-cvp.c | 348 ++++++++++++++++++++++++++++++++++++----------
> 1 file changed, 277 insertions(+), 71 deletions(-)
>
> --
> 2.7.4
>
this doesn't apply since I applied Carlos' patch 998c1de56dac7
("fpga: altera-cvp: Fix function definition argument") yesterday to
git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga.git
'for-next' branch.
Would you mind resending it on top of that and drop the extra dev_dbg()
for the offset in Patch [1/3]?
Sorry about that. Things are moving around a bit, but hopefully settle
down soon :)
- Moritz