From: Peng Fan <[email protected]>
V2:
update commit message to reflect the change
Merged sccg/composite-8m into one patchset
This patchset is insipred from Will Deacon's slide/video:
https://elinux.org/images/a/a8/Uh-oh-Its-IO-Ordering-Will-Deacon-Arm.pdf
https://www.youtube.com/watch?v=i6DayghhA8Q
Peng Fan (4):
clk: imx: pll14xx: use writel_relaxed
clk: imx: pll14xx: use readl to force write completed
clk: imx: sccg: use relaxed io api
clk: imx: composite-8m: use relaxed io api
drivers/clk/imx/clk-composite-8m.c | 8 ++++----
drivers/clk/imx/clk-pll14xx.c | 8 +++++++-
drivers/clk/imx/clk-sccg-pll.c | 17 +++++++++--------
3 files changed, 20 insertions(+), 13 deletions(-)
--
2.16.4
From: Peng Fan <[email protected]>
writel has a barrier, however that barrier is not needed,
because device memory mapping is nGnRE mapping and access is
in order and clk driver has spin lock or other lock to make
sure write finished.
Cc: Will Deacon <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
---
drivers/clk/imx/clk-pll14xx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
index 5778f3bfb339..5b7d41d43b3b 100644
--- a/drivers/clk/imx/clk-pll14xx.c
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -199,7 +199,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
/* Enable BYPASS */
tmp |= BYPASS_MASK;
- writel(tmp, pll->base);
+ writel_relaxed(tmp, pll->base);
div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
(rate->sdiv << SDIV_SHIFT);
--
2.16.4
From: Peng Fan <[email protected]>
To ensure writes to clock registers have properly completed,
add a readl after writel_relaxed. Then we could make sure
when udelay, write has been completed.
Signed-off-by: Peng Fan <[email protected]>
Cc: Will Deacon <[email protected]>
---
drivers/clk/imx/clk-pll14xx.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
index 5b7d41d43b3b..a8af949f0848 100644
--- a/drivers/clk/imx/clk-pll14xx.c
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -205,6 +205,12 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
(rate->sdiv << SDIV_SHIFT);
writel_relaxed(div_val, pll->base + 0x4);
+ /*
+ * readl will force write completed. There is a udelay below,
+ * we need make sure before udelay, write has been completed
+ */
+ readl(pll->base + 0x4);
+
/*
* According to SPEC, t3 - t2 need to be greater than
* 1us and 1/FREF, respectively.
--
2.16.4
From: Peng Fan <[email protected]>
writel/readl has a barrier, however that barrier is not needed,
because device memory mapping is nGnRE mapping and access is
in order and clk driver has spin lock or other lock to make
sure write finished. It is ok to use relaxed api here, no need
to use stronger readl/writel
Signed-off-by: Peng Fan <[email protected]>
---
drivers/clk/imx/clk-sccg-pll.c | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c
index 2cf874813458..e03f8acb1e82 100644
--- a/drivers/clk/imx/clk-sccg-pll.c
+++ b/drivers/clk/imx/clk-sccg-pll.c
@@ -106,8 +106,9 @@ static int clk_sccg_pll_wait_lock(struct clk_sccg_pll *pll)
/* don't wait for lock if all plls are bypassed */
if (!(val & SSCG_PLL_BYPASS2_MASK))
- return readl_poll_timeout(pll->base, val, val & PLL_LOCK_MASK,
- 0, PLL_SCCG_LOCK_TIMEOUT);
+ return readl_relaxed_poll_timeout(pll->base, val,
+ val & PLL_LOCK_MASK,
+ 0, PLL_SCCG_LOCK_TIMEOUT);
return 0;
}
@@ -349,7 +350,7 @@ static unsigned long clk_sccg_pll_recalc_rate(struct clk_hw *hw,
temp64 = parent_rate;
- val = readl(pll->base + PLL_CFG0);
+ val = readl_relaxed(pll->base + PLL_CFG0);
if (val & SSCG_PLL_BYPASS2_MASK) {
temp64 = parent_rate;
} else if (val & SSCG_PLL_BYPASS1_MASK) {
@@ -372,10 +373,10 @@ static int clk_sccg_pll_set_rate(struct clk_hw *hw, unsigned long rate,
u32 val;
/* set bypass here too since the parent might be the same */
- val = readl(pll->base + PLL_CFG0);
+ val = readl_relaxed(pll->base + PLL_CFG0);
val &= ~SSCG_PLL_BYPASS_MASK;
val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, setup->bypass);
- writel(val, pll->base + PLL_CFG0);
+ writel_relaxed(val, pll->base + PLL_CFG0);
val = readl_relaxed(pll->base + PLL_CFG2);
val &= ~(PLL_DIVF1_MASK | PLL_DIVF2_MASK);
@@ -396,7 +397,7 @@ static u8 clk_sccg_pll_get_parent(struct clk_hw *hw)
u32 val;
u8 ret = pll->parent;
- val = readl(pll->base + PLL_CFG0);
+ val = readl_relaxed(pll->base + PLL_CFG0);
if (val & SSCG_PLL_BYPASS2_MASK)
ret = pll->bypass2;
else if (val & SSCG_PLL_BYPASS1_MASK)
@@ -409,10 +410,10 @@ static int clk_sccg_pll_set_parent(struct clk_hw *hw, u8 index)
struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
u32 val;
- val = readl(pll->base + PLL_CFG0);
+ val = readl_relaxed(pll->base + PLL_CFG0);
val &= ~SSCG_PLL_BYPASS_MASK;
val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass);
- writel(val, pll->base + PLL_CFG0);
+ writel_relaxed(val, pll->base + PLL_CFG0);
return clk_sccg_pll_wait_lock(pll);
}
--
2.16.4
From: Peng Fan <[email protected]>
writel/readl has a barrier, however that barrier is not needed,
because device memory mapping is nGnRE mapping and access is
in order and clk driver has spin lock or other lock to make
sure write finished. It is ok to use relaxed api here, no need
to use stronger readl/writel
Signed-off-by: Peng Fan <[email protected]>
---
drivers/clk/imx/clk-composite-8m.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index 20f7c91c03d2..513dc57483d0 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -31,14 +31,14 @@ static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw *hw,
unsigned int prediv_value;
unsigned int div_value;
- prediv_value = readl(divider->reg) >> divider->shift;
+ prediv_value = readl_relaxed(divider->reg) >> divider->shift;
prediv_value &= clk_div_mask(divider->width);
prediv_rate = divider_recalc_rate(hw, parent_rate, prediv_value,
NULL, divider->flags,
divider->width);
- div_value = readl(divider->reg) >> PCG_DIV_SHIFT;
+ div_value = readl_relaxed(divider->reg) >> PCG_DIV_SHIFT;
div_value &= clk_div_mask(PCG_DIV_WIDTH);
return divider_recalc_rate(hw, prediv_rate, div_value, NULL,
@@ -104,13 +104,13 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw,
spin_lock_irqsave(divider->lock, flags);
- val = readl(divider->reg);
+ val = readl_relaxed(divider->reg);
val &= ~((clk_div_mask(divider->width) << divider->shift) |
(clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
val |= (u32)(prediv_value - 1) << divider->shift;
val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
- writel(val, divider->reg);
+ writel_relaxed(val, divider->reg);
spin_unlock_irqrestore(divider->lock, flags);
--
2.16.4
> Subject: [PATCH V2 0/4] clk: imx: pll14/sccg use relaxed API
Any comments?
Thanks,
Peng.
>
> From: Peng Fan <[email protected]>
>
> V2:
> update commit message to reflect the change Merged sccg/composite-8m
> into one patchset
>
> This patchset is insipred from Will Deacon's slide/video:
> https://elinux.org/images/a/a8/Uh-oh-Its-IO-Ordering-Will-Deacon-Arm.pdf
> https://www.youtube.com/watch?v=i6DayghhA8Q
>
> Peng Fan (4):
> clk: imx: pll14xx: use writel_relaxed
> clk: imx: pll14xx: use readl to force write completed
> clk: imx: sccg: use relaxed io api
> clk: imx: composite-8m: use relaxed io api
>
> drivers/clk/imx/clk-composite-8m.c | 8 ++++----
> drivers/clk/imx/clk-pll14xx.c | 8 +++++++-
> drivers/clk/imx/clk-sccg-pll.c | 17 +++++++++--------
> 3 files changed, 20 insertions(+), 13 deletions(-)
>
> --
> 2.16.4