Hi Michael,
On 22/11/2019 10:06, [email protected] wrote:
> From: "michael.kao" <[email protected]>
>
> This device node is for calculating dynamic power in mW.
> Since mt8173 has two clusters, there are two dynamic power
> coefficient as well.
Are you sure about the values? Usually, Big is ~x4 little, here it is ~x2.
> Signed-off-by: Dawei Chien <[email protected]>
> Signed-off-by: Michael.Kao <[email protected]>
>
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 15f1842f6df3..b03ca5a71338 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -157,6 +157,7 @@
> enable-method = "psci";
> cpu-idle-states = <&CPU_SLEEP_0>;
> #cooling-cells = <2>;
> + dynamic-power-coefficient = <263>;
> clocks = <&infracfg CLK_INFRA_CA53SEL>,
> <&apmixedsys CLK_APMIXED_MAINPLL>;
> clock-names = "cpu", "intermediate";
> @@ -170,6 +171,7 @@
> enable-method = "psci";
> cpu-idle-states = <&CPU_SLEEP_0>;
> #cooling-cells = <2>;
> + dynamic-power-coefficient = <263>;
> clocks = <&infracfg CLK_INFRA_CA53SEL>,
> <&apmixedsys CLK_APMIXED_MAINPLL>;
> clock-names = "cpu", "intermediate";
> @@ -183,6 +185,7 @@
> enable-method = "psci";
> cpu-idle-states = <&CPU_SLEEP_0>;
> #cooling-cells = <2>;
> + dynamic-power-coefficient = <530>;
> clocks = <&infracfg CLK_INFRA_CA72SEL>,
> <&apmixedsys CLK_APMIXED_MAINPLL>;
> clock-names = "cpu", "intermediate";
> @@ -196,6 +199,7 @@
> enable-method = "psci";
> cpu-idle-states = <&CPU_SLEEP_0>;
> #cooling-cells = <2>;
> + dynamic-power-coefficient = <530>;
> clocks = <&infracfg CLK_INFRA_CA72SEL>,
> <&apmixedsys CLK_APMIXED_MAINPLL>;
> clock-names = "cpu", "intermediate";
>
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On Thu, 2019-12-05 at 17:00 +0100, Daniel Lezcano wrote:
> Hi Michael,
>
>
> On 22/11/2019 10:06, [email protected] wrote:
> > From: "michael.kao" <[email protected]>
> >
> > This device node is for calculating dynamic power in mW.
> > Since mt8173 has two clusters, there are two dynamic power
> > coefficient as well.
>
> Are you sure about the values? Usually, Big is ~x4 little, here it is ~x2.
Hi Daniel,
I have confirmed again with our IC designer.
The dynamic power coefficients are these value is right.
Designer comment that it is result from different IC implement.
>
> > Signed-off-by: Dawei Chien <[email protected]>
> > Signed-off-by: Michael.Kao <[email protected]>
> >
> > ---
> > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index 15f1842f6df3..b03ca5a71338 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -157,6 +157,7 @@
> > enable-method = "psci";
> > cpu-idle-states = <&CPU_SLEEP_0>;
> > #cooling-cells = <2>;
> > + dynamic-power-coefficient = <263>;
> > clocks = <&infracfg CLK_INFRA_CA53SEL>,
> > <&apmixedsys CLK_APMIXED_MAINPLL>;
> > clock-names = "cpu", "intermediate";
> > @@ -170,6 +171,7 @@
> > enable-method = "psci";
> > cpu-idle-states = <&CPU_SLEEP_0>;
> > #cooling-cells = <2>;
> > + dynamic-power-coefficient = <263>;
> > clocks = <&infracfg CLK_INFRA_CA53SEL>,
> > <&apmixedsys CLK_APMIXED_MAINPLL>;
> > clock-names = "cpu", "intermediate";
> > @@ -183,6 +185,7 @@
> > enable-method = "psci";
> > cpu-idle-states = <&CPU_SLEEP_0>;
> > #cooling-cells = <2>;
> > + dynamic-power-coefficient = <530>;
> > clocks = <&infracfg CLK_INFRA_CA72SEL>,
> > <&apmixedsys CLK_APMIXED_MAINPLL>;
> > clock-names = "cpu", "intermediate";
> > @@ -196,6 +199,7 @@
> > enable-method = "psci";
> > cpu-idle-states = <&CPU_SLEEP_0>;
> > #cooling-cells = <2>;
> > + dynamic-power-coefficient = <530>;
> > clocks = <&infracfg CLK_INFRA_CA72SEL>,
> > <&apmixedsys CLK_APMIXED_MAINPLL>;
> > clock-names = "cpu", "intermediate";
> >
>
>
On 11/12/2019 09:13, Michael Kao wrote:
> On Thu, 2019-12-05 at 17:00 +0100, Daniel Lezcano wrote:
>> Hi Michael,
>>
>>
>> On 22/11/2019 10:06, [email protected] wrote:
>>> From: "michael.kao" <[email protected]>
>>>
>>> This device node is for calculating dynamic power in mW.
>>> Since mt8173 has two clusters, there are two dynamic power
>>> coefficient as well.
>>
>> Are you sure about the values? Usually, Big is ~x4 little, here it is ~x2.
>
> Hi Daniel,
>
> I have confirmed again with our IC designer.
> The dynamic power coefficients are these value is right.
> Designer comment that it is result from different IC implement.
Applied to v5.5-next/dts64
Thanks!
Matthias
>>
>>> Signed-off-by: Dawei Chien <[email protected]>
>>> Signed-off-by: Michael.Kao <[email protected]>
>>>
>>> ---
>>> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 4 ++++
>>> 1 file changed, 4 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>>> index 15f1842f6df3..b03ca5a71338 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>>> @@ -157,6 +157,7 @@
>>> enable-method = "psci";
>>> cpu-idle-states = <&CPU_SLEEP_0>;
>>> #cooling-cells = <2>;
>>> + dynamic-power-coefficient = <263>;
>>> clocks = <&infracfg CLK_INFRA_CA53SEL>,
>>> <&apmixedsys CLK_APMIXED_MAINPLL>;
>>> clock-names = "cpu", "intermediate";
>>> @@ -170,6 +171,7 @@
>>> enable-method = "psci";
>>> cpu-idle-states = <&CPU_SLEEP_0>;
>>> #cooling-cells = <2>;
>>> + dynamic-power-coefficient = <263>;
>>> clocks = <&infracfg CLK_INFRA_CA53SEL>,
>>> <&apmixedsys CLK_APMIXED_MAINPLL>;
>>> clock-names = "cpu", "intermediate";
>>> @@ -183,6 +185,7 @@
>>> enable-method = "psci";
>>> cpu-idle-states = <&CPU_SLEEP_0>;
>>> #cooling-cells = <2>;
>>> + dynamic-power-coefficient = <530>;
>>> clocks = <&infracfg CLK_INFRA_CA72SEL>,
>>> <&apmixedsys CLK_APMIXED_MAINPLL>;
>>> clock-names = "cpu", "intermediate";
>>> @@ -196,6 +199,7 @@
>>> enable-method = "psci";
>>> cpu-idle-states = <&CPU_SLEEP_0>;
>>> #cooling-cells = <2>;
>>> + dynamic-power-coefficient = <530>;
>>> clocks = <&infracfg CLK_INFRA_CA72SEL>,
>>> <&apmixedsys CLK_APMIXED_MAINPLL>;
>>> clock-names = "cpu", "intermediate";
>>>
>>
>>
>