2020-01-07 21:06:42

by Elliot Berman

[permalink] [raw]
Subject: [PATCH v5 00/17] Restructure, improve target support for qcom_scm driver

This series improves support for 32-bit Qualcomm targets on qcom_scm driver and cleans
up the driver for 64-bit implementations.

Currently, the qcom_scm driver supports only 64-bit Qualcomm targets and very
old 32-bit Qualcomm targets. Newer 32-bit targets use ARM's SMC Calling
Convention to communicate with secure world. Older 32-bit targets use a
"buffer-based" legacy approach for communicating with secure world (as
implemented in qcom_scm-32.c). All arm64 Qualcomm targets use ARM SMCCC.
Currently, SMCCC-based communication is enabled only on ARM64 config and
buffer-based communication only on ARM config. This patch-series combines SMCCC
and legacy conventions and selects the correct convention by querying the secure
world [1].

We decided to take the opportunity as well to clean up the driver rather than
try to patch together qcom_scm-32 and qcom_scm-64.

Patches 1-3 and 15 improve macro names, reorder macros/functions, and prune unused
macros/functions. No functional changes were introduced.
Patches 4-8 clears up the SCM abstraction in qcom_scm-64.
Patches 9-14 clears up the SCM abstraction in qcom_scm-32.
Patches 16-17 enable dynamically using the different calling conventions.

[1]: https://source.codeaurora.org/quic/la/kernel/msm-4.9/tree/drivers/soc/qcom/scm.c?h=kernel.lnx.4.9.r28-rel#n555

Changes since v4:
- Restored missing arginfo/args to pas_auth_and_reset

Changes since v3:
- Updated recepients

Changes since v2:
- Addressed Stephen's comments throughout v2.
- Rebased onto latest for-next branch
- Removed v2 08/18 (firmware: qcom_scm-64: Remove qcom_scm_call_do_smccc)
- Cleaned up the convention query from v2 to align with [1].

Changes since v1:
- Renamed functions/variables per Vinod's suggestions
- Split v1 01/17 into v2 [01,02,03]/18 per Vinod's suggestion
- Fix suggestions by Bjorn in v1 09/18 (now v2 10/18)
- Refactor last 3 commits per Bjorn suggestions in v1 17/18 and v1 10/18

Changes since RFC:
- Fixed missing return values in qcom_scm_call_smccc
- Fixed order of arguments in qcom_scm_set_warm_boot_addr
- Adjusted logic of SMC convention to properly support older QCOM secure worlds
- Boot tested on IFC6410 based on linaro kernel tag:
debian-qcom-dragonboard410c-18.01 (which does basic verification of legacy
SCM calls: at least warm_boot_addr, cold_boot_addr, and power_down)

Elliot Berman (17):
firmware: qcom_scm: Rename macros and structures
firmware: qcom_scm: Apply consistent naming scheme to command IDs
firmware: qcom_scm: Remove unused qcom_scm_get_version
firmware: qcom_scm-64: Make SMC macros less magical
firmware: qcom_scm-64: Move svc/cmd/owner into qcom_scm_desc
firmware: qcom_scm-64: Add SCM results struct
firmware: qcom_scm-64: Move SMC register filling to
qcom_scm_call_smccc
firmware: qcom_scm-64: Improve SMC convention detection
firmware: qcom_scm-32: Use SMC arch wrappers
firmware: qcom_scm-32: Add funcnum IDs
firmware: qcom_scm-32: Use qcom_scm_desc in non-atomic calls
firmware: qcom_scm-32: Move SMCCC register filling to qcom_scm_call
firmware: qcom_scm-32: Create common legacy atomic call
firmware: qcom_scm-32: Add device argument to atomic calls
firmware: qcom_scm: Order functions, definitions by service/command
firmware: qcom_scm: Remove thin wrappers
firmware: qcom_scm: Dynamically support SMCCC and legacy conventions

drivers/firmware/Kconfig | 8 -
drivers/firmware/Makefile | 5 +-
drivers/firmware/qcom_scm-32.c | 671 -----------------------------
drivers/firmware/qcom_scm-64.c | 579 -------------------------
drivers/firmware/qcom_scm-legacy.c | 242 +++++++++++
drivers/firmware/qcom_scm-smc.c | 151 +++++++
drivers/firmware/qcom_scm.c | 854 +++++++++++++++++++++++++++++--------
drivers/firmware/qcom_scm.h | 178 ++++----
include/linux/qcom_scm.h | 125 +++---
9 files changed, 1232 insertions(+), 1581 deletions(-)
delete mode 100644 drivers/firmware/qcom_scm-32.c
delete mode 100644 drivers/firmware/qcom_scm-64.c
create mode 100644 drivers/firmware/qcom_scm-legacy.c
create mode 100644 drivers/firmware/qcom_scm-smc.c

--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


2020-01-07 21:06:50

by Elliot Berman

[permalink] [raw]
Subject: [PATCH v5 12/17] firmware: qcom_scm-32: Move SMCCC register filling to qcom_scm_call

Move SMCCC register filling to qcom_scm_call so that __scm_legacy_do
only needs to concern itself with retry mechanism. qcom_scm_call then is
responsible for translating qcom_scm_desc into the complete set of
register arguments and passing onto qcom_scm_call_do.

Change-Id: I435d974724118943084f618f63fffb1109d1cfe0
Tested-by: Brian Masney <[email protected]> # arm32
Tested-by: Stephan Gerhold <[email protected]>
Signed-off-by: Elliot Berman <[email protected]>
---
drivers/firmware/qcom_scm-32.c | 36 ++++++++++++++++++++++++------------
1 file changed, 24 insertions(+), 12 deletions(-)

diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c
index ce3a61b..acd956f 100644
--- a/drivers/firmware/qcom_scm-32.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -85,6 +85,14 @@ struct qcom_scm_res {
u64 result[MAX_QCOM_SCM_RETS];
};

+/**
+ * struct arm_smccc_args
+ * @args: The array of values used in registers in smc instruction
+ */
+struct arm_smccc_args {
+ unsigned long args[8];
+};
+
#define SCM_LEGACY_FNID(s, c) (((s) << 10) | ((c) & 0x3ff))

/**
@@ -167,16 +175,14 @@ static inline void *scm_legacy_get_response_buffer(
return (void *)rsp + le32_to_cpu(rsp->buf_offset);
}

-static u32 __scm_legacy_do(u32 cmd_addr)
+static void __scm_legacy_do(const struct arm_smccc_args *smc,
+ struct arm_smccc_res *res)
{
- int context_id;
- struct arm_smccc_res res;
do {
- arm_smccc_smc(1, (unsigned long)&context_id, cmd_addr,
- 0, 0, 0, 0, 0, &res);
- } while (res.a0 == QCOM_SCM_INTERRUPTED);
-
- return res.a0;
+ arm_smccc_smc(smc->args[0], smc->args[1], smc->args[2],
+ smc->args[3], smc->args[4], smc->args[5],
+ smc->args[6], smc->args[7], res);
+ } while (res->a0 == QCOM_SCM_INTERRUPTED);
}

/**
@@ -194,10 +200,12 @@ static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
struct qcom_scm_res *res)
{
u8 arglen = desc->arginfo & 0xf;
- int ret;
+ int ret = 0, context_id;
unsigned int i;
struct scm_legacy_command *cmd;
struct scm_legacy_response *rsp;
+ struct arm_smccc_args smc = {0};
+ struct arm_smccc_res smc_res;
const size_t cmd_len = arglen * sizeof(__le32);
const size_t resp_len = MAX_QCOM_SCM_RETS * sizeof(__le32);
size_t alloc_len = sizeof(*cmd) + cmd_len + sizeof(*rsp) + resp_len;
@@ -226,10 +234,14 @@ static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
return -ENOMEM;
}

+ smc.args[0] = 1;
+ smc.args[1] = (unsigned long)&context_id;
+ smc.args[2] = cmd_phys;
+
mutex_lock(&qcom_scm_lock);
- ret = __scm_legacy_do(cmd_phys);
- if (ret < 0)
- ret = qcom_scm_remap_error(ret);
+ __scm_legacy_do(&smc, &smc_res);
+ if (smc_res.a0)
+ ret = qcom_scm_remap_error(smc_res.a0);
mutex_unlock(&qcom_scm_lock);
if (ret)
goto out;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

2020-01-07 21:19:18

by Elliot Berman

[permalink] [raw]
Subject: [PATCH v5 14/17] firmware: qcom_scm-32: Add device argument to atomic calls

Add unused "device" parameter to reduce merge friction between SMCCC and
legacy based conventions in an upcoming patch.

Change-Id: Ie31b220d751ae08430b3e89d41de0217e5213435
Tested-by: Brian Masney <[email protected]> # arm32
Tested-by: Stephan Gerhold <[email protected]>
Signed-off-by: Elliot Berman <[email protected]>
---
drivers/firmware/qcom_scm-32.c | 18 ++++++++++--------
drivers/firmware/qcom_scm-64.c | 5 +++--
drivers/firmware/qcom_scm.c | 5 +++--
drivers/firmware/qcom_scm.h | 5 +++--
4 files changed, 19 insertions(+), 14 deletions(-)

diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c
index 9729a8a..e9b396c 100644
--- a/drivers/firmware/qcom_scm-32.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -285,7 +285,8 @@ static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
* This shall only be used with commands that are guaranteed to be
* uninterruptable, atomic and SMP safe.
*/
-static int qcom_scm_call_atomic(const struct qcom_scm_desc *desc,
+static int qcom_scm_call_atomic(struct device *unused,
+ const struct qcom_scm_desc *desc,
struct qcom_scm_res *res)
{
int context_id;
@@ -316,7 +317,8 @@ static int qcom_scm_call_atomic(const struct qcom_scm_desc *desc,
* Set the cold boot address of the cpus. Any cpu outside the supported
* range would be removed from the cpu present mask.
*/
-int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_cold_boot_addr(struct device *dev, void *entry,
+ const cpumask_t *cpus)
{
int flags = 0;
int cpu;
@@ -345,7 +347,7 @@ int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
desc.args[1] = virt_to_phys(entry);
desc.arginfo = QCOM_SCM_ARGS(2);

- return qcom_scm_call_atomic(&desc, NULL);
+ return qcom_scm_call_atomic(dev, &desc, NULL);
}

/**
@@ -402,7 +404,7 @@ int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
* the control would return from this function, otherwise, the cpu jumps to the
* warm boot entry point set for this cpu upon reset.
*/
-void __qcom_scm_cpu_power_down(u32 flags)
+void __qcom_scm_cpu_power_down(struct device *dev, u32 flags)
{
struct qcom_scm_desc desc = {
.svc = QCOM_SCM_SVC_BOOT,
@@ -411,7 +413,7 @@ void __qcom_scm_cpu_power_down(u32 flags)
.arginfo = QCOM_SCM_ARGS(1),
};

- qcom_scm_call_atomic(&desc, NULL);
+ qcom_scm_call_atomic(dev, &desc, NULL);
}

int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
@@ -616,7 +618,7 @@ int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
desc.arginfo = QCOM_SCM_ARGS(2);

- return qcom_scm_call_atomic(&desc, NULL);
+ return qcom_scm_call_atomic(dev, &desc, NULL);
}

int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
@@ -687,7 +689,7 @@ int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
desc.args[0] = addr;
desc.arginfo = QCOM_SCM_ARGS(1);

- ret = qcom_scm_call_atomic(&desc, &res);
+ ret = qcom_scm_call_atomic(dev, &desc, &res);
if (ret >= 0)
*val = res.result[0];

@@ -705,7 +707,7 @@ int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)
desc.args[1] = val;
desc.arginfo = QCOM_SCM_ARGS(2);

- return qcom_scm_call_atomic(&desc, NULL);
+ return qcom_scm_call_atomic(dev, &desc, NULL);
}

int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool enable)
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
index 6bc7f69..9507047 100644
--- a/drivers/firmware/qcom_scm-64.c
+++ b/drivers/firmware/qcom_scm-64.c
@@ -239,7 +239,8 @@ static int qcom_scm_call_atomic(struct device *dev,
* Set the cold boot address of the cpus. Any cpu outside the supported
* range would be removed from the cpu present mask.
*/
-int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
+int __qcom_scm_set_cold_boot_addr(struct device *dev, void *entry,
+ const cpumask_t *cpus)
{
return -ENOTSUPP;
}
@@ -267,7 +268,7 @@ int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
* the control would return from this function, otherwise, the cpu jumps to the
* warm boot entry point set for this cpu upon reset.
*/
-void __qcom_scm_cpu_power_down(u32 flags)
+void __qcom_scm_cpu_power_down(struct device *dev, u32 flags)
{
}

diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 097f8b3..5efe729 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -94,7 +94,8 @@ static void qcom_scm_clk_disable(void)
*/
int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
{
- return __qcom_scm_set_cold_boot_addr(entry, cpus);
+ return __qcom_scm_set_cold_boot_addr(__scm ? __scm->dev : NULL, entry,
+ cpus);
}
EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);

@@ -122,7 +123,7 @@ EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
*/
void qcom_scm_cpu_power_down(u32 flags)
{
- __qcom_scm_cpu_power_down(flags);
+ __qcom_scm_cpu_power_down(__scm ? __scm->dev : NULL, flags);
}
EXPORT_SYMBOL(qcom_scm_cpu_power_down);

diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h
index afcca16..a022556 100644
--- a/drivers/firmware/qcom_scm.h
+++ b/drivers/firmware/qcom_scm.h
@@ -13,11 +13,12 @@ extern int __qcom_scm_set_dload_mode(struct device *dev, bool enable);

extern int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
const cpumask_t *cpus);
-extern int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
+extern int __qcom_scm_set_cold_boot_addr(struct device *dev, void *entry,
+ const cpumask_t *cpus);

#define QCOM_SCM_BOOT_TERMINATE_PC 0x2
#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
-extern void __qcom_scm_cpu_power_down(u32 flags);
+extern void __qcom_scm_cpu_power_down(struct device *dev, u32 flags);

#define QCOM_SCM_SVC_IO 0x5
#define QCOM_SCM_IO_READ 0x1
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

2020-01-07 21:20:05

by Elliot Berman

[permalink] [raw]
Subject: [PATCH v5 11/17] firmware: qcom_scm-32: Use qcom_scm_desc in non-atomic calls

Use qcom_scm_desc in non-atomic calls to remove legacy convention
details from every SCM wrapper function. Implementations were copied
from qcom_scm-64 and are functionally equivalent when using the
qcom_scm_desc and qcom_scm_res structs.

Change-Id: I6962d86b0a8edcedf0d7fe7700794aa8bfdac430
Tested-by: Brian Masney <[email protected]> # arm32
Tested-by: Stephan Gerhold <[email protected]>
Signed-off-by: Elliot Berman <[email protected]>
---
drivers/firmware/qcom_scm-32.c | 367 ++++++++++++++++++++++++-----------------
1 file changed, 218 insertions(+), 149 deletions(-)

diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c
index fcbe9e0..ce3a61b 100644
--- a/drivers/firmware/qcom_scm-32.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -39,6 +39,52 @@ static struct qcom_scm_entry qcom_scm_wb[] = {

static DEFINE_MUTEX(qcom_scm_lock);

+#define MAX_QCOM_SCM_ARGS 10
+#define MAX_QCOM_SCM_RETS 3
+
+enum qcom_scm_arg_types {
+ QCOM_SCM_VAL,
+ QCOM_SCM_RO,
+ QCOM_SCM_RW,
+ QCOM_SCM_BUFVAL,
+};
+
+#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
+ (((a) & 0x3) << 4) | \
+ (((b) & 0x3) << 6) | \
+ (((c) & 0x3) << 8) | \
+ (((d) & 0x3) << 10) | \
+ (((e) & 0x3) << 12) | \
+ (((f) & 0x3) << 14) | \
+ (((g) & 0x3) << 16) | \
+ (((h) & 0x3) << 18) | \
+ (((i) & 0x3) << 20) | \
+ (((j) & 0x3) << 22) | \
+ ((num) & 0xf))
+
+#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
+
+/**
+ * struct qcom_scm_desc
+ * @arginfo: Metadata describing the arguments in args[]
+ * @args: The array of arguments for the secure syscall
+ */
+struct qcom_scm_desc {
+ u32 svc;
+ u32 cmd;
+ u32 arginfo;
+ u64 args[MAX_QCOM_SCM_ARGS];
+ u32 owner;
+};
+
+/**
+ * struct qcom_scm_res
+ * @result: The values returned by the secure syscall
+ */
+struct qcom_scm_res {
+ u64 result[MAX_QCOM_SCM_RETS];
+};
+
#define SCM_LEGACY_FNID(s, c) (((s) << 10) | ((c) & 0x3ff))

/**
@@ -134,16 +180,8 @@ static u32 __scm_legacy_do(u32 cmd_addr)
}

/**
- * qcom_scm_call() - Send an SCM command
- * @dev: struct device
- * @svc_id: service identifier
- * @cmd_id: command identifier
- * @cmd_buf: command buffer
- * @cmd_len: length of the command buffer
- * @resp_buf: response buffer
- * @resp_len: length of the response buffer
- *
- * Sends a command to the SCM and waits for the command to finish processing.
+ * qcom_scm_call() - Sends a command to the SCM and waits for the command to
+ * finish processing.
*
* A note on cache maintenance:
* Note that any buffers that are expected to be accessed by the secure world
@@ -152,15 +190,20 @@ static u32 __scm_legacy_do(u32 cmd_addr)
* and response buffers is taken care of by qcom_scm_call; however, callers are
* responsible for any other cached buffers passed over to the secure world.
*/
-static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id,
- const void *cmd_buf, size_t cmd_len, void *resp_buf,
- size_t resp_len)
+static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
+ struct qcom_scm_res *res)
{
+ u8 arglen = desc->arginfo & 0xf;
int ret;
+ unsigned int i;
struct scm_legacy_command *cmd;
struct scm_legacy_response *rsp;
+ const size_t cmd_len = arglen * sizeof(__le32);
+ const size_t resp_len = MAX_QCOM_SCM_RETS * sizeof(__le32);
size_t alloc_len = sizeof(*cmd) + cmd_len + sizeof(*rsp) + resp_len;
dma_addr_t cmd_phys;
+ __le32 *arg_buf;
+ const __le32 *res_buf;

cmd = kzalloc(PAGE_ALIGN(alloc_len), GFP_KERNEL);
if (!cmd)
@@ -169,10 +212,11 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id,
cmd->len = cpu_to_le32(alloc_len);
cmd->buf_offset = cpu_to_le32(sizeof(*cmd));
cmd->resp_hdr_offset = cpu_to_le32(sizeof(*cmd) + cmd_len);
+ cmd->id = cpu_to_le32(SCM_LEGACY_FNID(desc->svc, desc->cmd));

- cmd->id = cpu_to_le32(SCM_LEGACY_FNID(svc_id, cmd_id));
- if (cmd_buf)
- memcpy(scm_legacy_get_command_buffer(cmd), cmd_buf, cmd_len);
+ arg_buf = scm_legacy_get_command_buffer(cmd);
+ for (i = 0; i < arglen; i++)
+ arg_buf[i] = cpu_to_le32(desc->args[i]);

rsp = scm_legacy_command_to_response(cmd);

@@ -195,12 +239,14 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id,
sizeof(*rsp), DMA_FROM_DEVICE);
} while (!rsp->is_complete);

- if (resp_buf) {
- dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
- le32_to_cpu(rsp->buf_offset),
- resp_len, DMA_FROM_DEVICE);
- memcpy(resp_buf, scm_legacy_get_response_buffer(rsp),
- resp_len);
+ dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
+ le32_to_cpu(rsp->buf_offset),
+ resp_len, DMA_FROM_DEVICE);
+
+ if (res) {
+ res_buf = scm_legacy_get_response_buffer(rsp);
+ for (i = 0; i < MAX_QCOM_SCM_RETS; i++)
+ res->result[i] = le32_to_cpu(res_buf[i]);
}
out:
dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
@@ -304,10 +350,10 @@ int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
int ret;
int flags = 0;
int cpu;
- struct {
- __le32 flags;
- __le32 addr;
- } cmd;
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_BOOT,
+ .cmd = QCOM_SCM_BOOT_SET_ADDR,
+ };

/*
* Reassign only if we are switching from hotplug entry point
@@ -323,10 +369,11 @@ int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
if (!flags)
return 0;

- cmd.addr = cpu_to_le32(virt_to_phys(entry));
- cmd.flags = cpu_to_le32(flags);
- ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_ADDR,
- &cmd, sizeof(cmd), NULL, 0);
+ desc.args[0] = flags;
+ desc.args[1] = virt_to_phys(entry);
+ desc.arginfo = QCOM_SCM_ARGS(2);
+
+ ret = qcom_scm_call(dev, &desc, NULL);
if (!ret) {
for_each_cpu(cpu, cpus)
qcom_scm_wb[cpu].entry = entry;
@@ -352,61 +399,80 @@ void __qcom_scm_cpu_power_down(u32 flags)
int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
{
int ret;
- __le32 svc_cmd = cpu_to_le32(SCM_LEGACY_FNID(svc_id, cmd_id));
- __le32 ret_val = 0;
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_INFO,
+ .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
+ .args[0] = SCM_LEGACY_FNID(svc_id, cmd_id),
+ .arginfo = QCOM_SCM_ARGS(1),
+ };
+ struct qcom_scm_res res;

- ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_SCM_INFO_IS_CALL_AVAIL,
- &svc_cmd, sizeof(svc_cmd), &ret_val,
- sizeof(ret_val));
- if (ret)
- return ret;
+ ret = qcom_scm_call(dev, &desc, &res);

- return le32_to_cpu(ret_val);
+ return ret ? : res.result[0];
}

int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
u32 req_cnt, u32 *resp)
{
+ int ret;
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_HDCP,
+ .cmd = QCOM_SCM_HDCP_INVOKE,
+ };
+ struct qcom_scm_res res;
+
if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
return -ERANGE;

- return qcom_scm_call(dev, QCOM_SCM_SVC_HDCP, QCOM_SCM_HDCP_INVOKE,
- req, req_cnt * sizeof(*req), resp, sizeof(*resp));
+ desc.args[0] = req[0].addr;
+ desc.args[1] = req[0].val;
+ desc.args[2] = req[1].addr;
+ desc.args[3] = req[1].val;
+ desc.args[4] = req[2].addr;
+ desc.args[5] = req[2].val;
+ desc.args[6] = req[3].addr;
+ desc.args[7] = req[3].val;
+ desc.args[8] = req[4].addr;
+ desc.args[9] = req[4].val;
+ desc.arginfo = QCOM_SCM_ARGS(10);
+
+ ret = qcom_scm_call(dev, &desc, &res);
+ *resp = res.result[0];
+
+ return ret;
}

int __qcom_scm_ocmem_lock(struct device *dev, u32 id, u32 offset, u32 size,
u32 mode)
{
- struct ocmem_tz_lock {
- __le32 id;
- __le32 offset;
- __le32 size;
- __le32 mode;
- } request;
-
- request.id = cpu_to_le32(id);
- request.offset = cpu_to_le32(offset);
- request.size = cpu_to_le32(size);
- request.mode = cpu_to_le32(mode);
-
- return qcom_scm_call(dev, QCOM_SCM_SVC_OCMEM, QCOM_SCM_OCMEM_LOCK_CMD,
- &request, sizeof(request), NULL, 0);
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_OCMEM,
+ .cmd = QCOM_SCM_OCMEM_LOCK_CMD,
+ };
+
+ desc.args[0] = id;
+ desc.args[1] = offset;
+ desc.args[2] = size;
+ desc.args[3] = mode;
+ desc.arginfo = QCOM_SCM_ARGS(4);
+
+ return qcom_scm_call(dev, &desc, NULL);
}

int __qcom_scm_ocmem_unlock(struct device *dev, u32 id, u32 offset, u32 size)
{
- struct ocmem_tz_unlock {
- __le32 id;
- __le32 offset;
- __le32 size;
- } request;
-
- request.id = cpu_to_le32(id);
- request.offset = cpu_to_le32(offset);
- request.size = cpu_to_le32(size);
-
- return qcom_scm_call(dev, QCOM_SCM_SVC_OCMEM, QCOM_SCM_OCMEM_UNLOCK_CMD,
- &request, sizeof(request), NULL, 0);
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_OCMEM,
+ .cmd = QCOM_SCM_OCMEM_UNLOCK_CMD,
+ };
+
+ desc.args[0] = id;
+ desc.args[1] = offset;
+ desc.args[2] = size;
+ desc.arginfo = QCOM_SCM_ARGS(3);
+
+ return qcom_scm_call(dev, &desc, NULL);
}

void __qcom_scm_init(void)
@@ -415,104 +481,110 @@ void __qcom_scm_init(void)

bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral)
{
- __le32 out;
- __le32 in;
int ret;
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_PIL,
+ .cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED,
+ };
+ struct qcom_scm_res res;
+
+ desc.args[0] = peripheral;
+ desc.arginfo = QCOM_SCM_ARGS(1);

- in = cpu_to_le32(peripheral);
- ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
- QCOM_SCM_PIL_PAS_IS_SUPPORTED,
- &in, sizeof(in),
- &out, sizeof(out));
+ ret = qcom_scm_call(dev, &desc, &res);

- return ret ? false : !!out;
+ return ret ? false : !!res.result[0];
}

int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
dma_addr_t metadata_phys)
{
- __le32 scm_ret;
int ret;
- struct {
- __le32 proc;
- __le32 image_addr;
- } request;
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_PIL,
+ .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,
+ };
+ struct qcom_scm_res res;

- request.proc = cpu_to_le32(peripheral);
- request.image_addr = cpu_to_le32(metadata_phys);
+ desc.args[0] = peripheral;
+ desc.args[1] = metadata_phys;
+ desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW);

- ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
- QCOM_SCM_PIL_PAS_INIT_IMAGE,
- &request, sizeof(request),
- &scm_ret, sizeof(scm_ret));
+ ret = qcom_scm_call(dev, &desc, &res);

- return ret ? : le32_to_cpu(scm_ret);
+ return ret ? : res.result[0];
}

int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
- phys_addr_t addr, phys_addr_t size)
+ phys_addr_t addr, phys_addr_t size)
{
- __le32 scm_ret;
int ret;
- struct {
- __le32 proc;
- __le32 addr;
- __le32 len;
- } request;
-
- request.proc = cpu_to_le32(peripheral);
- request.addr = cpu_to_le32(addr);
- request.len = cpu_to_le32(size);
-
- ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
- QCOM_SCM_PIL_PAS_MEM_SETUP,
- &request, sizeof(request),
- &scm_ret, sizeof(scm_ret));
-
- return ret ? : le32_to_cpu(scm_ret);
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_PIL,
+ .cmd = QCOM_SCM_PIL_PAS_MEM_SETUP,
+ };
+ struct qcom_scm_res res;
+
+ desc.args[0] = peripheral;
+ desc.args[1] = addr;
+ desc.args[2] = size;
+ desc.arginfo = QCOM_SCM_ARGS(3);
+
+ ret = qcom_scm_call(dev, &desc, &res);
+
+ return ret ? : res.result[0];
}

int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral)
{
- __le32 out;
- __le32 in;
int ret;
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_PIL,
+ .cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
+ };
+ struct qcom_scm_res res;
+
+ desc.args[0] = peripheral;
+ desc.arginfo = QCOM_SCM_ARGS(1);

- in = cpu_to_le32(peripheral);
- ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
- QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
- &in, sizeof(in),
- &out, sizeof(out));
+ ret = qcom_scm_call(dev, &desc, &res);

- return ret ? : le32_to_cpu(out);
+ return ret ? : res.result[0];
}

int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral)
{
- __le32 out;
- __le32 in;
int ret;
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_PIL,
+ .cmd = QCOM_SCM_PIL_PAS_SHUTDOWN,
+ };
+ struct qcom_scm_res res;
+
+ desc.args[0] = peripheral;
+ desc.arginfo = QCOM_SCM_ARGS(1);

- in = cpu_to_le32(peripheral);
- ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
- QCOM_SCM_PIL_PAS_SHUTDOWN,
- &in, sizeof(in),
- &out, sizeof(out));
+ ret = qcom_scm_call(dev, &desc, &res);

- return ret ? : le32_to_cpu(out);
+ return ret ? : res.result[0];
}

int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
{
- __le32 out;
- __le32 in = cpu_to_le32(reset);
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_PIL,
+ .cmd = QCOM_SCM_PIL_PAS_MSS_RESET,
+ };
+ struct qcom_scm_res res;
int ret;

- ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_MSS_RESET,
- &in, sizeof(in),
- &out, sizeof(out));
+ desc.args[0] = reset;
+ desc.args[1] = 0;
+ desc.arginfo = QCOM_SCM_ARGS(2);

- return ret ? : le32_to_cpu(out);
+ ret = qcom_scm_call(dev, &desc, &res);
+
+ return ret ? : res.result[0];
}

int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
@@ -523,20 +595,19 @@ int __qcom_scm_set_dload_mode(struct device *dev, bool enable)

int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
{
- struct {
- __le32 state;
- __le32 id;
- } req;
- __le32 scm_ret = 0;
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_BOOT,
+ .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE,
+ };
+ struct qcom_scm_res res;
int ret;

- req.state = cpu_to_le32(state);
- req.id = cpu_to_le32(id);
+ desc.args[0] = state;
+ desc.args[1] = id;

- ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_REMOTE_STATE,
- &req, sizeof(req), &scm_ret, sizeof(scm_ret));
+ ret = qcom_scm_call(dev, &desc, &res);

- return ret ? : le32_to_cpu(scm_ret);
+ return ret ? : res.result[0];
}

int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
@@ -549,22 +620,20 @@ int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
u32 spare)
{
- struct msm_scm_sec_cfg {
- __le32 id;
- __le32 ctx_bank_num;
- } cfg;
- int ret, scm_ret = 0;
-
- cfg.id = cpu_to_le32(device_id);
- cfg.ctx_bank_num = cpu_to_le32(spare);
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_MP,
+ .cmd = QCOM_SCM_MP_RESTORE_SEC_CFG,
+ };
+ struct qcom_scm_res res;
+ int ret;

- ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP, QCOM_SCM_MP_RESTORE_SEC_CFG,
- &cfg, sizeof(cfg), &scm_ret, sizeof(scm_ret));
+ desc.args[0] = device_id;
+ desc.args[1] = spare;
+ desc.arginfo = QCOM_SCM_ARGS(2);

- if (ret || scm_ret)
- return ret ? ret : -EINVAL;
+ ret = qcom_scm_call(dev, &desc, &res);

- return 0;
+ return ret ? : res.result[0];
}

int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

2020-01-07 21:20:16

by Elliot Berman

[permalink] [raw]
Subject: [PATCH v5 16/17] firmware: qcom_scm: Remove thin wrappers

qcom_scm-32 and qcom_scm-64 implementations are nearly identical, so
make qcom_scm_call and qcom_scm_call_atomic unique to each and the SCM
descriptor creation common to each. There are the following catches:
- __qcom_scm_is_call_available is still in each -32,-64 implementation
as the argument is unique to each convention
- For some functions, only one implementation was provided in -32 or
-64. The actual implementation was moved into qcom_scm.c
- io_writel and io_readl in -64 were non-atomic calls and in -32 they
were. Atomic is the better option, so use it.

Change-Id: Iecc28c4a7afef2fc39c7da207c8f53f27447727e
Tested-by: Brian Masney <[email protected]> # arm32
Tested-by: Stephan Gerhold <[email protected]>
Signed-off-by: Elliot Berman <[email protected]>
---
drivers/firmware/qcom_scm-32.c | 461 +----------------------------------------
drivers/firmware/qcom_scm-64.c | 434 +-------------------------------------
drivers/firmware/qcom_scm.c | 394 ++++++++++++++++++++++++++++++++---
drivers/firmware/qcom_scm.h | 87 ++++----
4 files changed, 428 insertions(+), 948 deletions(-)

diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c
index e9b396c..08220e7 100644
--- a/drivers/firmware/qcom_scm-32.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -15,75 +15,8 @@

#include "qcom_scm.h"

-#define QCOM_SCM_FLAG_COLDBOOT_CPU0 0x00
-#define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01
-#define QCOM_SCM_FLAG_COLDBOOT_CPU2 0x08
-#define QCOM_SCM_FLAG_COLDBOOT_CPU3 0x20
-
-#define QCOM_SCM_FLAG_WARMBOOT_CPU0 0x04
-#define QCOM_SCM_FLAG_WARMBOOT_CPU1 0x02
-#define QCOM_SCM_FLAG_WARMBOOT_CPU2 0x10
-#define QCOM_SCM_FLAG_WARMBOOT_CPU3 0x40
-
-struct qcom_scm_entry {
- int flag;
- void *entry;
-};
-
-static struct qcom_scm_entry qcom_scm_wb[] = {
- { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 },
- { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 },
- { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 },
- { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 },
-};
-
static DEFINE_MUTEX(qcom_scm_lock);

-#define MAX_QCOM_SCM_ARGS 10
-#define MAX_QCOM_SCM_RETS 3
-
-enum qcom_scm_arg_types {
- QCOM_SCM_VAL,
- QCOM_SCM_RO,
- QCOM_SCM_RW,
- QCOM_SCM_BUFVAL,
-};
-
-#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
- (((a) & 0x3) << 4) | \
- (((b) & 0x3) << 6) | \
- (((c) & 0x3) << 8) | \
- (((d) & 0x3) << 10) | \
- (((e) & 0x3) << 12) | \
- (((f) & 0x3) << 14) | \
- (((g) & 0x3) << 16) | \
- (((h) & 0x3) << 18) | \
- (((i) & 0x3) << 20) | \
- (((j) & 0x3) << 22) | \
- ((num) & 0xf))
-
-#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
-
-/**
- * struct qcom_scm_desc
- * @arginfo: Metadata describing the arguments in args[]
- * @args: The array of arguments for the secure syscall
- */
-struct qcom_scm_desc {
- u32 svc;
- u32 cmd;
- u32 arginfo;
- u64 args[MAX_QCOM_SCM_ARGS];
- u32 owner;
-};
-
-/**
- * struct qcom_scm_res
- * @result: The values returned by the secure syscall
- */
-struct qcom_scm_res {
- u64 result[MAX_QCOM_SCM_RETS];
-};

/**
* struct arm_smccc_args
@@ -196,7 +129,7 @@ static void __scm_legacy_do(const struct arm_smccc_args *smc,
* and response buffers is taken care of by qcom_scm_call; however, callers are
* responsible for any other cached buffers passed over to the secure world.
*/
-static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
+int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
struct qcom_scm_res *res)
{
u8 arglen = desc->arginfo & 0xf;
@@ -285,9 +218,9 @@ static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
* This shall only be used with commands that are guaranteed to be
* uninterruptable, atomic and SMP safe.
*/
-static int qcom_scm_call_atomic(struct device *unused,
- const struct qcom_scm_desc *desc,
- struct qcom_scm_res *res)
+int qcom_scm_call_atomic(struct device *unused,
+ const struct qcom_scm_desc *desc,
+ struct qcom_scm_res *res)
{
int context_id;
struct arm_smccc_res smc_res;
@@ -309,113 +242,6 @@ static int qcom_scm_call_atomic(struct device *unused,
return smc_res.a0;
}

-/**
- * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
- * @entry: Entry point function for the cpus
- * @cpus: The cpumask of cpus that will use the entry point
- *
- * Set the cold boot address of the cpus. Any cpu outside the supported
- * range would be removed from the cpu present mask.
- */
-int __qcom_scm_set_cold_boot_addr(struct device *dev, void *entry,
- const cpumask_t *cpus)
-{
- int flags = 0;
- int cpu;
- int scm_cb_flags[] = {
- QCOM_SCM_FLAG_COLDBOOT_CPU0,
- QCOM_SCM_FLAG_COLDBOOT_CPU1,
- QCOM_SCM_FLAG_COLDBOOT_CPU2,
- QCOM_SCM_FLAG_COLDBOOT_CPU3,
- };
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_BOOT,
- .cmd = QCOM_SCM_BOOT_SET_ADDR,
- };
-
- if (!cpus || (cpus && cpumask_empty(cpus)))
- return -EINVAL;
-
- for_each_cpu(cpu, cpus) {
- if (cpu < ARRAY_SIZE(scm_cb_flags))
- flags |= scm_cb_flags[cpu];
- else
- set_cpu_present(cpu, false);
- }
-
- desc.args[0] = flags;
- desc.args[1] = virt_to_phys(entry);
- desc.arginfo = QCOM_SCM_ARGS(2);
-
- return qcom_scm_call_atomic(dev, &desc, NULL);
-}
-
-/**
- * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
- * @entry: Entry point function for the cpus
- * @cpus: The cpumask of cpus that will use the entry point
- *
- * Set the Linux entry point for the SCM to transfer control to when coming
- * out of a power down. CPU power down may be executed on cpuidle or hotplug.
- */
-int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
- const cpumask_t *cpus)
-{
- int ret;
- int flags = 0;
- int cpu;
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_BOOT,
- .cmd = QCOM_SCM_BOOT_SET_ADDR,
- };
-
- /*
- * Reassign only if we are switching from hotplug entry point
- * to cpuidle entry point or vice versa.
- */
- for_each_cpu(cpu, cpus) {
- if (entry == qcom_scm_wb[cpu].entry)
- continue;
- flags |= qcom_scm_wb[cpu].flag;
- }
-
- /* No change in entry function */
- if (!flags)
- return 0;
-
- desc.args[0] = flags;
- desc.args[1] = virt_to_phys(entry);
- desc.arginfo = QCOM_SCM_ARGS(2);
-
- ret = qcom_scm_call(dev, &desc, NULL);
- if (!ret) {
- for_each_cpu(cpu, cpus)
- qcom_scm_wb[cpu].entry = entry;
- }
-
- return ret;
-}
-
-/**
- * qcom_scm_cpu_power_down() - Power down the cpu
- * @flags - Flags to flush cache
- *
- * This is an end point to power down cpu. If there was a pending interrupt,
- * the control would return from this function, otherwise, the cpu jumps to the
- * warm boot entry point set for this cpu upon reset.
- */
-void __qcom_scm_cpu_power_down(struct device *dev, u32 flags)
-{
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_BOOT,
- .cmd = QCOM_SCM_BOOT_TERMINATE_PC,
- .args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK,
- .arginfo = QCOM_SCM_ARGS(1),
- };
-
- qcom_scm_call_atomic(dev, &desc, NULL);
-}
-
int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
{
int ret;
@@ -432,285 +258,6 @@ int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
return ret ? : res.result[0];
}

-int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
- u32 req_cnt, u32 *resp)
-{
- int ret;
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_HDCP,
- .cmd = QCOM_SCM_HDCP_INVOKE,
- };
- struct qcom_scm_res res;
-
- if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
- return -ERANGE;
-
- desc.args[0] = req[0].addr;
- desc.args[1] = req[0].val;
- desc.args[2] = req[1].addr;
- desc.args[3] = req[1].val;
- desc.args[4] = req[2].addr;
- desc.args[5] = req[2].val;
- desc.args[6] = req[3].addr;
- desc.args[7] = req[3].val;
- desc.args[8] = req[4].addr;
- desc.args[9] = req[4].val;
- desc.arginfo = QCOM_SCM_ARGS(10);
-
- ret = qcom_scm_call(dev, &desc, &res);
- *resp = res.result[0];
-
- return ret;
-}
-
-int __qcom_scm_ocmem_lock(struct device *dev, u32 id, u32 offset, u32 size,
- u32 mode)
-{
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_OCMEM,
- .cmd = QCOM_SCM_OCMEM_LOCK_CMD,
- };
-
- desc.args[0] = id;
- desc.args[1] = offset;
- desc.args[2] = size;
- desc.args[3] = mode;
- desc.arginfo = QCOM_SCM_ARGS(4);
-
- return qcom_scm_call(dev, &desc, NULL);
-}
-
-int __qcom_scm_ocmem_unlock(struct device *dev, u32 id, u32 offset, u32 size)
-{
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_OCMEM,
- .cmd = QCOM_SCM_OCMEM_UNLOCK_CMD,
- };
-
- desc.args[0] = id;
- desc.args[1] = offset;
- desc.args[2] = size;
- desc.arginfo = QCOM_SCM_ARGS(3);
-
- return qcom_scm_call(dev, &desc, NULL);
-}
-
void __qcom_scm_init(void)
{
}
-
-bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral)
-{
- int ret;
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_PIL,
- .cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED,
- };
- struct qcom_scm_res res;
-
- desc.args[0] = peripheral;
- desc.arginfo = QCOM_SCM_ARGS(1);
-
- ret = qcom_scm_call(dev, &desc, &res);
-
- return ret ? false : !!res.result[0];
-}
-
-int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
- dma_addr_t metadata_phys)
-{
- int ret;
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_PIL,
- .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,
- };
- struct qcom_scm_res res;
-
- desc.args[0] = peripheral;
- desc.args[1] = metadata_phys;
- desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW);
-
- ret = qcom_scm_call(dev, &desc, &res);
-
- return ret ? : res.result[0];
-}
-
-int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
- phys_addr_t addr, phys_addr_t size)
-{
- int ret;
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_PIL,
- .cmd = QCOM_SCM_PIL_PAS_MEM_SETUP,
- };
- struct qcom_scm_res res;
-
- desc.args[0] = peripheral;
- desc.args[1] = addr;
- desc.args[2] = size;
- desc.arginfo = QCOM_SCM_ARGS(3);
-
- ret = qcom_scm_call(dev, &desc, &res);
-
- return ret ? : res.result[0];
-}
-
-int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral)
-{
- int ret;
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_PIL,
- .cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
- };
- struct qcom_scm_res res;
-
- desc.args[0] = peripheral;
- desc.arginfo = QCOM_SCM_ARGS(1);
-
- ret = qcom_scm_call(dev, &desc, &res);
-
- return ret ? : res.result[0];
-}
-
-int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral)
-{
- int ret;
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_PIL,
- .cmd = QCOM_SCM_PIL_PAS_SHUTDOWN,
- };
- struct qcom_scm_res res;
-
- desc.args[0] = peripheral;
- desc.arginfo = QCOM_SCM_ARGS(1);
-
- ret = qcom_scm_call(dev, &desc, &res);
-
- return ret ? : res.result[0];
-}
-
-int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
-{
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_PIL,
- .cmd = QCOM_SCM_PIL_PAS_MSS_RESET,
- };
- struct qcom_scm_res res;
- int ret;
-
- desc.args[0] = reset;
- desc.args[1] = 0;
- desc.arginfo = QCOM_SCM_ARGS(2);
-
- ret = qcom_scm_call(dev, &desc, &res);
-
- return ret ? : res.result[0];
-}
-
-int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
-{
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_BOOT,
- .cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE,
- };
-
- desc.args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE;
- desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
- desc.arginfo = QCOM_SCM_ARGS(2);
-
- return qcom_scm_call_atomic(dev, &desc, NULL);
-}
-
-int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
-{
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_BOOT,
- .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE,
- };
- struct qcom_scm_res res;
- int ret;
-
- desc.args[0] = state;
- desc.args[1] = id;
-
- ret = qcom_scm_call(dev, &desc, &res);
-
- return ret ? : res.result[0];
-}
-
-int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
- size_t mem_sz, phys_addr_t src, size_t src_sz,
- phys_addr_t dest, size_t dest_sz)
-{
- return -ENODEV;
-}
-
-int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
- u32 spare)
-{
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_MP,
- .cmd = QCOM_SCM_MP_RESTORE_SEC_CFG,
- };
- struct qcom_scm_res res;
- int ret;
-
- desc.args[0] = device_id;
- desc.args[1] = spare;
- desc.arginfo = QCOM_SCM_ARGS(2);
-
- ret = qcom_scm_call(dev, &desc, &res);
-
- return ret ? : res.result[0];
-}
-
-int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
- size_t *size)
-{
- return -ENODEV;
-}
-
-int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,
- u32 spare)
-{
- return -ENODEV;
-}
-
-int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
- unsigned int *val)
-{
- int ret;
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_IO,
- .cmd = QCOM_SCM_IO_READ,
- };
- struct qcom_scm_res res;
-
- desc.args[0] = addr;
- desc.arginfo = QCOM_SCM_ARGS(1);
-
- ret = qcom_scm_call_atomic(dev, &desc, &res);
- if (ret >= 0)
- *val = res.result[0];
-
- return ret < 0 ? ret : 0;
-}
-
-int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)
-{
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_IO,
- .cmd = QCOM_SCM_IO_WRITE,
- };
-
- desc.args[0] = addr;
- desc.args[1] = val;
- desc.arginfo = QCOM_SCM_ARGS(2);
-
- return qcom_scm_call_atomic(dev, &desc, NULL);
-}
-
-int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool enable)
-{
- return -ENODEV;
-}
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
index 9507047..4defc7c 100644
--- a/drivers/firmware/qcom_scm-64.c
+++ b/drivers/firmware/qcom_scm-64.c
@@ -16,52 +16,6 @@

#define SCM_SMC_FNID(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF))

-#define MAX_QCOM_SCM_ARGS 10
-#define MAX_QCOM_SCM_RETS 3
-
-enum qcom_scm_arg_types {
- QCOM_SCM_VAL,
- QCOM_SCM_RO,
- QCOM_SCM_RW,
- QCOM_SCM_BUFVAL,
-};
-
-#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
- (((a) & 0x3) << 4) | \
- (((b) & 0x3) << 6) | \
- (((c) & 0x3) << 8) | \
- (((d) & 0x3) << 10) | \
- (((e) & 0x3) << 12) | \
- (((f) & 0x3) << 14) | \
- (((g) & 0x3) << 16) | \
- (((h) & 0x3) << 18) | \
- (((i) & 0x3) << 20) | \
- (((j) & 0x3) << 22) | \
- ((num) & 0xf))
-
-#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
-
-/**
- * struct qcom_scm_desc
- * @arginfo: Metadata describing the arguments in args[]
- * @args: The array of arguments for the secure syscall
- */
-struct qcom_scm_desc {
- u32 svc;
- u32 cmd;
- u32 arginfo;
- u64 args[MAX_QCOM_SCM_ARGS];
- u32 owner;
-};
-
-/**
- * struct qcom_scm_res
- * @result: The values returned by the secure syscall
- */
-struct qcom_scm_res {
- u64 result[MAX_QCOM_SCM_RETS];
-};
-
/**
* struct arm_smccc_args
* @args: The array of values used in registers in smc instruction
@@ -206,8 +160,8 @@ static int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
* Sends a command to the SCM and waits for the command to finish processing.
* This should *only* be called in pre-emptible context.
*/
-static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
- struct qcom_scm_res *res)
+int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
+ struct qcom_scm_res *res)
{
might_sleep();
return __scm_smc_call(dev, desc, res, false);
@@ -224,54 +178,12 @@ static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
* Sends a command to the SCM and waits for the command to finish processing.
* This can be called in atomic context.
*/
-static int qcom_scm_call_atomic(struct device *dev,
- const struct qcom_scm_desc *desc,
- struct qcom_scm_res *res)
+int qcom_scm_call_atomic(struct device *dev, const struct qcom_scm_desc *desc,
+ struct qcom_scm_res *res)
{
return __scm_smc_call(dev, desc, res, true);
}

-/**
- * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
- * @entry: Entry point function for the cpus
- * @cpus: The cpumask of cpus that will use the entry point
- *
- * Set the cold boot address of the cpus. Any cpu outside the supported
- * range would be removed from the cpu present mask.
- */
-int __qcom_scm_set_cold_boot_addr(struct device *dev, void *entry,
- const cpumask_t *cpus)
-{
- return -ENOTSUPP;
-}
-
-/**
- * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
- * @dev: Device pointer
- * @entry: Entry point function for the cpus
- * @cpus: The cpumask of cpus that will use the entry point
- *
- * Set the Linux entry point for the SCM to transfer control to when coming
- * out of a power down. CPU power down may be executed on cpuidle or hotplug.
- */
-int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
- const cpumask_t *cpus)
-{
- return -ENOTSUPP;
-}
-
-/**
- * qcom_scm_cpu_power_down() - Power down the cpu
- * @flags - Flags to flush cache
- *
- * This is an end point to power down cpu. If there was a pending interrupt,
- * the control would return from this function, otherwise, the cpu jumps to the
- * warm boot entry point set for this cpu upon reset.
- */
-void __qcom_scm_cpu_power_down(struct device *dev, u32 flags)
-{
-}
-
int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
{
int ret;
@@ -291,50 +203,6 @@ int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
return ret ? : res.result[0];
}

-int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
- u32 req_cnt, u32 *resp)
-{
- int ret;
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_HDCP,
- .cmd = QCOM_SCM_HDCP_INVOKE,
- .owner = ARM_SMCCC_OWNER_SIP,
- };
- struct qcom_scm_res res;
-
- if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
- return -ERANGE;
-
- desc.args[0] = req[0].addr;
- desc.args[1] = req[0].val;
- desc.args[2] = req[1].addr;
- desc.args[3] = req[1].val;
- desc.args[4] = req[2].addr;
- desc.args[5] = req[2].val;
- desc.args[6] = req[3].addr;
- desc.args[7] = req[3].val;
- desc.args[8] = req[4].addr;
- desc.args[9] = req[4].val;
- desc.arginfo = QCOM_SCM_ARGS(10);
-
- ret = qcom_scm_call(dev, &desc, &res);
- *resp = res.result[0];
-
- return ret;
-}
-
-int __qcom_scm_ocmem_lock(struct device *dev, uint32_t id, uint32_t offset,
- uint32_t size, uint32_t mode)
-{
- return -ENOTSUPP;
-}
-
-int __qcom_scm_ocmem_unlock(struct device *dev, uint32_t id, uint32_t offset,
- uint32_t size)
-{
- return -ENOTSUPP;
-}
-
void __qcom_scm_init(void)
{
struct qcom_scm_desc desc = {
@@ -366,297 +234,3 @@ void __qcom_scm_init(void)
out:
pr_info("QCOM SCM SMC Convention: %lld\n", qcom_smccc_convention);
}
-
-bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral)
-{
- int ret;
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_PIL,
- .cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED,
- .owner = ARM_SMCCC_OWNER_SIP,
- };
- struct qcom_scm_res res;
-
- desc.args[0] = peripheral;
- desc.arginfo = QCOM_SCM_ARGS(1);
-
- ret = qcom_scm_call(dev, &desc, &res);
-
- return ret ? false : !!res.result[0];
-}
-
-int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
- dma_addr_t metadata_phys)
-{
- int ret;
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_PIL,
- .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,
- .owner = ARM_SMCCC_OWNER_SIP,
- };
- struct qcom_scm_res res;
-
- desc.args[0] = peripheral;
- desc.args[1] = metadata_phys;
- desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW);
-
- ret = qcom_scm_call(dev, &desc, &res);
-
- return ret ? : res.result[0];
-}
-
-int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
- phys_addr_t addr, phys_addr_t size)
-{
- int ret;
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_PIL,
- .cmd = QCOM_SCM_PIL_PAS_MEM_SETUP,
- .owner = ARM_SMCCC_OWNER_SIP,
- };
- struct qcom_scm_res res;
-
- desc.args[0] = peripheral;
- desc.args[1] = addr;
- desc.args[2] = size;
- desc.arginfo = QCOM_SCM_ARGS(3);
-
- ret = qcom_scm_call(dev, &desc, &res);
-
- return ret ? : res.result[0];
-}
-
-int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral)
-{
- int ret;
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_PIL,
- .cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
- .owner = ARM_SMCCC_OWNER_SIP,
- };
- struct qcom_scm_res res;
-
- desc.args[0] = peripheral;
- desc.arginfo = QCOM_SCM_ARGS(1);
-
- ret = qcom_scm_call(dev, &desc, &res);
-
- return ret ? : res.result[0];
-}
-
-int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral)
-{
- int ret;
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_PIL,
- .cmd = QCOM_SCM_PIL_PAS_SHUTDOWN,
- .owner = ARM_SMCCC_OWNER_SIP,
- };
- struct qcom_scm_res res;
-
- desc.args[0] = peripheral;
- desc.arginfo = QCOM_SCM_ARGS(1);
-
- ret = qcom_scm_call(dev, &desc, &res);
-
- return ret ? : res.result[0];
-}
-
-int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
-{
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_PIL,
- .cmd = QCOM_SCM_PIL_PAS_MSS_RESET,
- .owner = ARM_SMCCC_OWNER_SIP,
- };
- struct qcom_scm_res res;
- int ret;
-
- desc.args[0] = reset;
- desc.args[1] = 0;
- desc.arginfo = QCOM_SCM_ARGS(2);
-
- ret = qcom_scm_call(dev, &desc, &res);
-
- return ret ? : res.result[0];
-}
-
-int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
-{
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_BOOT,
- .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE,
- .owner = ARM_SMCCC_OWNER_SIP,
- };
- struct qcom_scm_res res;
- int ret;
-
- desc.args[0] = state;
- desc.args[1] = id;
- desc.arginfo = QCOM_SCM_ARGS(2);
-
- ret = qcom_scm_call(dev, &desc, &res);
-
- return ret ? : res.result[0];
-}
-
-int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
- size_t mem_sz, phys_addr_t src, size_t src_sz,
- phys_addr_t dest, size_t dest_sz)
-{
- int ret;
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_MP,
- .cmd = QCOM_SCM_MP_ASSIGN,
- .owner = ARM_SMCCC_OWNER_SIP,
- };
- struct qcom_scm_res res;
-
- desc.args[0] = mem_region;
- desc.args[1] = mem_sz;
- desc.args[2] = src;
- desc.args[3] = src_sz;
- desc.args[4] = dest;
- desc.args[5] = dest_sz;
- desc.args[6] = 0;
-
- desc.arginfo = QCOM_SCM_ARGS(7, QCOM_SCM_RO, QCOM_SCM_VAL,
- QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_RO,
- QCOM_SCM_VAL, QCOM_SCM_VAL);
-
- ret = qcom_scm_call(dev, &desc, &res);
-
- return ret ? : res.result[0];
-}
-
-int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare)
-{
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_MP,
- .cmd = QCOM_SCM_MP_RESTORE_SEC_CFG,
- .owner = ARM_SMCCC_OWNER_SIP,
- };
- struct qcom_scm_res res;
- int ret;
-
- desc.args[0] = device_id;
- desc.args[1] = spare;
- desc.arginfo = QCOM_SCM_ARGS(2);
-
- ret = qcom_scm_call(dev, &desc, &res);
-
- return ret ? : res.result[0];
-}
-
-int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
- size_t *size)
-{
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_MP,
- .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE,
- .owner = ARM_SMCCC_OWNER_SIP,
- };
- struct qcom_scm_res res;
- int ret;
-
- desc.args[0] = spare;
- desc.arginfo = QCOM_SCM_ARGS(1);
-
- ret = qcom_scm_call(dev, &desc, &res);
-
- if (size)
- *size = res.result[0];
-
- return ret ? : res.result[1];
-}
-
-int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,
- u32 spare)
-{
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_MP,
- .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT,
- .owner = ARM_SMCCC_OWNER_SIP,
- };
- int ret;
-
- desc.args[0] = addr;
- desc.args[1] = size;
- desc.args[2] = spare;
- desc.arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL,
- QCOM_SCM_VAL);
-
- ret = qcom_scm_call(dev, &desc, NULL);
-
- /* the pg table has been initialized already, ignore the error */
- if (ret == -EPERM)
- ret = 0;
-
- return ret;
-}
-
-int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
-{
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_BOOT,
- .cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE,
- .owner = ARM_SMCCC_OWNER_SIP,
- };
-
- desc.args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE;
- desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
- desc.arginfo = QCOM_SCM_ARGS(2);
-
- return qcom_scm_call(dev, &desc, NULL);
-}
-
-int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
- unsigned int *val)
-{
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_IO,
- .cmd = QCOM_SCM_IO_READ,
- .owner = ARM_SMCCC_OWNER_SIP,
- };
- struct qcom_scm_res res;
- int ret;
-
- desc.args[0] = addr;
- desc.arginfo = QCOM_SCM_ARGS(1);
-
- ret = qcom_scm_call(dev, &desc, &res);
- if (ret >= 0)
- *val = res.result[0];
-
- return ret < 0 ? ret : 0;
-}
-
-int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)
-{
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_IO,
- .cmd = QCOM_SCM_IO_WRITE,
- .owner = ARM_SMCCC_OWNER_SIP,
- };
-
- desc.args[0] = addr;
- desc.args[1] = val;
- desc.arginfo = QCOM_SCM_ARGS(2);
-
- return qcom_scm_call(dev, &desc, NULL);
-}
-
-int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool en)
-{
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_SMMU_PROGRAM,
- .cmd = QCOM_SCM_SMMU_CONFIG_ERRATA1,
- .owner = ARM_SMCCC_OWNER_SIP,
- };
-
- desc.args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL;
- desc.args[1] = en;
- desc.arginfo = QCOM_SCM_ARGS(2);
-
- return qcom_scm_call_atomic(dev, &desc, NULL);
-}
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 5ba4c85..895f148 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -16,6 +16,7 @@
#include <linux/of_platform.h>
#include <linux/clk.h>
#include <linux/reset-controller.h>
+#include <linux/arm-smccc.h>

#include "qcom_scm.h"

@@ -49,6 +50,28 @@ struct qcom_scm_mem_map_info {
__le64 mem_size;
};

+#define QCOM_SCM_FLAG_COLDBOOT_CPU0 0x00
+#define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01
+#define QCOM_SCM_FLAG_COLDBOOT_CPU2 0x08
+#define QCOM_SCM_FLAG_COLDBOOT_CPU3 0x20
+
+#define QCOM_SCM_FLAG_WARMBOOT_CPU0 0x04
+#define QCOM_SCM_FLAG_WARMBOOT_CPU1 0x02
+#define QCOM_SCM_FLAG_WARMBOOT_CPU2 0x10
+#define QCOM_SCM_FLAG_WARMBOOT_CPU3 0x40
+
+struct qcom_scm_wb_entry {
+ int flag;
+ void *entry;
+};
+
+static struct qcom_scm_wb_entry qcom_scm_wb[] = {
+ { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 },
+ { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 },
+ { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 },
+ { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 },
+};
+
static struct qcom_scm *__scm;

static int qcom_scm_clk_enable(void)
@@ -94,7 +117,39 @@ static void qcom_scm_clk_disable(void)
*/
int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
{
- return __qcom_scm_set_warm_boot_addr(__scm->dev, entry, cpus);
+ int ret;
+ int flags = 0;
+ int cpu;
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_BOOT,
+ .cmd = QCOM_SCM_BOOT_SET_ADDR,
+ .arginfo = QCOM_SCM_ARGS(2),
+ };
+
+ /*
+ * Reassign only if we are switching from hotplug entry point
+ * to cpuidle entry point or vice versa.
+ */
+ for_each_cpu(cpu, cpus) {
+ if (entry == qcom_scm_wb[cpu].entry)
+ continue;
+ flags |= qcom_scm_wb[cpu].flag;
+ }
+
+ /* No change in entry function */
+ if (!flags)
+ return 0;
+
+ desc.args[0] = flags;
+ desc.args[1] = virt_to_phys(entry);
+
+ ret = qcom_scm_call(__scm->dev, &desc, NULL);
+ if (!ret) {
+ for_each_cpu(cpu, cpus)
+ qcom_scm_wb[cpu].entry = entry;
+ }
+
+ return ret;
}
EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);

@@ -108,8 +163,35 @@ EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
*/
int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
{
- return __qcom_scm_set_cold_boot_addr(__scm ? __scm->dev : NULL, entry,
- cpus);
+ int flags = 0;
+ int cpu;
+ int scm_cb_flags[] = {
+ QCOM_SCM_FLAG_COLDBOOT_CPU0,
+ QCOM_SCM_FLAG_COLDBOOT_CPU1,
+ QCOM_SCM_FLAG_COLDBOOT_CPU2,
+ QCOM_SCM_FLAG_COLDBOOT_CPU3,
+ };
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_BOOT,
+ .cmd = QCOM_SCM_BOOT_SET_ADDR,
+ .arginfo = QCOM_SCM_ARGS(2),
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+
+ if (!cpus || (cpus && cpumask_empty(cpus)))
+ return -EINVAL;
+
+ for_each_cpu(cpu, cpus) {
+ if (cpu < ARRAY_SIZE(scm_cb_flags))
+ flags |= scm_cb_flags[cpu];
+ else
+ set_cpu_present(cpu, false);
+ }
+
+ desc.args[0] = flags;
+ desc.args[1] = virt_to_phys(entry);
+
+ return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
}
EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);

@@ -123,16 +205,52 @@ EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
*/
void qcom_scm_cpu_power_down(u32 flags)
{
- __qcom_scm_cpu_power_down(__scm ? __scm->dev : NULL, flags);
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_BOOT,
+ .cmd = QCOM_SCM_BOOT_TERMINATE_PC,
+ .args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK,
+ .arginfo = QCOM_SCM_ARGS(1),
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+
+ qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
}
EXPORT_SYMBOL(qcom_scm_cpu_power_down);

int qcom_scm_set_remote_state(u32 state, u32 id)
{
- return __qcom_scm_set_remote_state(__scm->dev, state, id);
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_BOOT,
+ .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE,
+ .arginfo = QCOM_SCM_ARGS(2),
+ .args[0] = state,
+ .args[1] = id,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+ struct qcom_scm_res res;
+ int ret;
+
+ ret = qcom_scm_call(__scm->dev, &desc, &res);
+
+ return ret ? : res.result[0];
}
EXPORT_SYMBOL(qcom_scm_set_remote_state);

+static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
+{
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_BOOT,
+ .cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE,
+ .arginfo = QCOM_SCM_ARGS(2),
+ .args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+
+ desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
+
+ return qcom_scm_call(__scm->dev, &desc, NULL);
+}
+
static void qcom_scm_set_download_mode(bool enable)
{
bool avail;
@@ -144,8 +262,8 @@ static void qcom_scm_set_download_mode(bool enable)
if (avail) {
ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
} else if (__scm->dload_mode_addr) {
- ret = __qcom_scm_io_writel(__scm->dev, __scm->dload_mode_addr,
- enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0);
+ ret = qcom_scm_io_writel(__scm->dload_mode_addr,
+ enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0);
} else {
dev_err(__scm->dev,
"No available mechanism for setting download mode\n");
@@ -172,6 +290,14 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size)
dma_addr_t mdata_phys;
void *mdata_buf;
int ret;
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_PIL,
+ .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,
+ .arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW),
+ .args[0] = peripheral,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+ struct qcom_scm_res res;

/*
* During the scm call memory protection will be enabled for the meta
@@ -190,14 +316,16 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size)
if (ret)
goto free_metadata;

- ret = __qcom_scm_pas_init_image(__scm->dev, peripheral, mdata_phys);
+ desc.args[1] = mdata_phys;
+
+ ret = qcom_scm_call(__scm->dev, &desc, &res);

qcom_scm_clk_disable();

free_metadata:
dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys);

- return ret;
+ return ret ? : res.result[0];
}
EXPORT_SYMBOL(qcom_scm_pas_init_image);

@@ -213,15 +341,25 @@ EXPORT_SYMBOL(qcom_scm_pas_init_image);
int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size)
{
int ret;
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_PIL,
+ .cmd = QCOM_SCM_PIL_PAS_MEM_SETUP,
+ .arginfo = QCOM_SCM_ARGS(3),
+ .args[0] = peripheral,
+ .args[1] = addr,
+ .args[2] = size,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+ struct qcom_scm_res res;

ret = qcom_scm_clk_enable();
if (ret)
return ret;

- ret = __qcom_scm_pas_mem_setup(__scm->dev, peripheral, addr, size);
+ ret = qcom_scm_call(__scm->dev, &desc, &res);
qcom_scm_clk_disable();

- return ret;
+ return ret ? : res.result[0];
}
EXPORT_SYMBOL(qcom_scm_pas_mem_setup);

@@ -235,15 +373,23 @@ EXPORT_SYMBOL(qcom_scm_pas_mem_setup);
int qcom_scm_pas_auth_and_reset(u32 peripheral)
{
int ret;
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_PIL,
+ .cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
+ .arginfo = QCOM_SCM_ARGS(1),
+ .args[0] = peripheral,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+ struct qcom_scm_res res;

ret = qcom_scm_clk_enable();
if (ret)
return ret;

- ret = __qcom_scm_pas_auth_and_reset(__scm->dev, peripheral);
+ ret = qcom_scm_call(__scm->dev, &desc, &res);
qcom_scm_clk_disable();

- return ret;
+ return ret ? : res.result[0];
}
EXPORT_SYMBOL(qcom_scm_pas_auth_and_reset);

@@ -256,15 +402,24 @@ EXPORT_SYMBOL(qcom_scm_pas_auth_and_reset);
int qcom_scm_pas_shutdown(u32 peripheral)
{
int ret;
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_PIL,
+ .cmd = QCOM_SCM_PIL_PAS_SHUTDOWN,
+ .arginfo = QCOM_SCM_ARGS(1),
+ .args[0] = peripheral,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+ struct qcom_scm_res res;

ret = qcom_scm_clk_enable();
if (ret)
return ret;

- ret = __qcom_scm_pas_shutdown(__scm->dev, peripheral);
+ ret = qcom_scm_call(__scm->dev, &desc, &res);
+
qcom_scm_clk_disable();

- return ret;
+ return ret ? : res.result[0];
}
EXPORT_SYMBOL(qcom_scm_pas_shutdown);

@@ -278,16 +433,44 @@ EXPORT_SYMBOL(qcom_scm_pas_shutdown);
bool qcom_scm_pas_supported(u32 peripheral)
{
int ret;
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_PIL,
+ .cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED,
+ .arginfo = QCOM_SCM_ARGS(1),
+ .args[0] = peripheral,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+ struct qcom_scm_res res;

ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
QCOM_SCM_PIL_PAS_IS_SUPPORTED);
if (ret <= 0)
return false;

- return __qcom_scm_pas_supported(__scm->dev, peripheral);
+ ret = qcom_scm_call(__scm->dev, &desc, &res);
+
+ return ret ? false : !!res.result[0];
}
EXPORT_SYMBOL(qcom_scm_pas_supported);

+static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
+{
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_PIL,
+ .cmd = QCOM_SCM_PIL_PAS_MSS_RESET,
+ .arginfo = QCOM_SCM_ARGS(2),
+ .args[0] = reset,
+ .args[1] = 0,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+ struct qcom_scm_res res;
+ int ret;
+
+ ret = qcom_scm_call(__scm->dev, &desc, &res);
+
+ return ret ? : res.result[0];
+}
+
static int qcom_scm_pas_reset_assert(struct reset_controller_dev *rcdev,
unsigned long idx)
{
@@ -313,13 +496,38 @@ static const struct reset_control_ops qcom_scm_pas_reset_ops = {

int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
{
- return __qcom_scm_io_readl(__scm->dev, addr, val);
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_IO,
+ .cmd = QCOM_SCM_IO_READ,
+ .arginfo = QCOM_SCM_ARGS(1),
+ .args[0] = addr,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+ struct qcom_scm_res res;
+ int ret;
+
+
+ ret = qcom_scm_call(__scm->dev, &desc, &res);
+ if (ret >= 0)
+ *val = res.result[0];
+
+ return ret < 0 ? ret : 0;
}
EXPORT_SYMBOL(qcom_scm_io_readl);

int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
{
- return __qcom_scm_io_writel(__scm->dev, addr, val);
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_IO,
+ .cmd = QCOM_SCM_IO_WRITE,
+ .arginfo = QCOM_SCM_ARGS(2),
+ .args[0] = addr,
+ .args[1] = val,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+
+
+ return qcom_scm_call(__scm->dev, &desc, NULL);
}
EXPORT_SYMBOL(qcom_scm_io_writel);

@@ -338,22 +546,101 @@ EXPORT_SYMBOL(qcom_scm_restore_sec_cfg_available);

int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
{
- return __qcom_scm_restore_sec_cfg(__scm->dev, device_id, spare);
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_MP,
+ .cmd = QCOM_SCM_MP_RESTORE_SEC_CFG,
+ .arginfo = QCOM_SCM_ARGS(2),
+ .args[0] = device_id,
+ .args[1] = spare,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+ struct qcom_scm_res res;
+ int ret;
+
+ ret = qcom_scm_call(__scm->dev, &desc, &res);
+
+ return ret ? : res.result[0];
}
EXPORT_SYMBOL(qcom_scm_restore_sec_cfg);

int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
{
- return __qcom_scm_iommu_secure_ptbl_size(__scm->dev, spare, size);
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_MP,
+ .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE,
+ .arginfo = QCOM_SCM_ARGS(1),
+ .args[0] = spare,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+ struct qcom_scm_res res;
+ int ret;
+
+ ret = qcom_scm_call(__scm->dev, &desc, &res);
+
+ if (size)
+ *size = res.result[0];
+
+ return ret ? : res.result[1];
}
EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_size);

int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
{
- return __qcom_scm_iommu_secure_ptbl_init(__scm->dev, addr, size, spare);
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_MP,
+ .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT,
+ .arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL,
+ QCOM_SCM_VAL),
+ .args[0] = addr,
+ .args[1] = size,
+ .args[2] = spare,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+ int ret;
+
+ desc.args[0] = addr;
+ desc.args[1] = size;
+ desc.args[2] = spare;
+ desc.arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL,
+ QCOM_SCM_VAL);
+
+ ret = qcom_scm_call(__scm->dev, &desc, NULL);
+
+ /* the pg table has been initialized already, ignore the error */
+ if (ret == -EPERM)
+ ret = 0;
+
+ return ret;
}
EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init);

+static int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
+ size_t mem_sz, phys_addr_t src, size_t src_sz,
+ phys_addr_t dest, size_t dest_sz)
+{
+ int ret;
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_MP,
+ .cmd = QCOM_SCM_MP_ASSIGN,
+ .arginfo = QCOM_SCM_ARGS(7, QCOM_SCM_RO, QCOM_SCM_VAL,
+ QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_RO,
+ QCOM_SCM_VAL, QCOM_SCM_VAL),
+ .args[0] = mem_region,
+ .args[1] = mem_sz,
+ .args[2] = src,
+ .args[3] = src_sz,
+ .args[4] = dest,
+ .args[5] = dest_sz,
+ .args[6] = 0,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+ struct qcom_scm_res res;
+
+ ret = qcom_scm_call(dev, &desc, &res);
+
+ return ret ? : res.result[0];
+}
+
/**
* qcom_scm_assign_mem() - Make a secure call to reassign memory ownership
* @mem_addr: mem region whose ownership need to be reassigned
@@ -458,7 +745,17 @@ EXPORT_SYMBOL(qcom_scm_ocmem_lock_available);
int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, u32 size,
u32 mode)
{
- return __qcom_scm_ocmem_lock(__scm->dev, id, offset, size, mode);
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_OCMEM,
+ .cmd = QCOM_SCM_OCMEM_LOCK_CMD,
+ .args[0] = id,
+ .args[1] = offset,
+ .args[2] = size,
+ .args[3] = mode,
+ .arginfo = QCOM_SCM_ARGS(4),
+ };
+
+ return qcom_scm_call(__scm->dev, &desc, NULL);
}
EXPORT_SYMBOL(qcom_scm_ocmem_lock);

@@ -472,7 +769,16 @@ EXPORT_SYMBOL(qcom_scm_ocmem_lock);
*/
int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size)
{
- return __qcom_scm_ocmem_unlock(__scm->dev, id, offset, size);
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_OCMEM,
+ .cmd = QCOM_SCM_OCMEM_UNLOCK_CMD,
+ .args[0] = id,
+ .args[1] = offset,
+ .args[2] = size,
+ .arginfo = QCOM_SCM_ARGS(3),
+ };
+
+ return qcom_scm_call(__scm->dev, &desc, NULL);
}
EXPORT_SYMBOL(qcom_scm_ocmem_unlock);

@@ -507,20 +813,56 @@ EXPORT_SYMBOL(qcom_scm_hdcp_available);
*/
int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
{
- int ret = qcom_scm_clk_enable();
+ int ret;
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_HDCP,
+ .cmd = QCOM_SCM_HDCP_INVOKE,
+ .arginfo = QCOM_SCM_ARGS(10),
+ .args = {
+ req[0].addr,
+ req[0].val,
+ req[1].addr,
+ req[1].val,
+ req[2].addr,
+ req[2].val,
+ req[3].addr,
+ req[3].val,
+ req[4].addr,
+ req[4].val
+ },
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+ struct qcom_scm_res res;
+
+ if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
+ return -ERANGE;

+ ret = qcom_scm_clk_enable();
if (ret)
return ret;

- ret = __qcom_scm_hdcp_req(__scm->dev, req, req_cnt, resp);
+ ret = qcom_scm_call(__scm->dev, &desc, &res);
+ *resp = res.result[0];
+
qcom_scm_clk_disable();
+
return ret;
}
EXPORT_SYMBOL(qcom_scm_hdcp_req);

int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
{
- return __qcom_scm_qsmmu500_wait_safe_toggle(__scm->dev, en);
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_SMMU_PROGRAM,
+ .cmd = QCOM_SCM_SMMU_CONFIG_ERRATA1,
+ .arginfo = QCOM_SCM_ARGS(2),
+ .args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL,
+ .args[1] = en,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+
+
+ return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
}
EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle);

diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h
index 56ace3b..9b7b357 100644
--- a/drivers/firmware/qcom_scm.h
+++ b/drivers/firmware/qcom_scm.h
@@ -3,19 +3,64 @@
*/
#ifndef __QCOM_SCM_INT_H
#define __QCOM_SCM_INT_H
+#define MAX_QCOM_SCM_ARGS 10
+#define MAX_QCOM_SCM_RETS 3
+
+enum qcom_scm_arg_types {
+ QCOM_SCM_VAL,
+ QCOM_SCM_RO,
+ QCOM_SCM_RW,
+ QCOM_SCM_BUFVAL,
+};
+
+#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
+ (((a) & 0x3) << 4) | \
+ (((b) & 0x3) << 6) | \
+ (((c) & 0x3) << 8) | \
+ (((d) & 0x3) << 10) | \
+ (((e) & 0x3) << 12) | \
+ (((f) & 0x3) << 14) | \
+ (((g) & 0x3) << 16) | \
+ (((h) & 0x3) << 18) | \
+ (((i) & 0x3) << 20) | \
+ (((j) & 0x3) << 22) | \
+ ((num) & 0xf))
+
+#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
+
+
+/**
+ * struct qcom_scm_desc
+ * @arginfo: Metadata describing the arguments in args[]
+ * @args: The array of arguments for the secure syscall
+ */
+struct qcom_scm_desc {
+ u32 svc;
+ u32 cmd;
+ u32 arginfo;
+ u64 args[MAX_QCOM_SCM_ARGS];
+ u32 owner;
+};
+
+/**
+ * struct qcom_scm_res
+ * @result: The values returned by the secure syscall
+ */
+struct qcom_scm_res {
+ u64 result[MAX_QCOM_SCM_RETS];
+};
+
+extern int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
+ struct qcom_scm_res *res);
+extern int qcom_scm_call_atomic(struct device *dev,
+ const struct qcom_scm_desc *desc,
+ struct qcom_scm_res *res);

#define QCOM_SCM_SVC_BOOT 0x01
#define QCOM_SCM_BOOT_SET_ADDR 0x01
#define QCOM_SCM_BOOT_TERMINATE_PC 0x02
#define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a
-extern int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
- const cpumask_t *cpus);
-extern int __qcom_scm_set_cold_boot_addr(struct device *dev, void *entry,
- const cpumask_t *cpus);
-extern void __qcom_scm_cpu_power_down(struct device *dev, u32 flags);
-extern int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id);
-extern int __qcom_scm_set_dload_mode(struct device *dev, bool enable);
#define QCOM_SCM_FLUSH_FLAG_MASK 0x3

#define QCOM_SCM_SVC_PIL 0x02
@@ -25,20 +70,10 @@ extern int __qcom_scm_set_dload_mode(struct device *dev, bool enable);
#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06
#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07
#define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a
-extern bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral);
-extern int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
- dma_addr_t metadata_phys);
-extern int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
- phys_addr_t addr, phys_addr_t size);
-extern int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral);
-extern int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral);
-extern int __qcom_scm_pas_mss_reset(struct device *dev, bool reset);

#define QCOM_SCM_SVC_IO 0x05
#define QCOM_SCM_IO_READ 0x01
#define QCOM_SCM_IO_WRITE 0x02
-extern int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, unsigned int *val);
-extern int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val);

#define QCOM_SCM_SVC_INFO 0x06
#define QCOM_SCM_INFO_IS_CALL_AVAIL 0x01
@@ -50,35 +85,17 @@ extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 0x03
#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 0x04
#define QCOM_SCM_MP_ASSIGN 0x16
-extern int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
- u32 spare);
-extern int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
- size_t *size);
-extern int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr,
- u32 size, u32 spare);
-extern int __qcom_scm_assign_mem(struct device *dev,
- phys_addr_t mem_region, size_t mem_sz,
- phys_addr_t src, size_t src_sz,
- phys_addr_t dest, size_t dest_sz);

#define QCOM_SCM_SVC_OCMEM 0x0f
#define QCOM_SCM_OCMEM_LOCK_CMD 0x01
#define QCOM_SCM_OCMEM_UNLOCK_CMD 0x02
-extern int __qcom_scm_ocmem_lock(struct device *dev, u32 id, u32 offset,
- u32 size, u32 mode);
-extern int __qcom_scm_ocmem_unlock(struct device *dev, u32 id, u32 offset,
- u32 size);

#define QCOM_SCM_SVC_HDCP 0x11
#define QCOM_SCM_HDCP_INVOKE 0x01
-extern int __qcom_scm_hdcp_req(struct device *dev,
- struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp);

#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
#define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03
#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02
-extern int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev,
- bool enable);

extern void __qcom_scm_init(void);

--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

2020-01-07 21:20:33

by Elliot Berman

[permalink] [raw]
Subject: [PATCH v5 06/17] firmware: qcom_scm-64: Add SCM results struct

Remove knowledge of arm_smccc_res struct from client wrappers so that
client wrappers only work QCOM SCM data structures. SCM calls may have
up to 3 arguments, so qcom_scm_call_smccc is responsible now for filling
those 3 arguments accordingly. This is necessary to support merging
legacy and SMC conventions in an upcoming patch.

Change-Id: I9712f75f6bea0a6528ccd5a69bc1602493574e19
Tested-by: Brian Masney <[email protected]> # arm32
Tested-by: Stephan Gerhold <[email protected]>
Signed-off-by: Elliot Berman <[email protected]>
---
drivers/firmware/qcom_scm-64.c | 93 +++++++++++++++++++++++-------------------
1 file changed, 50 insertions(+), 43 deletions(-)

diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
index 7b7aa88..e0e6530 100644
--- a/drivers/firmware/qcom_scm-64.c
+++ b/drivers/firmware/qcom_scm-64.c
@@ -45,7 +45,6 @@ enum qcom_scm_arg_types {
* struct qcom_scm_desc
* @arginfo: Metadata describing the arguments in args[]
* @args: The array of arguments for the secure syscall
- * @res: The values returned by the secure syscall
*/
struct qcom_scm_desc {
u32 svc;
@@ -55,6 +54,14 @@ struct qcom_scm_desc {
u32 owner;
};

+/**
+ * struct qcom_scm_res
+ * @result: The values returned by the secure syscall
+ */
+struct qcom_scm_res {
+ u64 result[MAX_QCOM_SCM_RETS];
+};
+
static u64 qcom_smccc_convention = -1;
static DEFINE_MUTEX(qcom_scm_lock);

@@ -116,7 +123,7 @@ static void __scm_smc_do(const struct qcom_scm_desc *desc,
}

static int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
- struct arm_smccc_res *res, bool atomic)
+ struct qcom_scm_res *res, bool atomic)
{
int arglen = desc->arginfo & 0xf;
int i;
@@ -125,6 +132,7 @@ static int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
void *args_virt = NULL;
size_t alloc_len;
gfp_t flag = atomic ? GFP_ATOMIC : GFP_KERNEL;
+ struct arm_smccc_res smc_res;

if (unlikely(arglen > SCM_SMC_N_REG_ARGS)) {
alloc_len = SCM_SMC_N_EXT_ARGS * sizeof(u64);
@@ -158,17 +166,20 @@ static int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
x5 = args_phys;
}

- __scm_smc_do(desc, res, x5, atomic);
+ __scm_smc_do(desc, &smc_res, x5, atomic);

if (args_virt) {
dma_unmap_single(dev, args_phys, alloc_len, DMA_TO_DEVICE);
kfree(args_virt);
}

- if ((long)res->a0 < 0)
- return qcom_scm_remap_error(res->a0);
+ if (res) {
+ res->result[0] = smc_res.a1;
+ res->result[1] = smc_res.a2;
+ res->result[2] = smc_res.a3;
+ }

- return 0;
+ return (long)smc_res.a0 ? qcom_scm_remap_error(smc_res.a0) : 0;
}

/**
@@ -182,7 +193,7 @@ static int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
* This should *only* be called in pre-emptible context.
*/
static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
- struct arm_smccc_res *res)
+ struct qcom_scm_res *res)
{
might_sleep();
return __scm_smc_call(dev, desc, res, false);
@@ -201,7 +212,7 @@ static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
*/
static int qcom_scm_call_atomic(struct device *dev,
const struct qcom_scm_desc *desc,
- struct arm_smccc_res *res)
+ struct qcom_scm_res *res)
{
return __scm_smc_call(dev, desc, res, true);
}
@@ -254,7 +265,7 @@ int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
.cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
.owner = ARM_SMCCC_OWNER_SIP,
};
- struct arm_smccc_res res;
+ struct qcom_scm_res res;

desc.arginfo = QCOM_SCM_ARGS(1);
desc.args[0] = SCM_SMC_FNID(svc_id, cmd_id) |
@@ -262,7 +273,7 @@ int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)

ret = qcom_scm_call(dev, &desc, &res);

- return ret ? : res.a1;
+ return ret ? : res.result[0];
}

int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
@@ -274,7 +285,7 @@ int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
.cmd = QCOM_SCM_HDCP_INVOKE,
.owner = ARM_SMCCC_OWNER_SIP,
};
- struct arm_smccc_res res;
+ struct qcom_scm_res res;

if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
return -ERANGE;
@@ -292,7 +303,7 @@ int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
desc.arginfo = QCOM_SCM_ARGS(10);

ret = qcom_scm_call(dev, &desc, &res);
- *resp = res.a1;
+ *resp = res.result[0];

return ret;
}
@@ -336,14 +347,14 @@ bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral)
.cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED,
.owner = ARM_SMCCC_OWNER_SIP,
};
- struct arm_smccc_res res;
+ struct qcom_scm_res res;

desc.args[0] = peripheral;
desc.arginfo = QCOM_SCM_ARGS(1);

ret = qcom_scm_call(dev, &desc, &res);

- return ret ? false : !!res.a1;
+ return ret ? false : !!res.result[0];
}

int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
@@ -355,7 +366,7 @@ int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
.cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,
.owner = ARM_SMCCC_OWNER_SIP,
};
- struct arm_smccc_res res;
+ struct qcom_scm_res res;

desc.args[0] = peripheral;
desc.args[1] = metadata_phys;
@@ -363,7 +374,7 @@ int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,

ret = qcom_scm_call(dev, &desc, &res);

- return ret ? : res.a1;
+ return ret ? : res.result[0];
}

int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
@@ -375,7 +386,7 @@ int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
.cmd = QCOM_SCM_PIL_PAS_MEM_SETUP,
.owner = ARM_SMCCC_OWNER_SIP,
};
- struct arm_smccc_res res;
+ struct qcom_scm_res res;

desc.args[0] = peripheral;
desc.args[1] = addr;
@@ -384,7 +395,7 @@ int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,

ret = qcom_scm_call(dev, &desc, &res);

- return ret ? : res.a1;
+ return ret ? : res.result[0];
}

int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral)
@@ -395,14 +406,14 @@ int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral)
.cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
.owner = ARM_SMCCC_OWNER_SIP,
};
- struct arm_smccc_res res;
+ struct qcom_scm_res res;

desc.args[0] = peripheral;
desc.arginfo = QCOM_SCM_ARGS(1);

ret = qcom_scm_call(dev, &desc, &res);

- return ret ? : res.a1;
+ return ret ? : res.result[0];
}

int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral)
@@ -413,14 +424,14 @@ int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral)
.cmd = QCOM_SCM_PIL_PAS_SHUTDOWN,
.owner = ARM_SMCCC_OWNER_SIP,
};
- struct arm_smccc_res res;
+ struct qcom_scm_res res;

desc.args[0] = peripheral;
desc.arginfo = QCOM_SCM_ARGS(1);

ret = qcom_scm_call(dev, &desc, &res);

- return ret ? : res.a1;
+ return ret ? : res.result[0];
}

int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
@@ -430,7 +441,7 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
.cmd = QCOM_SCM_PIL_PAS_MSS_RESET,
.owner = ARM_SMCCC_OWNER_SIP,
};
- struct arm_smccc_res res;
+ struct qcom_scm_res res;
int ret;

desc.args[0] = reset;
@@ -439,7 +450,7 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)

ret = qcom_scm_call(dev, &desc, &res);

- return ret ? : res.a1;
+ return ret ? : res.result[0];
}

int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
@@ -449,7 +460,7 @@ int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
.cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE,
.owner = ARM_SMCCC_OWNER_SIP,
};
- struct arm_smccc_res res;
+ struct qcom_scm_res res;
int ret;

desc.args[0] = state;
@@ -458,7 +469,7 @@ int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)

ret = qcom_scm_call(dev, &desc, &res);

- return ret ? : res.a1;
+ return ret ? : res.result[0];
}

int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
@@ -471,7 +482,7 @@ int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
.cmd = QCOM_SCM_MP_ASSIGN,
.owner = ARM_SMCCC_OWNER_SIP,
};
- struct arm_smccc_res res;
+ struct qcom_scm_res res;

desc.args[0] = mem_region;
desc.args[1] = mem_sz;
@@ -487,7 +498,7 @@ int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,

ret = qcom_scm_call(dev, &desc, &res);

- return ret ? : res.a1;
+ return ret ? : res.result[0];
}

int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare)
@@ -497,7 +508,7 @@ int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare)
.cmd = QCOM_SCM_MP_RESTORE_SEC_CFG,
.owner = ARM_SMCCC_OWNER_SIP,
};
- struct arm_smccc_res res;
+ struct qcom_scm_res res;
int ret;

desc.args[0] = device_id;
@@ -506,7 +517,7 @@ int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare)

ret = qcom_scm_call(dev, &desc, &res);

- return ret ? : res.a1;
+ return ret ? : res.result[0];
}

int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
@@ -517,7 +528,7 @@ int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
.cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE,
.owner = ARM_SMCCC_OWNER_SIP,
};
- struct arm_smccc_res res;
+ struct qcom_scm_res res;
int ret;

desc.args[0] = spare;
@@ -526,9 +537,9 @@ int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
ret = qcom_scm_call(dev, &desc, &res);

if (size)
- *size = res.a1;
+ *size = res.result[0];

- return ret ? : res.a2;
+ return ret ? : res.result[1];
}

int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,
@@ -539,7 +550,6 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,
.cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT,
.owner = ARM_SMCCC_OWNER_SIP,
};
- struct arm_smccc_res res;
int ret;

desc.args[0] = addr;
@@ -548,7 +558,7 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,
desc.arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL,
QCOM_SCM_VAL);

- ret = qcom_scm_call(dev, &desc, &res);
+ ret = qcom_scm_call(dev, &desc, NULL);

/* the pg table has been initialized already, ignore the error */
if (ret == -EPERM)
@@ -564,13 +574,12 @@ int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
.cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE,
.owner = ARM_SMCCC_OWNER_SIP,
};
- struct arm_smccc_res res;

desc.args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE;
desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
desc.arginfo = QCOM_SCM_ARGS(2);

- return qcom_scm_call(dev, &desc, &res);
+ return qcom_scm_call(dev, &desc, NULL);
}

int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
@@ -581,7 +590,7 @@ int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
.cmd = QCOM_SCM_IO_READ,
.owner = ARM_SMCCC_OWNER_SIP,
};
- struct arm_smccc_res res;
+ struct qcom_scm_res res;
int ret;

desc.args[0] = addr;
@@ -589,7 +598,7 @@ int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,

ret = qcom_scm_call(dev, &desc, &res);
if (ret >= 0)
- *val = res.a1;
+ *val = res.result[0];

return ret < 0 ? ret : 0;
}
@@ -601,13 +610,12 @@ int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)
.cmd = QCOM_SCM_IO_WRITE,
.owner = ARM_SMCCC_OWNER_SIP,
};
- struct arm_smccc_res res;

desc.args[0] = addr;
desc.args[1] = val;
desc.arginfo = QCOM_SCM_ARGS(2);

- return qcom_scm_call(dev, &desc, &res);
+ return qcom_scm_call(dev, &desc, NULL);
}

int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool en)
@@ -617,11 +625,10 @@ int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool en)
.cmd = QCOM_SCM_SMMU_CONFIG_ERRATA1,
.owner = ARM_SMCCC_OWNER_SIP,
};
- struct arm_smccc_res res;

desc.args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL;
desc.args[1] = en;
desc.arginfo = QCOM_SCM_ARGS(2);

- return qcom_scm_call_atomic(dev, &desc, &res);
+ return qcom_scm_call_atomic(dev, &desc, NULL);
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

2020-01-07 21:20:34

by Elliot Berman

[permalink] [raw]
Subject: [PATCH v5 08/17] firmware: qcom_scm-64: Improve SMC convention detection

Improve the calling convention detection to use
__qcom_scm_is_call_available() and not blindly assume 32-bit mode if
the checks fails. BUG() if neither 32-bit or 64-bit mode works.

Change-Id: I66beec550d05afde6c680d256183e8ad207d7268
Tested-by: Brian Masney <[email protected]> # arm32
Tested-by: Stephan Gerhold <[email protected]>
Signed-off-by: Elliot Berman <[email protected]>
---
drivers/firmware/qcom_scm-64.c | 41 +++++++++++++++++++++++++++--------------
1 file changed, 27 insertions(+), 14 deletions(-)

diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
index 3ae171a..6bc7f69 100644
--- a/drivers/firmware/qcom_scm-64.c
+++ b/drivers/firmware/qcom_scm-64.c
@@ -336,21 +336,34 @@ int __qcom_scm_ocmem_unlock(struct device *dev, uint32_t id, uint32_t offset,

void __qcom_scm_init(void)
{
- u64 cmd;
- struct arm_smccc_res res;
- u32 fnid = SCM_SMC_FNID(QCOM_SCM_SVC_INFO, QCOM_SCM_INFO_IS_CALL_AVAIL);
-
- /* First try a SMC64 call */
- cmd = ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64,
- ARM_SMCCC_OWNER_SIP, fnid);
-
- arm_smccc_smc(cmd, QCOM_SCM_ARGS(1), cmd & (~BIT(ARM_SMCCC_TYPE_SHIFT)),
- 0, 0, 0, 0, 0, &res);
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_INFO,
+ .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
+ .args[0] = SCM_SMC_FNID(QCOM_SCM_SVC_INFO,
+ QCOM_SCM_INFO_IS_CALL_AVAIL) |
+ (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT),
+ .arginfo = QCOM_SCM_ARGS(1),
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+ struct qcom_scm_res res;
+ int ret;

- if (!res.a0 && res.a1)
- qcom_smccc_convention = ARM_SMCCC_SMC_64;
- else
- qcom_smccc_convention = ARM_SMCCC_SMC_32;
+ qcom_smccc_convention = ARM_SMCCC_SMC_64;
+ // Device isn't required as there is only one argument - no device
+ // needed to dma_map_single to secure world
+ ret = qcom_scm_call_atomic(NULL, &desc, &res);
+ if (!ret && res.result[0] == 1)
+ goto out;
+
+ qcom_smccc_convention = ARM_SMCCC_SMC_32;
+ ret = qcom_scm_call_atomic(NULL, &desc, &res);
+ if (!ret && res.result[0] == 1)
+ goto out;
+
+ qcom_smccc_convention = -1;
+ BUG();
+out:
+ pr_info("QCOM SCM SMC Convention: %lld\n", qcom_smccc_convention);
}

bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

2020-01-07 21:20:40

by Elliot Berman

[permalink] [raw]
Subject: [PATCH v5 10/17] firmware: qcom_scm-32: Add funcnum IDs

Add SCM_LEGACY_FNID macro to qcom_scm-32.

Change-Id: I385f0b5ba31cb14e304617d5aa67b37dc3c33c9c
Tested-by: Brian Masney <[email protected]> # arm32
Tested-by: Stephan Gerhold <[email protected]>
Signed-off-by: Elliot Berman <[email protected]>
---
drivers/firmware/qcom_scm-32.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c
index 362d042..fcbe9e0 100644
--- a/drivers/firmware/qcom_scm-32.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -39,6 +39,8 @@ static struct qcom_scm_entry qcom_scm_wb[] = {

static DEFINE_MUTEX(qcom_scm_lock);

+#define SCM_LEGACY_FNID(s, c) (((s) << 10) | ((c) & 0x3ff))
+
/**
* struct scm_legacy_command - one SCM command buffer
* @len: total available memory for command and response
@@ -168,7 +170,7 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id,
cmd->buf_offset = cpu_to_le32(sizeof(*cmd));
cmd->resp_hdr_offset = cpu_to_le32(sizeof(*cmd) + cmd_len);

- cmd->id = cpu_to_le32((svc_id << 10) | cmd_id);
+ cmd->id = cpu_to_le32(SCM_LEGACY_FNID(svc_id, cmd_id));
if (cmd_buf)
memcpy(scm_legacy_get_command_buffer(cmd), cmd_buf, cmd_len);

@@ -209,7 +211,7 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id,
#define SCM_LEGACY_CLASS_REGISTER (0x2 << 8)
#define SCM_LEGACY_MASK_IRQS BIT(5)
#define SCM_LEGACY_ATOMIC_ID(svc, cmd, n) \
- (((((svc) << 10)|((cmd) & 0x3ff)) << 12) | \
+ ((SCM_LEGACY_FNID(svc, cmd) << 12) | \
SCM_LEGACY_CLASS_REGISTER | \
SCM_LEGACY_MASK_IRQS | \
(n & 0xf))
@@ -350,7 +352,7 @@ void __qcom_scm_cpu_power_down(u32 flags)
int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
{
int ret;
- __le32 svc_cmd = cpu_to_le32((svc_id << 10) | cmd_id);
+ __le32 svc_cmd = cpu_to_le32(SCM_LEGACY_FNID(svc_id, cmd_id));
__le32 ret_val = 0;

ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_SCM_INFO_IS_CALL_AVAIL,
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

2020-01-07 21:20:42

by Elliot Berman

[permalink] [raw]
Subject: [PATCH v5 03/17] firmware: qcom_scm: Remove unused qcom_scm_get_version

Remove unused qcom_scm_get_version.

Change-Id: I7e638d3ece7a2d52b51f570bb680cf3c5dcdc347
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Vinod Koul <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Tested-by: Brian Masney <[email protected]> # arm32
Tested-by: Stephan Gerhold <[email protected]>
Signed-off-by: Elliot Berman <[email protected]>
---
drivers/firmware/qcom_scm-32.c | 36 ------------------------------------
include/linux/qcom_scm.h | 2 --
2 files changed, 38 deletions(-)

diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c
index 6e62f73..8b57240 100644
--- a/drivers/firmware/qcom_scm-32.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -292,42 +292,6 @@ static s32 qcom_scm_call_atomic2(u32 svc, u32 cmd, u32 arg1, u32 arg2)
return r0;
}

-u32 qcom_scm_get_version(void)
-{
- int context_id;
- static u32 version = -1;
- register u32 r0 asm("r0");
- register u32 r1 asm("r1");
-
- if (version != -1)
- return version;
-
- mutex_lock(&qcom_scm_lock);
-
- r0 = 0x1 << 8;
- r1 = (u32)&context_id;
- do {
- asm volatile(
- __asmeq("%0", "r0")
- __asmeq("%1", "r1")
- __asmeq("%2", "r0")
- __asmeq("%3", "r1")
-#ifdef REQUIRES_SEC
- ".arch_extension sec\n"
-#endif
- "smc #0 @ switch to secure world\n"
- : "=r" (r0), "=r" (r1)
- : "r" (r0), "r" (r1)
- : "r2", "r3", "r12");
- } while (r0 == QCOM_SCM_INTERRUPTED);
-
- version = r1;
- mutex_unlock(&qcom_scm_lock);
-
- return version;
-}
-EXPORT_SYMBOL(qcom_scm_get_version);
-
/**
* qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
* @entry: Entry point function for the cpus
diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h
index 2c1d203..98e775d 100644
--- a/include/linux/qcom_scm.h
+++ b/include/linux/qcom_scm.h
@@ -78,7 +78,6 @@ extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
const struct qcom_scm_vmperm *newvm,
unsigned int dest_cnt);
extern void qcom_scm_cpu_power_down(u32 flags);
-extern u32 qcom_scm_get_version(void);
extern int qcom_scm_set_remote_state(u32 state, u32 id);
extern bool qcom_scm_restore_sec_cfg_available(void);
extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
@@ -123,7 +122,6 @@ static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
const struct qcom_scm_vmperm *newvm,
unsigned int dest_cnt) { return -ENODEV; }
static inline void qcom_scm_cpu_power_down(u32 flags) {}
-static inline u32 qcom_scm_get_version(void) { return 0; }
static inline u32
qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }
static inline bool qcom_scm_restore_sec_cfg_available(void) { return false; }
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

2020-01-07 21:20:45

by Elliot Berman

[permalink] [raw]
Subject: [PATCH v5 05/17] firmware: qcom_scm-64: Move svc/cmd/owner into qcom_scm_desc

Service, command, and owner IDs are all part of qcom_scm_desc struct and
have no special reason to be a function argument (or hard-coded in the
case of owner [1]). Moving them to be part of qcom_scm_desc struct improves
readability.

[1]: Example of SCM function using owner vale other than hard-coded SIP value:
https://source.codeaurora.org/quic/la/kernel/msm-4.9/tree/drivers/soc/qcom/smcinvoke.c?h=kernel.lnx.4.9.r28-rel#n35

Change-Id: I422e5b0c2c117ff4eafc80f16b34874ff86643d3
Tested-by: Brian Masney <[email protected]> # arm32
Tested-by: Stephan Gerhold <[email protected]>
Signed-off-by: Elliot Berman <[email protected]>
---
drivers/firmware/qcom_scm-64.c | 195 +++++++++++++++++++++++++----------------
1 file changed, 121 insertions(+), 74 deletions(-)

diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
index 3101f36..7b7aa88 100644
--- a/drivers/firmware/qcom_scm-64.c
+++ b/drivers/firmware/qcom_scm-64.c
@@ -48,8 +48,11 @@ enum qcom_scm_arg_types {
* @res: The values returned by the secure syscall
*/
struct qcom_scm_desc {
+ u32 svc;
+ u32 cmd;
u32 arginfo;
u64 args[MAX_QCOM_SCM_ARGS];
+ u32 owner;
};

static u64 qcom_smccc_convention = -1;
@@ -63,14 +66,16 @@ static DEFINE_MUTEX(qcom_scm_lock);
#define SCM_SMC_N_EXT_ARGS (MAX_QCOM_SCM_ARGS - SCM_SMC_N_REG_ARGS + 1)

static void __scm_smc_do_quirk(const struct qcom_scm_desc *desc,
- struct arm_smccc_res *res, u32 fn_id,
- u64 x5, u32 type)
+ struct arm_smccc_res *res, u64 x5, u32 type)
{
u64 cmd;
struct arm_smccc_quirk quirk = { .id = ARM_SMCCC_QUIRK_QCOM_A6 };

- cmd = ARM_SMCCC_CALL_VAL(type, qcom_smccc_convention,
- ARM_SMCCC_OWNER_SIP, fn_id);
+ cmd = ARM_SMCCC_CALL_VAL(
+ type,
+ qcom_smccc_convention,
+ desc->owner,
+ SCM_SMC_FNID(desc->svc, desc->cmd));

quirk.state.a6 = 0;

@@ -86,22 +91,19 @@ static void __scm_smc_do_quirk(const struct qcom_scm_desc *desc,
}

static void __scm_smc_do(const struct qcom_scm_desc *desc,
- struct arm_smccc_res *res, u32 fn_id,
- u64 x5, bool atomic)
+ struct arm_smccc_res *res, u64 x5, bool atomic)
{
int retry_count = 0;

if (atomic) {
- __scm_smc_do_quirk(desc, res, fn_id, x5,
- ARM_SMCCC_FAST_CALL);
+ __scm_smc_do_quirk(desc, res, x5, ARM_SMCCC_FAST_CALL);
return;
}

do {
mutex_lock(&qcom_scm_lock);

- __scm_smc_do_quirk(desc, res, fn_id, x5,
- ARM_SMCCC_STD_CALL);
+ __scm_smc_do_quirk(desc, res, x5, ARM_SMCCC_STD_CALL);

mutex_unlock(&qcom_scm_lock);

@@ -113,13 +115,11 @@ static void __scm_smc_do(const struct qcom_scm_desc *desc,
} while (res->a0 == QCOM_SCM_V2_EBUSY);
}

-static int __scm_smc_call(struct device *dev, u32 svc_id, u32 cmd_id,
- const struct qcom_scm_desc *desc,
- struct arm_smccc_res *res, bool atomic)
+static int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
+ struct arm_smccc_res *res, bool atomic)
{
int arglen = desc->arginfo & 0xf;
int i;
- u32 fn_id = SCM_SMC_FNID(svc_id, cmd_id);
u64 x5 = desc->args[SCM_SMC_FIRST_EXT_IDX];
dma_addr_t args_phys = 0;
void *args_virt = NULL;
@@ -158,7 +158,7 @@ static int __scm_smc_call(struct device *dev, u32 svc_id, u32 cmd_id,
x5 = args_phys;
}

- __scm_smc_do(desc, res, fn_id, x5, atomic);
+ __scm_smc_do(desc, res, x5, atomic);

if (args_virt) {
dma_unmap_single(dev, args_phys, alloc_len, DMA_TO_DEVICE);
@@ -181,12 +181,11 @@ static int __scm_smc_call(struct device *dev, u32 svc_id, u32 cmd_id,
* Sends a command to the SCM and waits for the command to finish processing.
* This should *only* be called in pre-emptible context.
*/
-static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id,
- const struct qcom_scm_desc *desc,
+static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
struct arm_smccc_res *res)
{
might_sleep();
- return __scm_smc_call(dev, svc_id, cmd_id, desc, res, false);
+ return __scm_smc_call(dev, desc, res, false);
}

/**
@@ -200,11 +199,11 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id,
* Sends a command to the SCM and waits for the command to finish processing.
* This can be called in atomic context.
*/
-static int qcom_scm_call_atomic(struct device *dev, u32 svc_id, u32 cmd_id,
+static int qcom_scm_call_atomic(struct device *dev,
const struct qcom_scm_desc *desc,
struct arm_smccc_res *res)
{
- return __scm_smc_call(dev, svc_id, cmd_id, desc, res, true);
+ return __scm_smc_call(dev, desc, res, true);
}

/**
@@ -250,15 +249,18 @@ void __qcom_scm_cpu_power_down(u32 flags)
int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
{
int ret;
- struct qcom_scm_desc desc = {0};
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_INFO,
+ .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
struct arm_smccc_res res;

desc.arginfo = QCOM_SCM_ARGS(1);
desc.args[0] = SCM_SMC_FNID(svc_id, cmd_id) |
(ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT);

- ret = qcom_scm_call(dev, QCOM_SCM_SVC_INFO, QCOM_SCM_INFO_IS_CALL_AVAIL,
- &desc, &res);
+ ret = qcom_scm_call(dev, &desc, &res);

return ret ? : res.a1;
}
@@ -267,7 +269,11 @@ int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
u32 req_cnt, u32 *resp)
{
int ret;
- struct qcom_scm_desc desc = {0};
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_HDCP,
+ .cmd = QCOM_SCM_HDCP_INVOKE,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
struct arm_smccc_res res;

if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
@@ -285,8 +291,7 @@ int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
desc.args[9] = req[4].val;
desc.arginfo = QCOM_SCM_ARGS(10);

- ret = qcom_scm_call(dev, QCOM_SCM_SVC_HDCP, QCOM_SCM_HDCP_INVOKE, &desc,
- &res);
+ ret = qcom_scm_call(dev, &desc, &res);
*resp = res.a1;

return ret;
@@ -326,15 +331,17 @@ void __qcom_scm_init(void)
bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral)
{
int ret;
- struct qcom_scm_desc desc = {0};
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_PIL,
+ .cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
struct arm_smccc_res res;

desc.args[0] = peripheral;
desc.arginfo = QCOM_SCM_ARGS(1);

- ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
- QCOM_SCM_PIL_PAS_IS_SUPPORTED,
- &desc, &res);
+ ret = qcom_scm_call(dev, &desc, &res);

return ret ? false : !!res.a1;
}
@@ -343,15 +350,18 @@ int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
dma_addr_t metadata_phys)
{
int ret;
- struct qcom_scm_desc desc = {0};
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_PIL,
+ .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
struct arm_smccc_res res;

desc.args[0] = peripheral;
desc.args[1] = metadata_phys;
desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW);

- ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_INIT_IMAGE,
- &desc, &res);
+ ret = qcom_scm_call(dev, &desc, &res);

return ret ? : res.a1;
}
@@ -360,7 +370,11 @@ int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
phys_addr_t addr, phys_addr_t size)
{
int ret;
- struct qcom_scm_desc desc = {0};
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_PIL,
+ .cmd = QCOM_SCM_PIL_PAS_MEM_SETUP,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
struct arm_smccc_res res;

desc.args[0] = peripheral;
@@ -368,8 +382,7 @@ int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
desc.args[2] = size;
desc.arginfo = QCOM_SCM_ARGS(3);

- ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_MEM_SETUP,
- &desc, &res);
+ ret = qcom_scm_call(dev, &desc, &res);

return ret ? : res.a1;
}
@@ -377,15 +390,17 @@ int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral)
{
int ret;
- struct qcom_scm_desc desc = {0};
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_PIL,
+ .cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
struct arm_smccc_res res;

desc.args[0] = peripheral;
desc.arginfo = QCOM_SCM_ARGS(1);

- ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL,
- QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
- &desc, &res);
+ ret = qcom_scm_call(dev, &desc, &res);

return ret ? : res.a1;
}
@@ -393,21 +408,28 @@ int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral)
int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral)
{
int ret;
- struct qcom_scm_desc desc = {0};
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_PIL,
+ .cmd = QCOM_SCM_PIL_PAS_SHUTDOWN,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
struct arm_smccc_res res;

desc.args[0] = peripheral;
desc.arginfo = QCOM_SCM_ARGS(1);

- ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_SHUTDOWN,
- &desc, &res);
+ ret = qcom_scm_call(dev, &desc, &res);

return ret ? : res.a1;
}

int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
{
- struct qcom_scm_desc desc = {0};
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_PIL,
+ .cmd = QCOM_SCM_PIL_PAS_MSS_RESET,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
struct arm_smccc_res res;
int ret;

@@ -415,15 +437,18 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
desc.args[1] = 0;
desc.arginfo = QCOM_SCM_ARGS(2);

- ret = qcom_scm_call(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_MSS_RESET, &desc,
- &res);
+ ret = qcom_scm_call(dev, &desc, &res);

return ret ? : res.a1;
}

int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
{
- struct qcom_scm_desc desc = {0};
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_BOOT,
+ .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
struct arm_smccc_res res;
int ret;

@@ -431,8 +456,7 @@ int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
desc.args[1] = id;
desc.arginfo = QCOM_SCM_ARGS(2);

- ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_REMOTE_STATE,
- &desc, &res);
+ ret = qcom_scm_call(dev, &desc, &res);

return ret ? : res.a1;
}
@@ -442,7 +466,11 @@ int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
phys_addr_t dest, size_t dest_sz)
{
int ret;
- struct qcom_scm_desc desc = {0};
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_MP,
+ .cmd = QCOM_SCM_MP_ASSIGN,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
struct arm_smccc_res res;

desc.args[0] = mem_region;
@@ -457,16 +485,18 @@ int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_RO,
QCOM_SCM_VAL, QCOM_SCM_VAL);

- ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP,
- QCOM_SCM_MP_ASSIGN,
- &desc, &res);
+ ret = qcom_scm_call(dev, &desc, &res);

return ret ? : res.a1;
}

int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare)
{
- struct qcom_scm_desc desc = {0};
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_MP,
+ .cmd = QCOM_SCM_MP_RESTORE_SEC_CFG,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
struct arm_smccc_res res;
int ret;

@@ -474,8 +504,7 @@ int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare)
desc.args[1] = spare;
desc.arginfo = QCOM_SCM_ARGS(2);

- ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP, QCOM_SCM_MP_RESTORE_SEC_CFG,
- &desc, &res);
+ ret = qcom_scm_call(dev, &desc, &res);

return ret ? : res.a1;
}
@@ -483,15 +512,18 @@ int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, u32 spare)
int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
size_t *size)
{
- struct qcom_scm_desc desc = {0};
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_MP,
+ .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
struct arm_smccc_res res;
int ret;

desc.args[0] = spare;
desc.arginfo = QCOM_SCM_ARGS(1);

- ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP,
- QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE, &desc, &res);
+ ret = qcom_scm_call(dev, &desc, &res);

if (size)
*size = res.a1;
@@ -502,7 +534,11 @@ int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,
u32 spare)
{
- struct qcom_scm_desc desc = {0};
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_MP,
+ .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
struct arm_smccc_res res;
int ret;

@@ -512,8 +548,7 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,
desc.arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL,
QCOM_SCM_VAL);

- ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP,
- QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT, &desc, &res);
+ ret = qcom_scm_call(dev, &desc, &res);

/* the pg table has been initialized already, ignore the error */
if (ret == -EPERM)
@@ -524,29 +559,35 @@ int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,

int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
{
- struct qcom_scm_desc desc = {0};
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_BOOT,
+ .cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
struct arm_smccc_res res;

desc.args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE;
desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
desc.arginfo = QCOM_SCM_ARGS(2);

- return qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_DLOAD_MODE,
- &desc, &res);
+ return qcom_scm_call(dev, &desc, &res);
}

int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
unsigned int *val)
{
- struct qcom_scm_desc desc = {0};
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_IO,
+ .cmd = QCOM_SCM_IO_READ,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
struct arm_smccc_res res;
int ret;

desc.args[0] = addr;
desc.arginfo = QCOM_SCM_ARGS(1);

- ret = qcom_scm_call(dev, QCOM_SCM_SVC_IO, QCOM_SCM_IO_READ,
- &desc, &res);
+ ret = qcom_scm_call(dev, &desc, &res);
if (ret >= 0)
*val = res.a1;

@@ -555,26 +596,32 @@ int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,

int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)
{
- struct qcom_scm_desc desc = {0};
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_IO,
+ .cmd = QCOM_SCM_IO_WRITE,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
struct arm_smccc_res res;

desc.args[0] = addr;
desc.args[1] = val;
desc.arginfo = QCOM_SCM_ARGS(2);

- return qcom_scm_call(dev, QCOM_SCM_SVC_IO, QCOM_SCM_IO_WRITE,
- &desc, &res);
+ return qcom_scm_call(dev, &desc, &res);
}

int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool en)
{
- struct qcom_scm_desc desc = {0};
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_SMMU_PROGRAM,
+ .cmd = QCOM_SCM_SMMU_CONFIG_ERRATA1,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
struct arm_smccc_res res;

desc.args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL;
desc.args[1] = en;
desc.arginfo = QCOM_SCM_ARGS(2);

- return qcom_scm_call_atomic(dev, QCOM_SCM_SVC_SMMU_PROGRAM,
- QCOM_SCM_SMMU_CONFIG_ERRATA1, &desc, &res);
+ return qcom_scm_call_atomic(dev, &desc, &res);
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

2020-01-07 21:20:50

by Elliot Berman

[permalink] [raw]
Subject: [PATCH v5 04/17] firmware: qcom_scm-64: Make SMC macros less magical

Improve understandability of SMC macros by reversing the logic as they
are all functions of how many arguments can be shoved in registers and
how many SCM arguments are supported.

There aren't 4 register arguments because are 7 arguments that go into a
buffer - there are up to 7 arguments that are overflowed into a buffer
because only 4 registers are allocated for arguments.

Change-Id: Iac0378fc4c5e20943a64b98223d53caa4955dd53
Reviewed-by: Stephen Boyd <[email protected]>
Tested-by: Brian Masney <[email protected]> # arm32
Tested-by: Stephan Gerhold <[email protected]>
Signed-off-by: Elliot Berman <[email protected]>
---
drivers/firmware/qcom_scm-64.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c
index 976c2b9..3101f36 100644
--- a/drivers/firmware/qcom_scm-64.c
+++ b/drivers/firmware/qcom_scm-64.c
@@ -58,9 +58,9 @@ static DEFINE_MUTEX(qcom_scm_lock);
#define QCOM_SCM_EBUSY_WAIT_MS 30
#define QCOM_SCM_EBUSY_MAX_RETRY 20

-#define SCM_SMC_N_EXT_ARGS 7
-#define SCM_SMC_FIRST_EXT_IDX 3
-#define SCM_SMC_N_REG_ARGS (MAX_QCOM_SCM_ARGS - SCM_SMC_N_EXT_ARGS + 1)
+#define SCM_SMC_N_REG_ARGS 4
+#define SCM_SMC_FIRST_EXT_IDX (SCM_SMC_N_REG_ARGS - 1)
+#define SCM_SMC_N_EXT_ARGS (MAX_QCOM_SCM_ARGS - SCM_SMC_N_REG_ARGS + 1)

static void __scm_smc_do_quirk(const struct qcom_scm_desc *desc,
struct arm_smccc_res *res, u32 fn_id,
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

2020-01-07 21:20:58

by Elliot Berman

[permalink] [raw]
Subject: [PATCH v5 17/17] firmware: qcom_scm: Dynamically support SMCCC and legacy conventions

Dynamically support SMCCCC and legacy conventions by detecting which
convention to use at runtime. qcom_scm_call_atomic and qcom_scm_call can
then be moved in qcom_scm.c and use underlying convention backend as
appropriate. Thus, rename qcom_scm-64,-32 to reflect that they are
backends for -smc and -legacy, respectively.

Also add support for making SCM calls earlier than when SCM driver
probes to support use cases such as qcom_scm_set_cold_boot_addr. Support
is added by lazily initializing the convention and guarding the query
with a spin lock. The limitation of these early SCM calls is that they
cannot use DMA, as in the case of >4 arguments for SMC convention and
any non-atomic call for legacy convention.

Change-Id: Ib46a29aeca4938b280821e526f2fdb6d1b461513
Tested-by: Brian Masney <[email protected]> # arm32
Tested-by: Stephan Gerhold <[email protected]>
Signed-off-by: Elliot Berman <[email protected]>
---
drivers/firmware/Kconfig | 8 --
drivers/firmware/Makefile | 4 +-
.../firmware/{qcom_scm-32.c => qcom_scm-legacy.c} | 31 +----
drivers/firmware/{qcom_scm-64.c => qcom_scm-smc.c} | 95 +-------------
drivers/firmware/qcom_scm.c | 146 ++++++++++++++++++++-
drivers/firmware/qcom_scm.h | 27 +++-
6 files changed, 176 insertions(+), 135 deletions(-)
rename drivers/firmware/{qcom_scm-32.c => qcom_scm-legacy.c} (90%)
rename drivers/firmware/{qcom_scm-64.c => qcom_scm-smc.c} (57%)

diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
index e40a77b..ea869ad 100644
--- a/drivers/firmware/Kconfig
+++ b/drivers/firmware/Kconfig
@@ -239,14 +239,6 @@ config QCOM_SCM
depends on ARM || ARM64
select RESET_CONTROLLER

-config QCOM_SCM_32
- def_bool y
- depends on QCOM_SCM && ARM
-
-config QCOM_SCM_64
- def_bool y
- depends on QCOM_SCM && ARM64
-
config QCOM_SCM_DOWNLOAD_MODE_DEFAULT
bool "Qualcomm download mode enabled by default"
depends on QCOM_SCM
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 747fb73..e9fb838 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -17,9 +17,7 @@ obj-$(CONFIG_ISCSI_IBFT) += iscsi_ibft.o
obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o
obj-$(CONFIG_RASPBERRYPI_FIRMWARE) += raspberrypi.o
obj-$(CONFIG_FW_CFG_SYSFS) += qemu_fw_cfg.o
-obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
-obj-$(CONFIG_QCOM_SCM_64) += qcom_scm-64.o
-obj-$(CONFIG_QCOM_SCM_32) += qcom_scm-32.o
+obj-$(CONFIG_QCOM_SCM) += qcom_scm.o qcom_scm-smc.o qcom_scm-legacy.o
obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o
obj-$(CONFIG_TRUSTED_FOUNDATIONS) += trusted_foundations.o
obj-$(CONFIG_TURRIS_MOX_RWTM) += turris-mox-rwtm.o
diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-legacy.c
similarity index 90%
rename from drivers/firmware/qcom_scm-32.c
rename to drivers/firmware/qcom_scm-legacy.c
index 08220e7..8532e7c 100644
--- a/drivers/firmware/qcom_scm-32.c
+++ b/drivers/firmware/qcom_scm-legacy.c
@@ -26,7 +26,6 @@ struct arm_smccc_args {
unsigned long args[8];
};

-#define SCM_LEGACY_FNID(s, c) (((s) << 10) | ((c) & 0x3ff))

/**
* struct scm_legacy_command - one SCM command buffer
@@ -129,8 +128,8 @@ static void __scm_legacy_do(const struct arm_smccc_args *smc,
* and response buffers is taken care of by qcom_scm_call; however, callers are
* responsible for any other cached buffers passed over to the secure world.
*/
-int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
- struct qcom_scm_res *res)
+int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,
+ struct qcom_scm_res *res)
{
u8 arglen = desc->arginfo & 0xf;
int ret = 0, context_id;
@@ -218,9 +217,9 @@ int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
* This shall only be used with commands that are guaranteed to be
* uninterruptable, atomic and SMP safe.
*/
-int qcom_scm_call_atomic(struct device *unused,
- const struct qcom_scm_desc *desc,
- struct qcom_scm_res *res)
+int scm_legacy_call_atomic(struct device *unused,
+ const struct qcom_scm_desc *desc,
+ struct qcom_scm_res *res)
{
int context_id;
struct arm_smccc_res smc_res;
@@ -241,23 +240,3 @@ int qcom_scm_call_atomic(struct device *unused,

return smc_res.a0;
}
-
-int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
-{
- int ret;
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_INFO,
- .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
- .args[0] = SCM_LEGACY_FNID(svc_id, cmd_id),
- .arginfo = QCOM_SCM_ARGS(1),
- };
- struct qcom_scm_res res;
-
- ret = qcom_scm_call(dev, &desc, &res);
-
- return ret ? : res.result[0];
-}
-
-void __qcom_scm_init(void)
-{
-}
diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-smc.c
similarity index 57%
rename from drivers/firmware/qcom_scm-64.c
rename to drivers/firmware/qcom_scm-smc.c
index 4defc7c..497c13b 100644
--- a/drivers/firmware/qcom_scm-64.c
+++ b/drivers/firmware/qcom_scm-smc.c
@@ -14,8 +14,6 @@

#include "qcom_scm.h"

-#define SCM_SMC_FNID(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF))
-
/**
* struct arm_smccc_args
* @args: The array of values used in registers in smc instruction
@@ -24,7 +22,6 @@ struct arm_smccc_args {
unsigned long args[8];
};

-static u64 qcom_smccc_convention = -1;
static DEFINE_MUTEX(qcom_scm_lock);

#define QCOM_SCM_EBUSY_WAIT_MS 30
@@ -80,8 +77,8 @@ static void __scm_smc_do(const struct arm_smccc_args *smc,
} while (res->a0 == QCOM_SCM_V2_EBUSY);
}

-static int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
- struct qcom_scm_res *res, bool atomic)
+int scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
+ struct qcom_scm_res *res, bool atomic)
{
int arglen = desc->arginfo & 0xf;
int i;
@@ -90,6 +87,9 @@ static int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
size_t alloc_len;
gfp_t flag = atomic ? GFP_ATOMIC : GFP_KERNEL;
u32 smccc_call_type = atomic ? ARM_SMCCC_FAST_CALL : ARM_SMCCC_STD_CALL;
+ u32 qcom_smccc_convention =
+ (qcom_scm_convention == SMC_CONVENTION_ARM_32) ?
+ ARM_SMCCC_SMC_32 : ARM_SMCCC_SMC_64;
struct arm_smccc_res smc_res;
struct arm_smccc_args smc = {0};

@@ -149,88 +149,3 @@ static int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,

return (long)smc_res.a0 ? qcom_scm_remap_error(smc_res.a0) : 0;
}
-
-/**
- * qcom_scm_call() - Invoke a syscall in the secure world
- * @dev: device
- * @svc_id: service identifier
- * @cmd_id: command identifier
- * @desc: Descriptor structure containing arguments and return values
- *
- * Sends a command to the SCM and waits for the command to finish processing.
- * This should *only* be called in pre-emptible context.
- */
-int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
- struct qcom_scm_res *res)
-{
- might_sleep();
- return __scm_smc_call(dev, desc, res, false);
-}
-
-/**
- * qcom_scm_call_atomic() - atomic variation of qcom_scm_call()
- * @dev: device
- * @svc_id: service identifier
- * @cmd_id: command identifier
- * @desc: Descriptor structure containing arguments and return values
- * @res: Structure containing results from SMC/HVC call
- *
- * Sends a command to the SCM and waits for the command to finish processing.
- * This can be called in atomic context.
- */
-int qcom_scm_call_atomic(struct device *dev, const struct qcom_scm_desc *desc,
- struct qcom_scm_res *res)
-{
- return __scm_smc_call(dev, desc, res, true);
-}
-
-int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
-{
- int ret;
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_INFO,
- .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
- .owner = ARM_SMCCC_OWNER_SIP,
- };
- struct qcom_scm_res res;
-
- desc.arginfo = QCOM_SCM_ARGS(1);
- desc.args[0] = SCM_SMC_FNID(svc_id, cmd_id) |
- (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT);
-
- ret = qcom_scm_call(dev, &desc, &res);
-
- return ret ? : res.result[0];
-}
-
-void __qcom_scm_init(void)
-{
- struct qcom_scm_desc desc = {
- .svc = QCOM_SCM_SVC_INFO,
- .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
- .args[0] = SCM_SMC_FNID(QCOM_SCM_SVC_INFO,
- QCOM_SCM_INFO_IS_CALL_AVAIL) |
- (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT),
- .arginfo = QCOM_SCM_ARGS(1),
- .owner = ARM_SMCCC_OWNER_SIP,
- };
- struct qcom_scm_res res;
- int ret;
-
- qcom_smccc_convention = ARM_SMCCC_SMC_64;
- // Device isn't required as there is only one argument - no device
- // needed to dma_map_single to secure world
- ret = qcom_scm_call_atomic(NULL, &desc, &res);
- if (!ret && res.result[0] == 1)
- goto out;
-
- qcom_smccc_convention = ARM_SMCCC_SMC_32;
- ret = qcom_scm_call_atomic(NULL, &desc, &res);
- if (!ret && res.result[0] == 1)
- goto out;
-
- qcom_smccc_convention = -1;
- BUG();
-out:
- pr_info("QCOM SCM SMC Convention: %lld\n", qcom_smccc_convention);
-}
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 895f148..059bb0f 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -72,6 +72,13 @@ static struct qcom_scm_wb_entry qcom_scm_wb[] = {
{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 },
};

+static const char *qcom_scm_convention_names[] = {
+ [SMC_CONVENTION_UNKNOWN] = "unknown",
+ [SMC_CONVENTION_ARM_32] = "smc arm 32",
+ [SMC_CONVENTION_ARM_64] = "smc arm 64",
+ [SMC_CONVENTION_LEGACY] = "smc legacy",
+};
+
static struct qcom_scm *__scm;

static int qcom_scm_clk_enable(void)
@@ -107,6 +114,143 @@ static void qcom_scm_clk_disable(void)
clk_disable_unprepare(__scm->bus_clk);
}

+static int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
+ u32 cmd_id);
+
+enum qcom_scm_convention qcom_scm_convention;
+static bool has_queried __read_mostly;
+static DEFINE_SPINLOCK(query_lock);
+
+static void __query_convention(void)
+{
+ unsigned long flags;
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_INFO,
+ .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
+ .args[0] = SCM_SMC_FNID(QCOM_SCM_SVC_INFO,
+ QCOM_SCM_INFO_IS_CALL_AVAIL) |
+ (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT),
+ .arginfo = QCOM_SCM_ARGS(1),
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+ struct qcom_scm_res res;
+ int ret;
+
+ spin_lock_irqsave(&query_lock, flags);
+ if (has_queried)
+ goto out;
+
+ qcom_scm_convention = SMC_CONVENTION_ARM_64;
+ // Device isn't required as there is only one argument - no device
+ // needed to dma_map_single to secure world
+ ret = scm_smc_call(NULL, &desc, &res, true);
+ if (!ret && res.result[0] == 1)
+ goto out;
+
+ qcom_scm_convention = SMC_CONVENTION_ARM_32;
+ ret = scm_smc_call(NULL, &desc, &res, true);
+ if (!ret && res.result[0] == 1)
+ goto out;
+
+ qcom_scm_convention = SMC_CONVENTION_LEGACY;
+out:
+ has_queried = true;
+ spin_unlock_irqrestore(&query_lock, flags);
+ pr_info("qcom_scm: convention: %s\n",
+ qcom_scm_convention_names[qcom_scm_convention]);
+}
+
+static inline enum qcom_scm_convention __get_convention(void)
+{
+ if (unlikely(!has_queried))
+ __query_convention();
+ return qcom_scm_convention;
+}
+
+/**
+ * qcom_scm_call() - Invoke a syscall in the secure world
+ * @dev: device
+ * @svc_id: service identifier
+ * @cmd_id: command identifier
+ * @desc: Descriptor structure containing arguments and return values
+ *
+ * Sends a command to the SCM and waits for the command to finish processing.
+ * This should *only* be called in pre-emptible context.
+ */
+static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
+ struct qcom_scm_res *res)
+{
+ might_sleep();
+ switch (__get_convention()) {
+ case SMC_CONVENTION_ARM_32:
+ case SMC_CONVENTION_ARM_64:
+ return scm_smc_call(dev, desc, res, false);
+ case SMC_CONVENTION_LEGACY:
+ return scm_legacy_call(dev, desc, res);
+ default:
+ pr_err("Unknown current SCM calling convention.\n");
+ return -EINVAL;
+ }
+}
+
+/**
+ * qcom_scm_call_atomic() - atomic variation of qcom_scm_call()
+ * @dev: device
+ * @svc_id: service identifier
+ * @cmd_id: command identifier
+ * @desc: Descriptor structure containing arguments and return values
+ * @res: Structure containing results from SMC/HVC call
+ *
+ * Sends a command to the SCM and waits for the command to finish processing.
+ * This can be called in atomic context.
+ */
+static int qcom_scm_call_atomic(struct device *dev,
+ const struct qcom_scm_desc *desc,
+ struct qcom_scm_res *res)
+{
+ switch (__get_convention()) {
+ case SMC_CONVENTION_ARM_32:
+ case SMC_CONVENTION_ARM_64:
+ return scm_smc_call(dev, desc, res, true);
+ case SMC_CONVENTION_LEGACY:
+ return scm_legacy_call_atomic(dev, desc, res);
+ default:
+ pr_err("Unknown current SCM calling convention.\n");
+ return -EINVAL;
+ }
+}
+
+static int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
+ u32 cmd_id)
+{
+ int ret;
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_INFO,
+ .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
+ .owner = ARM_SMCCC_OWNER_SIP,
+ };
+ struct qcom_scm_res res;
+
+ desc.arginfo = QCOM_SCM_ARGS(1);
+ switch (__get_convention()) {
+ case SMC_CONVENTION_ARM_32:
+ case SMC_CONVENTION_ARM_64:
+ desc.args[0] = SCM_SMC_FNID(svc_id, cmd_id) |
+ (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT);
+ break;
+ case SMC_CONVENTION_LEGACY:
+ desc.args[0] = SCM_LEGACY_FNID(svc_id, cmd_id);
+ break;
+ default:
+ pr_err("Unknown SMC convention being used\n");
+ return -EINVAL;
+ }
+
+ ret = qcom_scm_call(dev, &desc, &res);
+
+ return ret ? : res.result[0];
+}
+
/**
* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
* @entry: Entry point function for the cpus
@@ -971,7 +1115,7 @@ static int qcom_scm_probe(struct platform_device *pdev)
__scm = scm;
__scm->dev = &pdev->dev;

- __qcom_scm_init();
+ __query_convention();

/*
* If requested enable "download mode", from this point on warmboot
diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h
index 9b7b357..d9ed670 100644
--- a/drivers/firmware/qcom_scm.h
+++ b/drivers/firmware/qcom_scm.h
@@ -3,6 +3,16 @@
*/
#ifndef __QCOM_SCM_INT_H
#define __QCOM_SCM_INT_H
+
+enum qcom_scm_convention {
+ SMC_CONVENTION_UNKNOWN,
+ SMC_CONVENTION_LEGACY,
+ SMC_CONVENTION_ARM_32,
+ SMC_CONVENTION_ARM_64,
+};
+
+extern enum qcom_scm_convention qcom_scm_convention;
+
#define MAX_QCOM_SCM_ARGS 10
#define MAX_QCOM_SCM_RETS 3

@@ -50,11 +60,16 @@ struct qcom_scm_res {
u64 result[MAX_QCOM_SCM_RETS];
};

-extern int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
- struct qcom_scm_res *res);
-extern int qcom_scm_call_atomic(struct device *dev,
- const struct qcom_scm_desc *desc,
- struct qcom_scm_res *res);
+#define SCM_SMC_FNID(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF))
+extern int scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
+ struct qcom_scm_res *res, bool atomic);
+
+#define SCM_LEGACY_FNID(s, c) (((s) << 10) | ((c) & 0x3ff))
+extern int scm_legacy_call_atomic(struct device *dev,
+ const struct qcom_scm_desc *desc,
+ struct qcom_scm_res *res);
+extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,
+ struct qcom_scm_res *res);

#define QCOM_SCM_SVC_BOOT 0x01
#define QCOM_SCM_BOOT_SET_ADDR 0x01
@@ -77,8 +92,6 @@ extern int qcom_scm_call_atomic(struct device *dev,

#define QCOM_SCM_SVC_INFO 0x06
#define QCOM_SCM_INFO_IS_CALL_AVAIL 0x01
-extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
- u32 cmd_id);

#define QCOM_SCM_SVC_MP 0x0c
#define QCOM_SCM_MP_RESTORE_SEC_CFG 0x02
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

2020-01-07 21:21:09

by Elliot Berman

[permalink] [raw]
Subject: [PATCH v5 13/17] firmware: qcom_scm-32: Create common legacy atomic call

Per [1], legacy calling convention supports up to 5 arguments and 3
return values. Create one function to support this combination, and
remove the original "atomic1" and "atomic2" variants for 1 and 2
arguments. This more closely aligns scm_legacy implementation with
scm_smc implementation.

[1]: https://source.codeaurora.org/quic/la/kernel/msm-4.9/tree/drivers/soc/qcom/scm.c?h=kernel.lnx.4.9.r28-rel#n1024

Change-Id: I516d920e00d6da99a1f8290c2ed8654c75f268f9
Tested-by: Brian Masney <[email protected]> # arm32
Tested-by: Stephan Gerhold <[email protected]>
Signed-off-by: Elliot Berman <[email protected]>
---
drivers/firmware/qcom_scm-32.c | 106 ++++++++++++++++++++++++++---------------
1 file changed, 68 insertions(+), 38 deletions(-)

diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c
index acd956f..9729a8a 100644
--- a/drivers/firmware/qcom_scm-32.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -266,6 +266,8 @@ static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
return ret;
}

+#define SCM_LEGACY_ATOMIC_N_REG_ARGS 5
+#define SCM_LEGACY_ATOMIC_FIRST_REG_IDX 2
#define SCM_LEGACY_CLASS_REGISTER (0x2 << 8)
#define SCM_LEGACY_MASK_IRQS BIT(5)
#define SCM_LEGACY_ATOMIC_ID(svc, cmd, n) \
@@ -275,44 +277,35 @@ static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
(n & 0xf))

/**
- * qcom_scm_call_atomic1() - Send an atomic SCM command with one argument
- * @svc_id: service identifier
- * @cmd_id: command identifier
- * @arg1: first argument
+ * qcom_scm_call_atomic() - Send an atomic SCM command with up to 5 arguments
+ * and 3 return values
+ * @desc: SCM call descriptor containing arguments
+ * @res: SCM call return values
*
* This shall only be used with commands that are guaranteed to be
* uninterruptable, atomic and SMP safe.
*/
-static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1)
+static int qcom_scm_call_atomic(const struct qcom_scm_desc *desc,
+ struct qcom_scm_res *res)
{
int context_id;
- struct arm_smccc_res res;
+ struct arm_smccc_res smc_res;
+ size_t arglen = desc->arginfo & 0xf;

- arm_smccc_smc(SCM_LEGACY_ATOMIC_ID(svc, cmd, 1),
- (unsigned long)&context_id, arg1, 0, 0, 0, 0, 0, &res);
+ BUG_ON(arglen > SCM_LEGACY_ATOMIC_N_REG_ARGS);

- return res.a0;
-}
+ arm_smccc_smc(SCM_LEGACY_ATOMIC_ID(desc->svc, desc->cmd, arglen),
+ (unsigned long)&context_id,
+ desc->args[0], desc->args[1], desc->args[2],
+ desc->args[3], desc->args[4], 0, &smc_res);

-/**
- * qcom_scm_call_atomic2() - Send an atomic SCM command with two arguments
- * @svc_id: service identifier
- * @cmd_id: command identifier
- * @arg1: first argument
- * @arg2: second argument
- *
- * This shall only be used with commands that are guaranteed to be
- * uninterruptable, atomic and SMP safe.
- */
-static s32 qcom_scm_call_atomic2(u32 svc, u32 cmd, u32 arg1, u32 arg2)
-{
- int context_id;
- struct arm_smccc_res res;
-
- arm_smccc_smc(SCM_LEGACY_ATOMIC_ID(svc, cmd, 2),
- (unsigned long)&context_id, arg1, 0, 0, 0, 0, 0, &res);
+ if (res) {
+ res->result[0] = smc_res.a1;
+ res->result[1] = smc_res.a2;
+ res->result[2] = smc_res.a3;
+ }

- return res.a0;
+ return smc_res.a0;
}

/**
@@ -333,6 +326,10 @@ int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
QCOM_SCM_FLAG_COLDBOOT_CPU2,
QCOM_SCM_FLAG_COLDBOOT_CPU3,
};
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_BOOT,
+ .cmd = QCOM_SCM_BOOT_SET_ADDR,
+ };

if (!cpus || (cpus && cpumask_empty(cpus)))
return -EINVAL;
@@ -344,8 +341,11 @@ int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
set_cpu_present(cpu, false);
}

- return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_ADDR,
- flags, virt_to_phys(entry));
+ desc.args[0] = flags;
+ desc.args[1] = virt_to_phys(entry);
+ desc.arginfo = QCOM_SCM_ARGS(2);
+
+ return qcom_scm_call_atomic(&desc, NULL);
}

/**
@@ -404,8 +404,14 @@ int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
*/
void __qcom_scm_cpu_power_down(u32 flags)
{
- qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_TERMINATE_PC,
- flags & QCOM_SCM_FLUSH_FLAG_MASK);
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_BOOT,
+ .cmd = QCOM_SCM_BOOT_TERMINATE_PC,
+ .args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK,
+ .arginfo = QCOM_SCM_ARGS(1),
+ };
+
+ qcom_scm_call_atomic(&desc, NULL);
}

int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
@@ -601,8 +607,16 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)

int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
{
- return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_DLOAD_MODE,
- enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0, 0);
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_BOOT,
+ .cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE,
+ };
+
+ desc.args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE;
+ desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
+ desc.arginfo = QCOM_SCM_ARGS(2);
+
+ return qcom_scm_call_atomic(&desc, NULL);
}

int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
@@ -664,18 +678,34 @@ int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
unsigned int *val)
{
int ret;
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_IO,
+ .cmd = QCOM_SCM_IO_READ,
+ };
+ struct qcom_scm_res res;
+
+ desc.args[0] = addr;
+ desc.arginfo = QCOM_SCM_ARGS(1);

- ret = qcom_scm_call_atomic1(QCOM_SCM_SVC_IO, QCOM_SCM_IO_READ, addr);
+ ret = qcom_scm_call_atomic(&desc, &res);
if (ret >= 0)
- *val = ret;
+ *val = res.result[0];

return ret < 0 ? ret : 0;
}

int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)
{
- return qcom_scm_call_atomic2(QCOM_SCM_SVC_IO, QCOM_SCM_IO_WRITE,
- addr, val);
+ struct qcom_scm_desc desc = {
+ .svc = QCOM_SCM_SVC_IO,
+ .cmd = QCOM_SCM_IO_WRITE,
+ };
+
+ desc.args[0] = addr;
+ desc.args[1] = val;
+ desc.arginfo = QCOM_SCM_ARGS(2);
+
+ return qcom_scm_call_atomic(&desc, NULL);
}

int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool enable)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

2020-01-07 21:21:35

by Elliot Berman

[permalink] [raw]
Subject: [PATCH v5 09/17] firmware: qcom_scm-32: Use SMC arch wrappers

Use SMC arch wrappers instead of inline assembly.

Change-Id: Ia8b8518f842462eb3f7e0d3200497431ca9c2c4e
Tested-by: Brian Masney <[email protected]> # arm32
Tested-by: Stephan Gerhold <[email protected]>
Signed-off-by: Elliot Berman <[email protected]>
---
drivers/firmware/Makefile | 1 -
drivers/firmware/qcom_scm-32.c | 71 ++++++++++--------------------------------
2 files changed, 17 insertions(+), 55 deletions(-)

diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 3fcb919..747fb73 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -20,7 +20,6 @@ obj-$(CONFIG_FW_CFG_SYSFS) += qemu_fw_cfg.o
obj-$(CONFIG_QCOM_SCM) += qcom_scm.o
obj-$(CONFIG_QCOM_SCM_64) += qcom_scm-64.o
obj-$(CONFIG_QCOM_SCM_32) += qcom_scm-32.o
-CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch armv7-a\n.arch_extension sec,-DREQUIRES_SEC=1) -march=armv7-a
obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o
obj-$(CONFIG_TRUSTED_FOUNDATIONS) += trusted_foundations.o
obj-$(CONFIG_TURRIS_MOX_RWTM) += turris-mox-rwtm.o
diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c
index 8b57240..362d042 100644
--- a/drivers/firmware/qcom_scm-32.c
+++ b/drivers/firmware/qcom_scm-32.c
@@ -10,6 +10,7 @@
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/qcom_scm.h>
+#include <linux/arm-smccc.h>
#include <linux/dma-mapping.h>

#include "qcom_scm.h"
@@ -121,25 +122,13 @@ static inline void *scm_legacy_get_response_buffer(
static u32 __scm_legacy_do(u32 cmd_addr)
{
int context_id;
- register u32 r0 asm("r0") = 1;
- register u32 r1 asm("r1") = (u32)&context_id;
- register u32 r2 asm("r2") = cmd_addr;
+ struct arm_smccc_res res;
do {
- asm volatile(
- __asmeq("%0", "r0")
- __asmeq("%1", "r0")
- __asmeq("%2", "r1")
- __asmeq("%3", "r2")
-#ifdef REQUIRES_SEC
- ".arch_extension sec\n"
-#endif
- "smc #0 @ switch to secure world\n"
- : "=r" (r0)
- : "r" (r0), "r" (r1), "r" (r2)
- : "r3", "r12");
- } while (r0 == QCOM_SCM_INTERRUPTED);
-
- return r0;
+ arm_smccc_smc(1, (unsigned long)&context_id, cmd_addr,
+ 0, 0, 0, 0, 0, &res);
+ } while (res.a0 == QCOM_SCM_INTERRUPTED);
+
+ return res.a0;
}

/**
@@ -237,24 +226,12 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id,
static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1)
{
int context_id;
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(SCM_LEGACY_ATOMIC_ID(svc, cmd, 1),
+ (unsigned long)&context_id, arg1, 0, 0, 0, 0, 0, &res);

- register u32 r0 asm("r0") = SCM_LEGACY_ATOMIC_ID(svc, cmd, 1);
- register u32 r1 asm("r1") = (u32)&context_id;
- register u32 r2 asm("r2") = arg1;
-
- asm volatile(
- __asmeq("%0", "r0")
- __asmeq("%1", "r0")
- __asmeq("%2", "r1")
- __asmeq("%3", "r2")
-#ifdef REQUIRES_SEC
- ".arch_extension sec\n"
-#endif
- "smc #0 @ switch to secure world\n"
- : "=r" (r0)
- : "r" (r0), "r" (r1), "r" (r2)
- : "r3", "r12");
- return r0;
+ return res.a0;
}

/**
@@ -270,26 +247,12 @@ static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1)
static s32 qcom_scm_call_atomic2(u32 svc, u32 cmd, u32 arg1, u32 arg2)
{
int context_id;
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(SCM_LEGACY_ATOMIC_ID(svc, cmd, 2),
+ (unsigned long)&context_id, arg1, 0, 0, 0, 0, 0, &res);

- register u32 r0 asm("r0") = SCM_LEGACY_ATOMIC_ID(svc, cmd, 2);
- register u32 r1 asm("r1") = (u32)&context_id;
- register u32 r2 asm("r2") = arg1;
- register u32 r3 asm("r3") = arg2;
-
- asm volatile(
- __asmeq("%0", "r0")
- __asmeq("%1", "r0")
- __asmeq("%2", "r1")
- __asmeq("%3", "r2")
- __asmeq("%4", "r3")
-#ifdef REQUIRES_SEC
- ".arch_extension sec\n"
-#endif
- "smc #0 @ switch to secure world\n"
- : "=r" (r0)
- : "r" (r0), "r" (r1), "r" (r2), "r" (r3)
- : "r12");
- return r0;
+ return res.a0;
}

/**
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

2020-01-08 06:44:31

by Bjorn Andersson

[permalink] [raw]
Subject: Re: [PATCH v5 00/17] Restructure, improve target support for qcom_scm driver

On Tue 07 Jan 13:04 PST 2020, Elliot Berman wrote:

> This series improves support for 32-bit Qualcomm targets on qcom_scm driver and cleans
> up the driver for 64-bit implementations.
>
> Currently, the qcom_scm driver supports only 64-bit Qualcomm targets and very
> old 32-bit Qualcomm targets. Newer 32-bit targets use ARM's SMC Calling
> Convention to communicate with secure world. Older 32-bit targets use a
> "buffer-based" legacy approach for communicating with secure world (as
> implemented in qcom_scm-32.c). All arm64 Qualcomm targets use ARM SMCCC.
> Currently, SMCCC-based communication is enabled only on ARM64 config and
> buffer-based communication only on ARM config. This patch-series combines SMCCC
> and legacy conventions and selects the correct convention by querying the secure
> world [1].
>
> We decided to take the opportunity as well to clean up the driver rather than
> try to patch together qcom_scm-32 and qcom_scm-64.
>

Series applied.

Thank you,
Bjorn

> Patches 1-3 and 15 improve macro names, reorder macros/functions, and prune unused
> macros/functions. No functional changes were introduced.
> Patches 4-8 clears up the SCM abstraction in qcom_scm-64.
> Patches 9-14 clears up the SCM abstraction in qcom_scm-32.
> Patches 16-17 enable dynamically using the different calling conventions.
>
> [1]: https://source.codeaurora.org/quic/la/kernel/msm-4.9/tree/drivers/soc/qcom/scm.c?h=kernel.lnx.4.9.r28-rel#n555
>
> Changes since v4:
> - Restored missing arginfo/args to pas_auth_and_reset
>
> Changes since v3:
> - Updated recepients
>
> Changes since v2:
> - Addressed Stephen's comments throughout v2.
> - Rebased onto latest for-next branch
> - Removed v2 08/18 (firmware: qcom_scm-64: Remove qcom_scm_call_do_smccc)
> - Cleaned up the convention query from v2 to align with [1].
>
> Changes since v1:
> - Renamed functions/variables per Vinod's suggestions
> - Split v1 01/17 into v2 [01,02,03]/18 per Vinod's suggestion
> - Fix suggestions by Bjorn in v1 09/18 (now v2 10/18)
> - Refactor last 3 commits per Bjorn suggestions in v1 17/18 and v1 10/18
>
> Changes since RFC:
> - Fixed missing return values in qcom_scm_call_smccc
> - Fixed order of arguments in qcom_scm_set_warm_boot_addr
> - Adjusted logic of SMC convention to properly support older QCOM secure worlds
> - Boot tested on IFC6410 based on linaro kernel tag:
> debian-qcom-dragonboard410c-18.01 (which does basic verification of legacy
> SCM calls: at least warm_boot_addr, cold_boot_addr, and power_down)
>
> Elliot Berman (17):
> firmware: qcom_scm: Rename macros and structures
> firmware: qcom_scm: Apply consistent naming scheme to command IDs
> firmware: qcom_scm: Remove unused qcom_scm_get_version
> firmware: qcom_scm-64: Make SMC macros less magical
> firmware: qcom_scm-64: Move svc/cmd/owner into qcom_scm_desc
> firmware: qcom_scm-64: Add SCM results struct
> firmware: qcom_scm-64: Move SMC register filling to
> qcom_scm_call_smccc
> firmware: qcom_scm-64: Improve SMC convention detection
> firmware: qcom_scm-32: Use SMC arch wrappers
> firmware: qcom_scm-32: Add funcnum IDs
> firmware: qcom_scm-32: Use qcom_scm_desc in non-atomic calls
> firmware: qcom_scm-32: Move SMCCC register filling to qcom_scm_call
> firmware: qcom_scm-32: Create common legacy atomic call
> firmware: qcom_scm-32: Add device argument to atomic calls
> firmware: qcom_scm: Order functions, definitions by service/command
> firmware: qcom_scm: Remove thin wrappers
> firmware: qcom_scm: Dynamically support SMCCC and legacy conventions
>
> drivers/firmware/Kconfig | 8 -
> drivers/firmware/Makefile | 5 +-
> drivers/firmware/qcom_scm-32.c | 671 -----------------------------
> drivers/firmware/qcom_scm-64.c | 579 -------------------------
> drivers/firmware/qcom_scm-legacy.c | 242 +++++++++++
> drivers/firmware/qcom_scm-smc.c | 151 +++++++
> drivers/firmware/qcom_scm.c | 854 +++++++++++++++++++++++++++++--------
> drivers/firmware/qcom_scm.h | 178 ++++----
> include/linux/qcom_scm.h | 125 +++---
> 9 files changed, 1232 insertions(+), 1581 deletions(-)
> delete mode 100644 drivers/firmware/qcom_scm-32.c
> delete mode 100644 drivers/firmware/qcom_scm-64.c
> create mode 100644 drivers/firmware/qcom_scm-legacy.c
> create mode 100644 drivers/firmware/qcom_scm-smc.c
>
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project

2020-01-08 06:55:40

by Stephen Boyd

[permalink] [raw]
Subject: Re: [PATCH v5 00/17] Restructure, improve target support for qcom_scm driver

Quoting Bjorn Andersson (2020-01-07 22:42:53)
> On Tue 07 Jan 13:04 PST 2020, Elliot Berman wrote:
>
> > This series improves support for 32-bit Qualcomm targets on qcom_scm driver and cleans
> > up the driver for 64-bit implementations.
> >
> > Currently, the qcom_scm driver supports only 64-bit Qualcomm targets and very
> > old 32-bit Qualcomm targets. Newer 32-bit targets use ARM's SMC Calling
> > Convention to communicate with secure world. Older 32-bit targets use a
> > "buffer-based" legacy approach for communicating with secure world (as
> > implemented in qcom_scm-32.c). All arm64 Qualcomm targets use ARM SMCCC.
> > Currently, SMCCC-based communication is enabled only on ARM64 config and
> > buffer-based communication only on ARM config. This patch-series combines SMCCC
> > and legacy conventions and selects the correct convention by querying the secure
> > world [1].
> >
> > We decided to take the opportunity as well to clean up the driver rather than
> > try to patch together qcom_scm-32 and qcom_scm-64.
> >
>
> Series applied.

Without the change-ids presumably? I was going to review the patch
series tomorrow but I guess no more need! ;-)

2020-01-08 07:03:55

by Stephen Boyd

[permalink] [raw]
Subject: Re: [PATCH v5 17/17] firmware: qcom_scm: Dynamically support SMCCC and legacy conventions

(Nitpick trivia late at night)

Quoting Elliot Berman (2020-01-07 13:04:26)
> diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
> index 895f148..059bb0f 100644
> --- a/drivers/firmware/qcom_scm.c
> +++ b/drivers/firmware/qcom_scm.c
> @@ -72,6 +72,13 @@ static struct qcom_scm_wb_entry qcom_scm_wb[] = {
> { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 },
> };
>
> +static const char *qcom_scm_convention_names[] = {

Can this be const char * const ?

> + [SMC_CONVENTION_UNKNOWN] = "unknown",
> + [SMC_CONVENTION_ARM_32] = "smc arm 32",
> + [SMC_CONVENTION_ARM_64] = "smc arm 64",
> + [SMC_CONVENTION_LEGACY] = "smc legacy",
> +};
> +
> static struct qcom_scm *__scm;
>
> static int qcom_scm_clk_enable(void)
> @@ -107,6 +114,143 @@ static void qcom_scm_clk_disable(void)
> clk_disable_unprepare(__scm->bus_clk);
> }
>
> +static int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
> + u32 cmd_id);
> +
> +enum qcom_scm_convention qcom_scm_convention;
> +static bool has_queried __read_mostly;
> +static DEFINE_SPINLOCK(query_lock);
> +
> +static void __query_convention(void)
> +{
> + unsigned long flags;
> + struct qcom_scm_desc desc = {
> + .svc = QCOM_SCM_SVC_INFO,
> + .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
> + .args[0] = SCM_SMC_FNID(QCOM_SCM_SVC_INFO,
> + QCOM_SCM_INFO_IS_CALL_AVAIL) |
> + (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT),
> + .arginfo = QCOM_SCM_ARGS(1),
> + .owner = ARM_SMCCC_OWNER_SIP,
> + };
> + struct qcom_scm_res res;
> + int ret;
> +
> + spin_lock_irqsave(&query_lock, flags);
> + if (has_queried)
> + goto out;
> +
> + qcom_scm_convention = SMC_CONVENTION_ARM_64;
> + // Device isn't required as there is only one argument - no device
> + // needed to dma_map_single to secure world

This isn't kernel style for multiline comments. Please use /* and */.

> + ret = scm_smc_call(NULL, &desc, &res, true);
> + if (!ret && res.result[0] == 1)
> + goto out;
> +

2020-01-08 07:41:47

by Bjorn Andersson

[permalink] [raw]
Subject: Re: [PATCH v5 00/17] Restructure, improve target support for qcom_scm driver

On Tue 07 Jan 22:54 PST 2020, Stephen Boyd wrote:

> Quoting Bjorn Andersson (2020-01-07 22:42:53)
> > On Tue 07 Jan 13:04 PST 2020, Elliot Berman wrote:
> >
> > > This series improves support for 32-bit Qualcomm targets on qcom_scm driver and cleans
> > > up the driver for 64-bit implementations.
> > >
> > > Currently, the qcom_scm driver supports only 64-bit Qualcomm targets and very
> > > old 32-bit Qualcomm targets. Newer 32-bit targets use ARM's SMC Calling
> > > Convention to communicate with secure world. Older 32-bit targets use a
> > > "buffer-based" legacy approach for communicating with secure world (as
> > > implemented in qcom_scm-32.c). All arm64 Qualcomm targets use ARM SMCCC.
> > > Currently, SMCCC-based communication is enabled only on ARM64 config and
> > > buffer-based communication only on ARM config. This patch-series combines SMCCC
> > > and legacy conventions and selects the correct convention by querying the secure
> > > world [1].
> > >
> > > We decided to take the opportunity as well to clean up the driver rather than
> > > try to patch together qcom_scm-32 and qcom_scm-64.
> > >
> >
> > Series applied.
>
> Without the change-ids presumably?

Of course.

> I was going to review the patch series tomorrow but I guess no more
> need! ;-)
>

Thanks, I do appreciate the intention :)

Regards,
Bjorn