The CPU on Qualcomm's IPQ6018 devices are primarily fed by APSS PLL and XO,
these are connected to a clock mux and enable block.
This patch series adds support for these clocks and inturn enables clocks
required for CPU freq.
[V8]
* In patch 1 changed compatible string from const to enum
* Since this change is minimal retained Review tag from Rob
* In patch 3 re added Ack from Rob
[V7]
* Removed dts patch from this series, will send that separately
* Addressed Rob's minor comment on the binding
* Patch 1 depends on a53 pll bindings
https://lkml.org/lkml/2020/5/4/60
[V6]
* Split mailbox driver from this series, mailbox changes will sent as a
separate series
* Addressed review comments from Stephen
[V5]
* Addressed Bjorn comments on apss clk and dt-bindings
* Patch 2 depends on a53 pll dt-bindings
https://www.spinics.net/lists/linux-clk/msg48358.html
[V4]
* Re-written PLL found on IPQ platforms as a separate driver
* Addressed stephen's comments on apss clock controller and pll
* Addressed Rob's review comments on bindings
* moved a53 pll binding from this series as it is not applicable, will send
it separately.
[V3]
* Fixed dt binding check error in patch2
dt-bindings: clock: Add YAML schemas for QCOM A53 PLL
[V2]
* Restructred the patch series as there are two different HW blocks,
the mux and enable belongs to the apcs block and PLL has a separate HW
block.
* Converted qcom mailbox and qcom a53 pll documentation to yaml.
* Addressed review comments from Stephen, Rob and Sibi where it is applicable.
* Changed this cover letter to state the purpose of this patch series
Sivaprakash Murugesan (4):
dt-bindings: clock: add ipq6018 a53 pll compatible
clk: qcom: Add ipq apss pll driver
clk: qcom: Add DT bindings for ipq6018 apss clock controller
clk: qcom: Add ipq6018 apss clock controller
.../devicetree/bindings/clock/qcom,a53pll.yaml | 18 ++++
drivers/clk/qcom/Kconfig | 19 ++++
drivers/clk/qcom/Makefile | 2 +
drivers/clk/qcom/apss-ipq-pll.c | 95 ++++++++++++++++++
drivers/clk/qcom/apss-ipq6018.c | 106 +++++++++++++++++++++
include/dt-bindings/clock/qcom,apss-ipq.h | 12 +++
6 files changed, 252 insertions(+)
create mode 100644 drivers/clk/qcom/apss-ipq-pll.c
create mode 100644 drivers/clk/qcom/apss-ipq6018.c
create mode 100644 include/dt-bindings/clock/qcom,apss-ipq.h
--
2.7.4
The CPU on Qualcomm ipq6018 devices are clocked primarily by a aplha PLL
and xo which are connected to a mux and enable block.
Add support for the mux and enable block which feeds the CPU on ipq6018
devices.
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Sivaprakash Murugesan <[email protected]>
---
drivers/clk/qcom/Kconfig | 11 +++++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/apss-ipq6018.c | 106 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 118 insertions(+)
create mode 100644 drivers/clk/qcom/apss-ipq6018.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 49e265ddcdab..f510ef61db69 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -97,6 +97,17 @@ config IPQ_APSS_PLL
Say Y if you want to support CPU frequency scaling on ipq based
devices.
+config IPQ_APSS_6018
+ tristate "IPQ APSS Clock Controller"
+ select IPQ_APSS_PLL
+ depends on QCOM_APCS_IPC || COMPILE_TEST
+ help
+ Support for APSS clock controller on IPQ platforms. The
+ APSS clock controller manages the Mux and enable block that feeds the
+ CPUs.
+ Say Y if you want to support CPU frequency scaling on
+ ipq based devices.
+
config IPQ_GCC_4019
tristate "IPQ4019 Global Clock Controller"
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 7942c00902ec..21439b94395a 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -20,6 +20,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
+obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c
new file mode 100644
index 000000000000..004f7e1ecdc2
--- /dev/null
+++ b/drivers/clk/qcom/apss-ipq6018.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+#include <linux/module.h>
+
+#include <dt-bindings/clock/qcom,apss-ipq.h>
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-branch.h"
+#include "clk-alpha-pll.h"
+#include "clk-regmap-mux.h"
+
+enum {
+ P_XO,
+ P_APSS_PLL_EARLY,
+};
+
+static const struct clk_parent_data parents_apcs_alias0_clk_src[] = {
+ { .fw_name = "xo" },
+ { .fw_name = "pll" },
+};
+
+static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
+ { P_XO, 0 },
+ { P_APSS_PLL_EARLY, 5 },
+};
+
+static struct clk_regmap_mux apcs_alias0_clk_src = {
+ .reg = 0x0050,
+ .width = 3,
+ .shift = 7,
+ .parent_map = parents_apcs_alias0_clk_src_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "apcs_alias0_clk_src",
+ .parent_data = parents_apcs_alias0_clk_src,
+ .num_parents = 2,
+ .ops = &clk_regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_branch apcs_alias0_core_clk = {
+ .halt_reg = 0x0058,
+ .clkr = {
+ .enable_reg = 0x0058,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "apcs_alias0_core_clk",
+ .parent_hws = (const struct clk_hw *[]){
+ &apcs_alias0_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static const struct regmap_config apss_ipq6018_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x1000,
+ .fast_io = true,
+};
+
+static struct clk_regmap *apss_ipq6018_clks[] = {
+ [APCS_ALIAS0_CLK_SRC] = &apcs_alias0_clk_src.clkr,
+ [APCS_ALIAS0_CORE_CLK] = &apcs_alias0_core_clk.clkr,
+};
+
+static const struct qcom_cc_desc apss_ipq6018_desc = {
+ .config = &apss_ipq6018_regmap_config,
+ .clks = apss_ipq6018_clks,
+ .num_clks = ARRAY_SIZE(apss_ipq6018_clks),
+};
+
+static int apss_ipq6018_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+
+ regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ return qcom_cc_really_probe(pdev, &apss_ipq6018_desc, regmap);
+}
+
+static struct platform_driver apss_ipq6018_driver = {
+ .probe = apss_ipq6018_probe,
+ .driver = {
+ .name = "qcom,apss-ipq6018-clk",
+ },
+};
+
+module_platform_driver(apss_ipq6018_driver);
+
+MODULE_DESCRIPTION("QCOM APSS IPQ 6018 CLK Driver");
+MODULE_LICENSE("GPL v2");
--
2.7.4
Add dt-binding for ipq6018 apss clock controller
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Sivaprakash Murugesan <[email protected]>
---
[V8]
* took Ack from Rob
include/dt-bindings/clock/qcom,apss-ipq.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
create mode 100644 include/dt-bindings/clock/qcom,apss-ipq.h
diff --git a/include/dt-bindings/clock/qcom,apss-ipq.h b/include/dt-bindings/clock/qcom,apss-ipq.h
new file mode 100644
index 000000000000..77b6e05492e2
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,apss-ipq.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H
+#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H
+
+#define APCS_ALIAS0_CLK_SRC 0
+#define APCS_ALIAS0_CORE_CLK 1
+
+#endif
--
2.7.4
Quoting Sivaprakash Murugesan (2020-06-21 21:28:11)
> Add dt-binding for ipq6018 apss clock controller
>
> Acked-by: Rob Herring <[email protected]>
> Signed-off-by: Sivaprakash Murugesan <[email protected]>
> ---
Applied to clk-next
Quoting Sivaprakash Murugesan (2020-06-21 21:28:12)
> The CPU on Qualcomm ipq6018 devices are clocked primarily by a aplha PLL
> and xo which are connected to a mux and enable block.
>
> Add support for the mux and enable block which feeds the CPU on ipq6018
> devices.
>
> Reviewed-by: Stephen Boyd <[email protected]>
> Signed-off-by: Sivaprakash Murugesan <[email protected]>
> ---
Applied to clk-next