Currently firmware is maintaining CCF specific flags and provides to
CCF as it is. But CCF flag numbers may change and that shouldn't mean
that the firmware needs to change. The firmware should have its own
'flag number space' that is distinct from the common clk framework's
'flag number space'. So use firmware specific clock flags in ZynqMP
clock driver instead of CCF flags.
Changes in v3:
- Modify helper function signature to map zynqmp (common)flags with CCF
- Add helper function to map zynqmp (mux & divider)flags with CCF flags
Changes in v2:
- Add helper function to map zynqmp (common)flags with CCF flags.
- Mapped zynqmp clock flags with CCF flags from
zynqmp_clk_register_*() functions instead of
__zynqmp_clock_get_topology() which is changing the flags to struct
clk_init_data instead of the struct clock_topology.
Rajan Vaja (3):
clk: zynqmp: Use firmware specific common clock flags
clk: zynqmp: Use firmware specific divider clock flags
clk: zynqmp: Use firmware specific mux clock flags
drivers/clk/zynqmp/clk-gate-zynqmp.c | 4 +++-
drivers/clk/zynqmp/clk-mux-zynqmp.c | 26 +++++++++++++++++++++--
drivers/clk/zynqmp/clk-zynqmp.h | 41 ++++++++++++++++++++++++++++++++++++
drivers/clk/zynqmp/clkc.c | 32 +++++++++++++++++++++++++++-
drivers/clk/zynqmp/divider.c | 29 ++++++++++++++++++++++---
drivers/clk/zynqmp/pll.c | 4 +++-
6 files changed, 128 insertions(+), 8 deletions(-)
--
2.7.4
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From: Rajan Vaja <[email protected]>
Use ZynqMP specific divider clock flags instead of using CCF flags.
Signed-off-by: Rajan Vaja <[email protected]>
Signed-off-by: Tejas Patel <[email protected]>
Signed-off-by: Amit Sunil Dhamne <[email protected]>
---
drivers/clk/zynqmp/clk-zynqmp.h | 9 +++++++++
drivers/clk/zynqmp/divider.c | 24 +++++++++++++++++++++++-
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h
index 974d3da..9b2ff35e 100644
--- a/drivers/clk/zynqmp/clk-zynqmp.h
+++ b/drivers/clk/zynqmp/clk-zynqmp.h
@@ -32,6 +32,15 @@
/* do not gate, ever */
#define ZYNQMP_CLK_IS_CRITICAL BIT(11)
+/* Type Flags for divider clock */
+#define ZYNQMP_CLK_DIVIDER_ONE_BASED BIT(0)
+#define ZYNQMP_CLK_DIVIDER_POWER_OF_TWO BIT(1)
+#define ZYNQMP_CLK_DIVIDER_ALLOW_ZERO BIT(2)
+#define ZYNQMP_CLK_DIVIDER_HIWORD_MASK BIT(3)
+#define ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST BIT(4)
+#define ZYNQMP_CLK_DIVIDER_READ_ONLY BIT(5)
+#define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO BIT(6)
+
enum topology_type {
TYPE_INVALID,
TYPE_MUX,
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index 775d54f..3b8fad0 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -283,6 +283,28 @@ static u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type)
return ret_payload[1];
}
+static inline unsigned long zynqmp_clk_map_divider_ccf_flags(
+ const u32 zynqmp_type_flag)
+{
+ unsigned long ccf_flag = 0;
+
+ ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ONE_BASED) ?
+ CLK_DIVIDER_ONE_BASED : 0;
+ ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) ?
+ CLK_DIVIDER_POWER_OF_TWO : 0;
+ ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ALLOW_ZERO) ?
+ CLK_DIVIDER_ALLOW_ZERO : 0;
+ ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) ?
+ CLK_DIVIDER_HIWORD_MASK : 0;
+ ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST) ?
+ CLK_DIVIDER_ROUND_CLOSEST : 0;
+ ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_READ_ONLY) ?
+ CLK_DIVIDER_READ_ONLY : 0;
+ ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO) ?
+ CLK_DIVIDER_MAX_AT_ZERO : 0;
+ return ccf_flag;
+}
+
/**
* zynqmp_clk_register_divider() - Register a divider clock
* @name: Name of this clock
@@ -320,7 +342,7 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,
/* struct clk_divider assignments */
div->is_frac = !!((nodes->flag & CLK_FRAC) |
(nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC));
- div->flags = nodes->type_flag;
+ div->flags = zynqmp_clk_map_divider_ccf_flags(nodes->type_flag);
div->hw.init = &init;
div->clk_id = clk_id;
div->div_type = nodes->type;
--
2.7.4
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From: Rajan Vaja <[email protected]>
Currently firmware passes CCF specific flags to ZynqMP clock driver.
So firmware needs to be updated if CCF flags are changed. The firmware
should have its own 'flag number space' that is distinct from the
common clk framework's 'flag number space'. So define and use ZynqMP
specific common clock flags instead of using CCF flags.
Signed-off-by: Rajan Vaja <[email protected]>
Signed-off-by: Tejas Patel <[email protected]>
Signed-off-by: Amit Sunil Dhamne <[email protected]>
---
drivers/clk/zynqmp/clk-gate-zynqmp.c | 4 +++-
drivers/clk/zynqmp/clk-mux-zynqmp.c | 4 +++-
drivers/clk/zynqmp/clk-zynqmp.h | 24 ++++++++++++++++++++++++
drivers/clk/zynqmp/clkc.c | 32 +++++++++++++++++++++++++++++++-
drivers/clk/zynqmp/divider.c | 5 +++--
drivers/clk/zynqmp/pll.c | 4 +++-
6 files changed, 67 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/zynqmp/clk-gate-zynqmp.c b/drivers/clk/zynqmp/clk-gate-zynqmp.c
index 10c9b88..695feaa 100644
--- a/drivers/clk/zynqmp/clk-gate-zynqmp.c
+++ b/drivers/clk/zynqmp/clk-gate-zynqmp.c
@@ -121,7 +121,9 @@ struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,
init.name = name;
init.ops = &zynqmp_clk_gate_ops;
- init.flags = nodes->flag;
+
+ init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);
+
init.parent_names = parents;
init.num_parents = 1;
diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-mux-zynqmp.c
index 0619414..a49b1c5 100644
--- a/drivers/clk/zynqmp/clk-mux-zynqmp.c
+++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c
@@ -120,7 +120,9 @@ struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
init.ops = &zynqmp_clk_mux_ro_ops;
else
init.ops = &zynqmp_clk_mux_ops;
- init.flags = nodes->flag;
+
+ init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);
+
init.parent_names = parents;
init.num_parents = num_parents;
mux->flags = nodes->type_flag;
diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h
index 5beeb41..974d3da 100644
--- a/drivers/clk/zynqmp/clk-zynqmp.h
+++ b/drivers/clk/zynqmp/clk-zynqmp.h
@@ -10,6 +10,28 @@
#include <linux/firmware/xlnx-zynqmp.h>
+/* Common Flags */
+/* must be gated across rate change */
+#define ZYNQMP_CLK_SET_RATE_GATE BIT(0)
+/* must be gated across re-parent */
+#define ZYNQMP_CLK_SET_PARENT_GATE BIT(1)
+/* propagate rate change up one level */
+#define ZYNQMP_CLK_SET_RATE_PARENT BIT(2)
+/* do not gate even if unused */
+#define ZYNQMP_CLK_IGNORE_UNUSED BIT(3)
+/* do not use the cached clk rate */
+#define ZYNQMP_CLK_GET_RATE_NOCACHE BIT(6)
+/* don't re-parent on rate change */
+#define ZYNQMP_CLK_SET_RATE_NO_REPARENT BIT(7)
+/* do not use the cached clk accuracy */
+#define ZYNQMP_CLK_GET_ACCURACY_NOCACHE BIT(8)
+/* recalc rates after notifications */
+#define ZYNQMP_CLK_RECALC_NEW_RATES BIT(9)
+/* clock needs to run to set rate */
+#define ZYNQMP_CLK_SET_RATE_UNGATE BIT(10)
+/* do not gate, ever */
+#define ZYNQMP_CLK_IS_CRITICAL BIT(11)
+
enum topology_type {
TYPE_INVALID,
TYPE_MUX,
@@ -33,6 +55,8 @@ struct clock_topology {
u8 custom_type_flag;
};
+unsigned long zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag);
+
struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
const char * const *parents,
u8 num_parents,
diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
index db8d0d7..d813c34 100644
--- a/drivers/clk/zynqmp/clkc.c
+++ b/drivers/clk/zynqmp/clkc.c
@@ -271,6 +271,33 @@ static int zynqmp_pm_clock_get_topology(u32 clock_id, u32 index,
return ret;
}
+unsigned long zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag)
+{
+ unsigned long ccf_flag = 0;
+
+ ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_SET_RATE_GATE) ?
+ CLK_SET_RATE_GATE : 0;
+ ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_SET_PARENT_GATE) ?
+ CLK_SET_PARENT_GATE : 0;
+ ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_SET_RATE_PARENT) ?
+ CLK_SET_RATE_PARENT : 0;
+ ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_IGNORE_UNUSED) ?
+ CLK_IGNORE_UNUSED : 0;
+ ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_GET_RATE_NOCACHE) ?
+ CLK_GET_RATE_NOCACHE : 0;
+ ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_SET_RATE_NO_REPARENT) ?
+ CLK_SET_RATE_NO_REPARENT : 0;
+ ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_GET_ACCURACY_NOCACHE) ?
+ CLK_GET_ACCURACY_NOCACHE : 0;
+ ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_RECALC_NEW_RATES) ?
+ CLK_RECALC_NEW_RATES : 0;
+ ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_SET_RATE_UNGATE) ?
+ CLK_SET_RATE_UNGATE : 0;
+ ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_IS_CRITICAL) ?
+ CLK_IS_CRITICAL : 0;
+ return ccf_flag;
+}
+
/**
* zynqmp_clk_register_fixed_factor() - Register fixed factor with the
* clock framework
@@ -292,6 +319,7 @@ struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id,
struct zynqmp_pm_query_data qdata = {0};
u32 ret_payload[PAYLOAD_ARG_CNT];
int ret;
+ unsigned long flag;
qdata.qid = PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS;
qdata.arg1 = clk_id;
@@ -303,9 +331,11 @@ struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id,
mult = ret_payload[1];
div = ret_payload[2];
+ flag = zynqmp_clk_map_common_ccf_flags(nodes->flag);
+
hw = clk_hw_register_fixed_factor(NULL, name,
parents[0],
- nodes->flag, mult,
+ flag, mult,
div);
return hw;
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index 66da02b..775d54f 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -311,8 +311,9 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,
init.name = name;
init.ops = &zynqmp_clk_divider_ops;
- /* CLK_FRAC is not defined in the common clk framework */
- init.flags = nodes->flag & ~CLK_FRAC;
+
+ init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);
+
init.parent_names = parents;
init.num_parents = 1;
diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c
index 92f449e..d188924 100644
--- a/drivers/clk/zynqmp/pll.c
+++ b/drivers/clk/zynqmp/pll.c
@@ -302,7 +302,9 @@ struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
init.name = name;
init.ops = &zynqmp_pll_ops;
- init.flags = nodes->flag;
+
+ init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);
+
init.parent_names = parents;
init.num_parents = 1;
--
2.7.4
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From: Rajan Vaja <[email protected]>
Use ZynqMP specific mux clock flags instead of using CCF flags.
Signed-off-by: Rajan Vaja <[email protected]>
Signed-off-by: Tejas Patel <[email protected]>
Signed-off-by: Amit Sunil Dhamne <[email protected]>
---
drivers/clk/zynqmp/clk-mux-zynqmp.c | 22 +++++++++++++++++++++-
drivers/clk/zynqmp/clk-zynqmp.h | 8 ++++++++
2 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-mux-zynqmp.c
index a49b1c5..8a8c960 100644
--- a/drivers/clk/zynqmp/clk-mux-zynqmp.c
+++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c
@@ -90,6 +90,26 @@ static const struct clk_ops zynqmp_clk_mux_ro_ops = {
.get_parent = zynqmp_clk_mux_get_parent,
};
+static inline unsigned long zynqmp_clk_map_mux_ccf_flags(
+ const u32 zynqmp_type_flag)
+{
+ unsigned long ccf_flag = 0;
+
+ ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_MUX_INDEX_ONE) ?
+ CLK_MUX_INDEX_ONE : 0;
+ ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_MUX_INDEX_BIT) ?
+ CLK_MUX_INDEX_BIT : 0;
+ ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_MUX_HIWORD_MASK) ?
+ CLK_MUX_HIWORD_MASK : 0;
+ ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_MUX_READ_ONLY) ?
+ CLK_MUX_READ_ONLY : 0;
+ ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_MUX_ROUND_CLOSEST) ?
+ CLK_MUX_ROUND_CLOSEST : 0;
+ ccf_flag |= (zynqmp_type_flag & ZYNQMP_CLK_MUX_BIG_ENDIAN) ?
+ CLK_MUX_BIG_ENDIAN : 0;
+ return ccf_flag;
+}
+
/**
* zynqmp_clk_register_mux() - Register a mux table with the clock
* framework
@@ -125,7 +145,7 @@ struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
init.parent_names = parents;
init.num_parents = num_parents;
- mux->flags = nodes->type_flag;
+ mux->flags = zynqmp_clk_map_mux_ccf_flags(nodes->type_flag);
mux->hw.init = &init;
mux->clk_id = clk_id;
diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h
index 9b2ff35e..87a2e12 100644
--- a/drivers/clk/zynqmp/clk-zynqmp.h
+++ b/drivers/clk/zynqmp/clk-zynqmp.h
@@ -41,6 +41,14 @@
#define ZYNQMP_CLK_DIVIDER_READ_ONLY BIT(5)
#define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO BIT(6)
+/* Type Flags for mux clock */
+#define ZYNQMP_CLK_MUX_INDEX_ONE BIT(0)
+#define ZYNQMP_CLK_MUX_INDEX_BIT BIT(1)
+#define ZYNQMP_CLK_MUX_HIWORD_MASK BIT(2)
+#define ZYNQMP_CLK_MUX_READ_ONLY BIT(3)
+#define ZYNQMP_CLK_MUX_ROUND_CLOSEST BIT(4)
+#define ZYNQMP_CLK_MUX_BIG_ENDIAN BIT(5)
+
enum topology_type {
TYPE_INVALID,
TYPE_MUX,
--
2.7.4
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Hi Stephen, Reviewers,
I wanted to gently follow up on the review of this patch.
Thanks,
Amit
> -----Original Message-----
> From: Amit Sunil Dhamne <[email protected]>
> Sent: Monday, August 3, 2020 11:44 PM
> To: [email protected]; [email protected];
> [email protected]; Michal Simek <[email protected]>;
> [email protected]; [email protected]
> Cc: Rajan Vaja <[email protected]>; Jolly Shah <[email protected]>; Tejas
> Patel <[email protected]>; [email protected]; linux-
> [email protected]; Amit Sunil Dhamne <[email protected]>
> Subject: [PATCH v3 0/3] clk: zynqmp: Add firmware specific clock flags
>
> Currently firmware is maintaining CCF specific flags and provides to CCF as it
> is. But CCF flag numbers may change and that shouldn't mean that the
> firmware needs to change. The firmware should have its own 'flag number
> space' that is distinct from the common clk framework's 'flag number space'.
> So use firmware specific clock flags in ZynqMP clock driver instead of CCF
> flags.
>
> Changes in v3:
> - Modify helper function signature to map zynqmp (common)flags with CCF
> - Add helper function to map zynqmp (mux & divider)flags with CCF flags
>
> Changes in v2:
> - Add helper function to map zynqmp (common)flags with CCF flags.
> - Mapped zynqmp clock flags with CCF flags from
> zynqmp_clk_register_*() functions instead of
> __zynqmp_clock_get_topology() which is changing the flags to struct
> clk_init_data instead of the struct clock_topology.
>
> Rajan Vaja (3):
> clk: zynqmp: Use firmware specific common clock flags
> clk: zynqmp: Use firmware specific divider clock flags
> clk: zynqmp: Use firmware specific mux clock flags
>
> drivers/clk/zynqmp/clk-gate-zynqmp.c | 4 +++- drivers/clk/zynqmp/clk-
> mux-zynqmp.c | 26 +++++++++++++++++++++--
> drivers/clk/zynqmp/clk-zynqmp.h | 41
> ++++++++++++++++++++++++++++++++++++
> drivers/clk/zynqmp/clkc.c | 32 +++++++++++++++++++++++++++-
> drivers/clk/zynqmp/divider.c | 29 ++++++++++++++++++++++---
> drivers/clk/zynqmp/pll.c | 4 +++-
> 6 files changed, 128 insertions(+), 8 deletions(-)
>
> --
> 2.7.4
Quoting Amit Sunil Dhamne (2020-08-03 23:44:15)
> diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
> index db8d0d7..d813c34 100644
> --- a/drivers/clk/zynqmp/clkc.c
> +++ b/drivers/clk/zynqmp/clkc.c
> @@ -271,6 +271,33 @@ static int zynqmp_pm_clock_get_topology(u32 clock_id, u32 index,
> return ret;
> }
>
> +unsigned long zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag)
> +{
> + unsigned long ccf_flag = 0;
> +
> + ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_SET_RATE_GATE) ?
Please use an if condition instead
if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_GATE)
ccf_flag |= CLK_SET_RATE_GATE;
if (zynqmp_flag & ...)
> + CLK_SET_RATE_GATE : 0;
> + ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_SET_PARENT_GATE) ?
> + CLK_SET_PARENT_GATE : 0;
> + ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_SET_RATE_PARENT) ?
> + CLK_SET_RATE_PARENT : 0;
> + ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_IGNORE_UNUSED) ?
> + CLK_IGNORE_UNUSED : 0;
> + ccf_flag |= (zynqmp_flag & ZYNQMP_CLK_GET_RATE_NOCACHE) ?