The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as
compared to 3 in FU540. Update the DT documentation accordingly with
"compatible" and "interrupt" property changes.
Signed-off-by: Yash Shah <[email protected]>
---
.../devicetree/bindings/riscv/sifive-l2-cache.yaml | 33 +++++++++++++++++-----
1 file changed, 26 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
index efc0198..4873d5c 100644
--- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
@@ -27,6 +27,7 @@ select:
items:
- enum:
- sifive,fu540-c000-ccache
+ - sifive,fu740-c000-ccache
required:
- compatible
@@ -34,7 +35,9 @@ select:
properties:
compatible:
items:
- - const: sifive,fu540-c000-ccache
+ - enum:
+ - sifive,fu540-c000-ccache
+ - sifive,fu740-c000-ccache
- const: cache
cache-block-size:
@@ -51,12 +54,6 @@ properties:
cache-unified: true
- interrupts:
- description: |
- Must contain entries for DirError, DataError and DataFail signals.
- minItems: 3
- maxItems: 3
-
reg:
maxItems: 1
@@ -67,6 +64,28 @@ properties:
The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
The reserved memory node should be defined as per the bindings in reserved-memory.txt.
+if:
+ properties:
+ compatible:
+ contains:
+ const: sifive,fu540-c000-ccache
+
+then:
+ properties:
+ interrupts:
+ description: |
+ Must contain entries for DirError, DataError and DataFail signals.
+ minItems: 3
+ maxItems: 3
+
+else:
+ properties:
+ interrupts:
+ description: |
+ Must contain entries for DirError, DirFail, DataError, DataFail signals.
+ minItems: 4
+ maxItems: 4
+
additionalProperties: false
required:
--
2.7.4
SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540.
Update the L2 cache controller driver to support this additional
interrupt in case of FU740-C000 chip.
Signed-off-by: Yash Shah <[email protected]>
---
drivers/soc/sifive/sifive_l2_cache.c | 49 +++++++++++++++++++++++++++++++-----
1 file changed, 43 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
index 44d7e19..4e5e841 100644
--- a/drivers/soc/sifive/sifive_l2_cache.c
+++ b/drivers/soc/sifive/sifive_l2_cache.c
@@ -17,6 +17,10 @@
#define SIFIVE_L2_DIRECCFIX_HIGH 0x104
#define SIFIVE_L2_DIRECCFIX_COUNT 0x108
+#define SIFIVE_L2_DIRECCFAIL_LOW 0x120
+#define SIFIVE_L2_DIRECCFAIL_HIGH 0x124
+#define SIFIVE_L2_DIRECCFAIL_COUNT 0x128
+
#define SIFIVE_L2_DATECCFIX_LOW 0x140
#define SIFIVE_L2_DATECCFIX_HIGH 0x144
#define SIFIVE_L2_DATECCFIX_COUNT 0x148
@@ -29,7 +33,7 @@
#define SIFIVE_L2_WAYENABLE 0x08
#define SIFIVE_L2_ECCINJECTERR 0x40
-#define SIFIVE_L2_MAX_ECCINTR 3
+#define SIFIVE_L2_MAX_ECCINTR 4
static void __iomem *l2_base;
static int g_irq[SIFIVE_L2_MAX_ECCINTR];
@@ -37,6 +41,7 @@ static struct riscv_cacheinfo_ops l2_cache_ops;
enum {
DIR_CORR = 0,
+ DIR_UNCORR,
DATA_CORR,
DATA_UNCORR,
};
@@ -93,6 +98,7 @@ static void l2_config_read(void)
static const struct of_device_id sifive_l2_ids[] = {
{ .compatible = "sifive,fu540-c000-ccache" },
+ { .compatible = "sifive,fu740-c000-ccache" },
{ /* end of table */ },
};
@@ -155,6 +161,15 @@ static irqreturn_t l2_int_handler(int irq, void *device)
atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
"DirECCFix");
}
+ if (irq == g_irq[DIR_UNCORR]) {
+ add_h = readl(l2_base + SIFIVE_L2_DIRECCFAIL_HIGH);
+ add_l = readl(l2_base + SIFIVE_L2_DIRECCFAIL_LOW);
+ /* Reading this register clears the DirFail interrupt sig */
+ readl(l2_base + SIFIVE_L2_DIRECCFAIL_COUNT);
+ atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE,
+ "DirECCFail");
+ panic("L2CACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l);
+ }
if (irq == g_irq[DATA_CORR]) {
add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH);
add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW);
@@ -179,9 +194,9 @@ static irqreturn_t l2_int_handler(int irq, void *device)
static int __init sifive_l2_init(void)
{
+ int i, k, rc, intr_num, offset = 0;
struct device_node *np;
struct resource res;
- int i, rc;
np = of_find_matching_node(NULL, sifive_l2_ids);
if (!np)
@@ -194,11 +209,33 @@ static int __init sifive_l2_init(void)
if (!l2_base)
return -ENOMEM;
- for (i = 0; i < SIFIVE_L2_MAX_ECCINTR; i++) {
- g_irq[i] = irq_of_parse_and_map(np, i);
- rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
+ intr_num = of_property_count_u32_elems(np, "interrupts");
+ if (!intr_num) {
+ pr_err("L2CACHE: no interrupts property\n");
+ return -ENODEV;
+ }
+
+ /*
+ * Only FU540 have 3 interrupts. Rest all other variants have
+ * 4 interrupts (+dirfail). Therefore offset is required to skip
+ * 'dirfail' interrupt entry in case of FU540
+ */
+ if (of_device_is_compatible(np, "sifive,fu540-c000-ccache"))
+ offset = 1;
+
+ g_irq[0] = irq_of_parse_and_map(np, 0);
+ rc = request_irq(g_irq[0], l2_int_handler, 0, "l2_ecc", NULL);
+ if (rc) {
+ pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[0]);
+ return rc;
+ }
+
+ for (i = 1; i < intr_num; i++) {
+ k = i + offset;
+ g_irq[k] = irq_of_parse_and_map(np, i);
+ rc = request_irq(g_irq[k], l2_int_handler, 0, "l2_ecc", NULL);
if (rc) {
- pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
+ pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[k]);
return rc;
}
}
--
2.7.4
On Thu, Nov 12, 2020 at 02:41:13PM +0530, Yash Shah wrote:
> The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as
> compared to 3 in FU540. Update the DT documentation accordingly with
> "compatible" and "interrupt" property changes.
>
> Signed-off-by: Yash Shah <[email protected]>
> ---
> .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 33 +++++++++++++++++-----
> 1 file changed, 26 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> index efc0198..4873d5c 100644
> --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> @@ -27,6 +27,7 @@ select:
> items:
> - enum:
> - sifive,fu540-c000-ccache
> + - sifive,fu740-c000-ccache
>
> required:
> - compatible
> @@ -34,7 +35,9 @@ select:
> properties:
> compatible:
> items:
> - - const: sifive,fu540-c000-ccache
> + - enum:
> + - sifive,fu540-c000-ccache
> + - sifive,fu740-c000-ccache
> - const: cache
>
> cache-block-size:
> @@ -51,12 +54,6 @@ properties:
>
> cache-unified: true
>
> - interrupts:
> - description: |
> - Must contain entries for DirError, DataError and DataFail signals.
> - minItems: 3
> - maxItems: 3
Keep this here and just change maxItems to 4. Really, what each
interrupt is should be listed out as an 'items' entry.
> -
> reg:
> maxItems: 1
>
> @@ -67,6 +64,28 @@ properties:
> The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
> The reserved memory node should be defined as per the bindings in reserved-memory.txt.
>
> +if:
> + properties:
> + compatible:
> + contains:
> + const: sifive,fu540-c000-ccache
> +
> +then:
> + properties:
> + interrupts:
> + description: |
> + Must contain entries for DirError, DataError and DataFail signals.
> + minItems: 3
> + maxItems: 3
Here you just need 'maxItems: 3'.
> +
> +else:
> + properties:
> + interrupts:
> + description: |
> + Must contain entries for DirError, DirFail, DataError, DataFail signals.
DirFail should be last so you keep the same indices.
> + minItems: 4
> + maxItems: 4
And 'minItems: 4'
> +
> additionalProperties: false
>
> required:
> --
> 2.7.4
>
> -----Original Message-----
> From: Rob Herring <[email protected]>
> Sent: 21 November 2020 18:25
> To: Yash Shah <[email protected]>
> Cc: Paul Walmsley ( Sifive) <[email protected]>;
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> Sagar Kadam <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; Sachin Ghadi <[email protected]>
> Subject: Re: [PATCH 1/2] RISC-V: Update l2 cache DT documentation to add
> support for SiFive FU740
>
> [External Email] Do not click links or attachments unless you recognize the
> sender and know the content is safe
>
> On Thu, Nov 12, 2020 at 02:41:13PM +0530, Yash Shah wrote:
> > The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as
> > compared to 3 in FU540. Update the DT documentation accordingly with
> > "compatible" and "interrupt" property changes.
> >
> > Signed-off-by: Yash Shah <[email protected]>
> > ---
> > .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 33
> > +++++++++++++++++-----
> > 1 file changed, 26 insertions(+), 7 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> > b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> > index efc0198..4873d5c 100644
> > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
<...>
> > @@ -51,12 +54,6 @@ properties:
> >
> > cache-unified: true
> >
> > - interrupts:
> > - description: |
> > - Must contain entries for DirError, DataError and DataFail signals.
> > - minItems: 3
> > - maxItems: 3
>
> Keep this here and just change maxItems to 4. Really, what each interrupt is
> should be listed out as an 'items' entry.
>
Sure will send a v2 with the above modifications.
<...>
>
> > +
> > +else:
> > + properties:
> > + interrupts:
> > + description: |
> > + Must contain entries for DirError, DirFail, DataError, DataFail signals.
>
> DirFail should be last so you keep the same indices.
Actually, the interrupts have been numbered like that in FU740 SoCs and the driver expects the interrupts to be in this order.
I will keep the same order for v2 as well. Let me know if you still disagree.
Thanks for your review.
- Yash
On Mon, Nov 23, 2020 at 3:32 AM Yash Shah <[email protected]> wrote:
>
> > -----Original Message-----
> > From: Rob Herring <[email protected]>
> > Sent: 21 November 2020 18:25
> > To: Yash Shah <[email protected]>
> > Cc: Paul Walmsley ( Sifive) <[email protected]>;
> > [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected];
> > Sagar Kadam <[email protected]>; [email protected];
> > [email protected]; [email protected]; [email protected];
> > [email protected]; Sachin Ghadi <[email protected]>
> > Subject: Re: [PATCH 1/2] RISC-V: Update l2 cache DT documentation to add
> > support for SiFive FU740
> >
> > [External Email] Do not click links or attachments unless you recognize the
> > sender and know the content is safe
> >
> > On Thu, Nov 12, 2020 at 02:41:13PM +0530, Yash Shah wrote:
> > > The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as
> > > compared to 3 in FU540. Update the DT documentation accordingly with
> > > "compatible" and "interrupt" property changes.
> > >
> > > Signed-off-by: Yash Shah <[email protected]>
> > > ---
> > > .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 33
> > > +++++++++++++++++-----
> > > 1 file changed, 26 insertions(+), 7 deletions(-)
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> > > b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> > > index efc0198..4873d5c 100644
> > > --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> > > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
>
> <...>
>
> > > @@ -51,12 +54,6 @@ properties:
> > >
> > > cache-unified: true
> > >
> > > - interrupts:
> > > - description: |
> > > - Must contain entries for DirError, DataError and DataFail signals.
> > > - minItems: 3
> > > - maxItems: 3
> >
> > Keep this here and just change maxItems to 4. Really, what each interrupt is
> > should be listed out as an 'items' entry.
> >
>
> Sure will send a v2 with the above modifications.
>
> <...>
>
> >
> > > +
> > > +else:
> > > + properties:
> > > + interrupts:
> > > + description: |
> > > + Must contain entries for DirError, DirFail, DataError, DataFail signals.
> >
> > DirFail should be last so you keep the same indices.
>
> Actually, the interrupts have been numbered like that in FU740 SoCs and the driver expects the interrupts to be in this order.
> I will keep the same order for v2 as well. Let me know if you still disagree.
Numbered within the cache block or the interrupt controller? If the
former, then fine. The latter would be outside the scope of the
binding. Another SoC could hook up interrupts differently.
It's going to be easier for the driver to deal with 1 new irq index
rather than 2 whole sets of different indices, but if you want to do
it the hard way...
Rob