2021-02-12 07:36:07

by Rajendra Nayak

Subject: [PATCH 05/13] arm64: dts: qcom: sc7280: Add RSC and PDC devices

From: Maulik Shah <[email protected]>

Add PDC interrupt controller along with apps RSC device.
Also add reserved memory for command_db.

Signed-off-by: Maulik Shah <[email protected]>
Signed-off-by: Rajendra Nayak <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 44 ++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 1fe2eba..7848e88 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -7,6 +7,7 @@

#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>

/ {
interrupt-parent = <&intc>;
@@ -30,6 +31,18 @@
};
};

+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ aop_cmd_db_mem: memory@80860000 {
+ reg = <0x0 0x80860000 0x0 0x20000>;
+ compatible = "qcom,cmd-db";
+ no-map;
+ };
+ };
+
cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -189,6 +202,19 @@
};
};

+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,sc7280-pdc", "qcom,pdc";
+ reg = <0 0xb220000 0 0x30000>;
+ qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
+ <55 306 4>, <59 312 3>, <62 374 2>,
+ <64 434 2>, <66 438 3>, <69 86 1>,
+ <70 520 54>, <124 609 31>, <155 63 1>,
+ <156 716 12>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
tlmm: pinctrl@f100000 {
compatible = "qcom,sc7280-pinctrl";
reg = <0 0xf100000 0 0x1000000>;
@@ -198,6 +224,7 @@
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 175>;
+ wakeup-parent = <&pdc>;

qup_uart5_default: qup-uart5-default {
pins = "gpio46", "gpio47";
@@ -282,6 +309,23 @@
status = "disabled";
};
};
+
+ apps_rsc: rsc@18200000 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0 0x18200000 0 0x10000>,
+ <0 0x18210000 0 0x10000>,
+ <0 0x18220000 0 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 2>,
+ <SLEEP_TCS 3>,
+ <WAKE_TCS 3>,
+ <CONTROL_TCS 1>;
+ };
};

timer {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

2021-02-23 09:11:01

by Stephen Boyd

Subject: Re: [PATCH 05/13] arm64: dts: qcom: sc7280: Add RSC and PDC devices

Quoting Rajendra Nayak (2021-02-11 23:28:42)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 1fe2eba..7848e88 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -7,6 +7,7 @@
>
> #include <dt-bindings/clock/qcom,gcc-sc7280.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
>
> / {
> interrupt-parent = <&intc>;
> @@ -30,6 +31,18 @@
> };
> };
>
> + reserved_memory: reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + aop_cmd_db_mem: memory@80860000 {
> + reg = <0x0 0x80860000 0x0 0x20000>;
> + compatible = "qcom,cmd-db";
> + no-map;
> + };
> + };
> +
> cpus {
> #address-cells = <2>;
> #size-cells = <0>;
> @@ -189,6 +202,19 @@
> };
> };
>
> + pdc: interrupt-controller@b220000 {
> + compatible = "qcom,sc7280-pdc", "qcom,pdc";
> + reg = <0 0xb220000 0 0x30000>;

Can you pad out reg to 8 digits? 0x0b220000

> + qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
> + <55 306 4>, <59 312 3>, <62 374 2>,
> + <64 434 2>, <66 438 3>, <69 86 1>,
> + <70 520 54>, <124 609 31>, <155 63 1>,
> + <156 716 12>;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&intc>;
> + interrupt-controller;
> + };
> +
> tlmm: pinctrl@f100000 {
> compatible = "qcom,sc7280-pinctrl";
> reg = <0 0xf100000 0 0x1000000>;

The same applies to the previous patch. Sorry for missing that.

> @@ -198,6 +224,7 @@
> interrupt-controller;
> #interrupt-cells = <2>;
> gpio-ranges = <&tlmm 0 0 175>;
> + wakeup-parent = <&pdc>;
>
> qup_uart5_default: qup-uart5-default {
> pins = "gpio46", "gpio47";
> @@ -282,6 +309,23 @@
> status = "disabled";
> };
> };
> +
> + apps_rsc: rsc@18200000 {
> + compatible = "qcom,rpmh-rsc";
> + reg = <0 0x18200000 0 0x10000>,
> + <0 0x18210000 0 0x10000>,
> + <0 0x18220000 0 0x10000>;
> + reg-names = "drv-0", "drv-1", "drv-2";
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + qcom,tcs-offset = <0xd00>;
> + qcom,drv-id = <2>;
> + qcom,tcs-config = <ACTIVE_TCS 2>,
> + <SLEEP_TCS 3>,
> + <WAKE_TCS 3>,
> + <CONTROL_TCS 1>;
> + };
> };