From: Nina Wu <[email protected]>
To support newer hardware architecture of devapc,
update device tree bindings.
Signed-off-by: Nina Wu <[email protected]>
---
Documentation/devicetree/bindings/soc/mediatek/devapc.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
index 31e4d3c..42b284e 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
@@ -20,11 +20,17 @@ properties:
compatible:
enum:
- mediatek,mt6779-devapc
+ - mediatek,mt8192-devapc
reg:
description: The base address of devapc register bank
maxItems: 1
+ vio-idx-num:
+ description: The number of the devices controlled by devapc
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+
interrupts:
description: A single interrupt specifier
maxItems: 1
@@ -40,6 +46,7 @@ properties:
required:
- compatible
- reg
+ - vio-idx-num
- interrupts
- clocks
- clock-names
@@ -54,6 +61,7 @@ examples:
devapc: devapc@10207000 {
compatible = "mediatek,mt6779-devapc";
reg = <0x10207000 0x1000>;
+ vio-idx-num = <511>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg_ao CLK_INFRA_DEVICE_APC>;
clock-names = "devapc-infra-clock";
--
2.6.4
From: Nina Wu <[email protected]>
For new ICs, there are multiple devapc HWs for different subsys.
They all share the same IRQ number.
Signed-off-by: Nina Wu <[email protected]>
---
drivers/soc/mediatek/mtk-devapc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c
index a0f6fbd..68c3e35 100644
--- a/drivers/soc/mediatek/mtk-devapc.c
+++ b/drivers/soc/mediatek/mtk-devapc.c
@@ -268,7 +268,7 @@ static int mtk_devapc_probe(struct platform_device *pdev)
return -EINVAL;
ret = devm_request_irq(&pdev->dev, devapc_irq, devapc_violation_irq,
- IRQF_TRIGGER_NONE, "devapc", ctx);
+ IRQF_TRIGGER_NONE | IRQF_SHARED, "devapc", ctx);
if (ret) {
clk_disable_unprepare(ctx->infra_clk);
return ret;
--
2.6.4
From: Nina Wu <[email protected]>
For new ICs, there are multiple devapc HWs for different subsys.
For example, there is devapc respectively for infra, peri, peri2, etc.
So we rename the variable 'infra_base' to 'base' for code readability.
Signed-off-by: Nina Wu <[email protected]>
---
drivers/soc/mediatek/mtk-devapc.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c
index 68c3e35..bcf6e3c 100644
--- a/drivers/soc/mediatek/mtk-devapc.c
+++ b/drivers/soc/mediatek/mtk-devapc.c
@@ -45,7 +45,7 @@ struct mtk_devapc_data {
struct mtk_devapc_context {
struct device *dev;
- void __iomem *infra_base;
+ void __iomem *base;
u32 vio_idx_num;
struct clk *infra_clk;
const struct mtk_devapc_data *data;
@@ -56,7 +56,7 @@ static void clear_vio_status(struct mtk_devapc_context *ctx)
void __iomem *reg;
int i;
- reg = ctx->infra_base + ctx->data->vio_sta_offset;
+ reg = ctx->base + ctx->data->vio_sta_offset;
for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num - 1); i++)
writel(GENMASK(31, 0), reg + 4 * i);
@@ -71,7 +71,7 @@ static void mask_module_irq(struct mtk_devapc_context *ctx, bool mask)
u32 val;
int i;
- reg = ctx->infra_base + ctx->data->vio_mask_offset;
+ reg = ctx->base + ctx->data->vio_mask_offset;
if (mask)
val = GENMASK(31, 0);
@@ -113,11 +113,11 @@ static int devapc_sync_vio_dbg(struct mtk_devapc_context *ctx)
int ret;
u32 val;
- pd_vio_shift_sta_reg = ctx->infra_base +
+ pd_vio_shift_sta_reg = ctx->base +
ctx->data->vio_shift_sta_offset;
- pd_vio_shift_sel_reg = ctx->infra_base +
+ pd_vio_shift_sel_reg = ctx->base +
ctx->data->vio_shift_sel_offset;
- pd_vio_shift_con_reg = ctx->infra_base +
+ pd_vio_shift_con_reg = ctx->base +
ctx->data->vio_shift_con_offset;
/* Find the minimum shift group which has violation */
@@ -159,8 +159,8 @@ static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx)
void __iomem *vio_dbg0_reg;
void __iomem *vio_dbg1_reg;
- vio_dbg0_reg = ctx->infra_base + ctx->data->vio_dbg0_offset;
- vio_dbg1_reg = ctx->infra_base + ctx->data->vio_dbg1_offset;
+ vio_dbg0_reg = ctx->base + ctx->data->vio_dbg0_offset;
+ vio_dbg1_reg = ctx->base + ctx->data->vio_dbg1_offset;
vio_dbgs.vio_dbg0 = readl(vio_dbg0_reg);
vio_dbgs.vio_dbg1 = readl(vio_dbg1_reg);
@@ -198,7 +198,7 @@ static irqreturn_t devapc_violation_irq(int irq_number, void *data)
*/
static void start_devapc(struct mtk_devapc_context *ctx)
{
- writel(BIT(31), ctx->infra_base + ctx->data->apc_con_offset);
+ writel(BIT(31), ctx->base + ctx->data->apc_con_offset);
mask_module_irq(ctx, false);
}
@@ -210,7 +210,7 @@ static void stop_devapc(struct mtk_devapc_context *ctx)
{
mask_module_irq(ctx, true);
- writel(BIT(2), ctx->infra_base + ctx->data->apc_con_offset);
+ writel(BIT(2), ctx->base + ctx->data->apc_con_offset);
}
static const struct mtk_devapc_data devapc_mt6779 = {
@@ -249,8 +249,8 @@ static int mtk_devapc_probe(struct platform_device *pdev)
ctx->data = of_device_get_match_data(&pdev->dev);
ctx->dev = &pdev->dev;
- ctx->infra_base = of_iomap(node, 0);
- if (!ctx->infra_base)
+ ctx->base = of_iomap(node, 0);
+ if (!ctx->base)
return -EINVAL;
if (of_property_read_u32(node, "vio_idx_num", &ctx->vio_idx_num))
--
2.6.4
From: Nina Wu <[email protected]>
For new ICs, there are multiple devapc HWs for different subsys.
The number of devices controlled by each devapc (i.e. 'vio_idx_num'
in the code) varies.
We move this info from compatible data to DT so that we do not need
to add n compatible for a certain IC which has n devapc HWs with
different 'vio_idx_num', respectively.
Signed-off-by: Nina Wu <[email protected]>
---
drivers/soc/mediatek/mtk-devapc.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c
index f1cea04..a0f6fbd 100644
--- a/drivers/soc/mediatek/mtk-devapc.c
+++ b/drivers/soc/mediatek/mtk-devapc.c
@@ -32,9 +32,6 @@ struct mtk_devapc_vio_dbgs {
};
struct mtk_devapc_data {
- /* numbers of violation index */
- u32 vio_idx_num;
-
/* reg offset */
u32 vio_mask_offset;
u32 vio_sta_offset;
@@ -49,6 +46,7 @@ struct mtk_devapc_data {
struct mtk_devapc_context {
struct device *dev;
void __iomem *infra_base;
+ u32 vio_idx_num;
struct clk *infra_clk;
const struct mtk_devapc_data *data;
};
@@ -60,10 +58,10 @@ static void clear_vio_status(struct mtk_devapc_context *ctx)
reg = ctx->infra_base + ctx->data->vio_sta_offset;
- for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++)
+ for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num - 1); i++)
writel(GENMASK(31, 0), reg + 4 * i);
- writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, 0),
+ writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num - 1), 0),
reg + 4 * i);
}
@@ -80,15 +78,15 @@ static void mask_module_irq(struct mtk_devapc_context *ctx, bool mask)
else
val = 0;
- for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++)
+ for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num - 1); i++)
writel(val, reg + 4 * i);
val = readl(reg + 4 * i);
if (mask)
- val |= GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1,
+ val |= GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num - 1),
0);
else
- val &= ~GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1,
+ val &= ~GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num - 1),
0);
writel(val, reg + 4 * i);
@@ -216,7 +214,6 @@ static void stop_devapc(struct mtk_devapc_context *ctx)
}
static const struct mtk_devapc_data devapc_mt6779 = {
- .vio_idx_num = 511,
.vio_mask_offset = 0x0,
.vio_sta_offset = 0x400,
.vio_dbg0_offset = 0x900,
@@ -256,6 +253,9 @@ static int mtk_devapc_probe(struct platform_device *pdev)
if (!ctx->infra_base)
return -EINVAL;
+ if (of_property_read_u32(node, "vio_idx_num", &ctx->vio_idx_num))
+ return -EINVAL;
+
devapc_irq = irq_of_parse_and_map(node, 0);
if (!devapc_irq)
return -EINVAL;
--
2.6.4
From: Nina Wu <[email protected]>
There are 3 debug info registers in new ICs while in legacy ones,
we have only 2. When dumping the debug info, we need to check first
if the 3rd debug register exists and then we can konw how to decipher
the debug info.
Signed-off-by: Nina Wu <[email protected]>
---
drivers/soc/mediatek/mtk-devapc.c | 31 +++++++++++++++++++++++++++++--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c
index bcf6e3c..af55c01 100644
--- a/drivers/soc/mediatek/mtk-devapc.c
+++ b/drivers/soc/mediatek/mtk-devapc.c
@@ -26,9 +26,19 @@ struct mtk_devapc_vio_dbgs {
u32 addr_h:4;
u32 resv:4;
} dbg0_bits;
+
+ /* Not used, reference only */
+ struct {
+ u32 dmnid:6;
+ u32 vio_w:1;
+ u32 vio_r:1;
+ u32 addr_h:4;
+ u32 resv:20;
+ } dbg0_bits_ver2;
};
u32 vio_dbg1;
+ u32 vio_dbg2;
};
struct mtk_devapc_data {
@@ -37,6 +47,7 @@ struct mtk_devapc_data {
u32 vio_sta_offset;
u32 vio_dbg0_offset;
u32 vio_dbg1_offset;
+ u32 vio_dbg2_offset;
u32 apc_con_offset;
u32 vio_shift_sta_offset;
u32 vio_shift_sel_offset;
@@ -158,12 +169,29 @@ static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx)
struct mtk_devapc_vio_dbgs vio_dbgs;
void __iomem *vio_dbg0_reg;
void __iomem *vio_dbg1_reg;
+ void __iomem *vio_dbg2_reg;
+ u32 vio_addr, bus_id;
vio_dbg0_reg = ctx->base + ctx->data->vio_dbg0_offset;
vio_dbg1_reg = ctx->base + ctx->data->vio_dbg1_offset;
+ vio_dbg2_reg = ctx->base + ctx->data->vio_dbg2_offset;
vio_dbgs.vio_dbg0 = readl(vio_dbg0_reg);
vio_dbgs.vio_dbg1 = readl(vio_dbg1_reg);
+ vio_dbgs.vio_dbg2 = readl(vio_dbg2_reg);
+
+ if (!ctx->data->vio_dbg2_offset) {
+ /* arch version 1 */
+ bus_id = vio_dbgs.dbg0_bits.mstid;
+ vio_addr = vio_dbgs.vio_dbg1;
+ } else {
+ /* arch version 2 */
+ bus_id = vio_dbgs.vio_dbg1;
+ vio_addr = vio_dbgs.vio_dbg2;
+
+ /* To align with the bit definition of arch_ver 1 */
+ vio_dbgs.vio_dbg0 = (vio_dbgs.vio_dbg0 << 16);
+ }
/* Print violation information */
if (vio_dbgs.dbg0_bits.vio_w)
@@ -172,8 +200,7 @@ static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx)
dev_info(ctx->dev, "Read Violation\n");
dev_info(ctx->dev, "Bus ID:0x%x, Dom ID:0x%x, Vio Addr:0x%x\n",
- vio_dbgs.dbg0_bits.mstid, vio_dbgs.dbg0_bits.dmnid,
- vio_dbgs.vio_dbg1);
+ bus_id, vio_dbgs.dbg0_bits.dmnid, vio_addr);
}
/*
--
2.6.4
From: Nina Wu <[email protected]>
Add compatible to support mt8192.
Signed-off-by: Nina Wu <[email protected]>
---
drivers/soc/mediatek/mtk-devapc.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c
index af55c01..a5c15b5 100644
--- a/drivers/soc/mediatek/mtk-devapc.c
+++ b/drivers/soc/mediatek/mtk-devapc.c
@@ -251,11 +251,26 @@ static const struct mtk_devapc_data devapc_mt6779 = {
.vio_shift_con_offset = 0xF20,
};
+static const struct mtk_devapc_data devapc_mt8192 = {
+ .vio_mask_offset = 0x0,
+ .vio_sta_offset = 0x400,
+ .vio_dbg0_offset = 0x900,
+ .vio_dbg1_offset = 0x904,
+ .vio_dbg2_offset = 0x908,
+ .apc_con_offset = 0xF00,
+ .vio_shift_sta_offset = 0xF20,
+ .vio_shift_sel_offset = 0xF30,
+ .vio_shift_con_offset = 0xF10,
+};
+
static const struct of_device_id mtk_devapc_dt_match[] = {
{
.compatible = "mediatek,mt6779-devapc",
.data = &devapc_mt6779,
}, {
+ .compatible = "mediatek,mt8192-devapc",
+ .data = &devapc_mt8192,
+ }, {
},
};
--
2.6.4
On 01/04/2021 08:38, Nina Wu wrote:
> From: Nina Wu <[email protected]>
>
> For new ICs, there are multiple devapc HWs for different subsys.
> The number of devices controlled by each devapc (i.e. 'vio_idx_num'
> in the code) varies.
> We move this info from compatible data to DT so that we do not need
> to add n compatible for a certain IC which has n devapc HWs with
> different 'vio_idx_num', respectively.
>
> Signed-off-by: Nina Wu <[email protected]>
> ---
> drivers/soc/mediatek/mtk-devapc.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c
> index f1cea04..a0f6fbd 100644
> --- a/drivers/soc/mediatek/mtk-devapc.c
> +++ b/drivers/soc/mediatek/mtk-devapc.c
> @@ -32,9 +32,6 @@ struct mtk_devapc_vio_dbgs {
> };
>
> struct mtk_devapc_data {
> - /* numbers of violation index */
> - u32 vio_idx_num;
> -
> /* reg offset */
> u32 vio_mask_offset;
> u32 vio_sta_offset;
> @@ -49,6 +46,7 @@ struct mtk_devapc_data {
> struct mtk_devapc_context {
> struct device *dev;
> void __iomem *infra_base;
> + u32 vio_idx_num;
We should try to stay backwards compatible (newer kernel with older DTS). I
think we don't need to move vio_idx_num to mtk_devapc_context. Just don't
declare it in the per SoC match data. More details see below...
> struct clk *infra_clk;
> const struct mtk_devapc_data *data;
> };
> @@ -60,10 +58,10 @@ static void clear_vio_status(struct mtk_devapc_context *ctx)
>
> reg = ctx->infra_base + ctx->data->vio_sta_offset;
>
> - for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++)
> + for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num - 1); i++)
> writel(GENMASK(31, 0), reg + 4 * i);
>
> - writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, 0),
> + writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num - 1), 0),
> reg + 4 * i);
> }
>
> @@ -80,15 +78,15 @@ static void mask_module_irq(struct mtk_devapc_context *ctx, bool mask)
> else
> val = 0;
>
> - for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++)
> + for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num - 1); i++)
> writel(val, reg + 4 * i);
>
> val = readl(reg + 4 * i);
> if (mask)
> - val |= GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1,
> + val |= GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num - 1),
> 0);
> else
> - val &= ~GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1,
> + val &= ~GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num - 1),
> 0);
>
> writel(val, reg + 4 * i);
> @@ -216,7 +214,6 @@ static void stop_devapc(struct mtk_devapc_context *ctx)
> }
>
> static const struct mtk_devapc_data devapc_mt6779 = {
> - .vio_idx_num = 511,
> .vio_mask_offset = 0x0,
> .vio_sta_offset = 0x400,
> .vio_dbg0_offset = 0x900,
> @@ -256,6 +253,9 @@ static int mtk_devapc_probe(struct platform_device *pdev)
> if (!ctx->infra_base)
> return -EINVAL;
>
> + if (of_property_read_u32(node, "vio_idx_num", &ctx->vio_idx_num))
> + return -EINVAL;
> +
...only read the property if vio_idx_num == 0.
What do you think?
Regards,
Matthias
> devapc_irq = irq_of_parse_and_map(node, 0);
> if (!devapc_irq)
> return -EINVAL;
>
Regarding the commit subject:
"soc: mediatek: devapc: rename variable for new IC support"
maybe something like:
"soc: mediatek: devapc: rename register variable infra_base"
Other then that looks good to me.
On 01/04/2021 08:38, Nina Wu wrote:
> From: Nina Wu <[email protected]>
>
> For new ICs, there are multiple devapc HWs for different subsys.
> For example, there is devapc respectively for infra, peri, peri2, etc.
> So we rename the variable 'infra_base' to 'base' for code readability.
>
> Signed-off-by: Nina Wu <[email protected]>
> ---
> drivers/soc/mediatek/mtk-devapc.c | 24 ++++++++++++------------
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c
> index 68c3e35..bcf6e3c 100644
> --- a/drivers/soc/mediatek/mtk-devapc.c
> +++ b/drivers/soc/mediatek/mtk-devapc.c
> @@ -45,7 +45,7 @@ struct mtk_devapc_data {
>
> struct mtk_devapc_context {
> struct device *dev;
> - void __iomem *infra_base;
> + void __iomem *base;
> u32 vio_idx_num;
> struct clk *infra_clk;
> const struct mtk_devapc_data *data;
> @@ -56,7 +56,7 @@ static void clear_vio_status(struct mtk_devapc_context *ctx)
> void __iomem *reg;
> int i;
>
> - reg = ctx->infra_base + ctx->data->vio_sta_offset;
> + reg = ctx->base + ctx->data->vio_sta_offset;
>
> for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num - 1); i++)
> writel(GENMASK(31, 0), reg + 4 * i);
> @@ -71,7 +71,7 @@ static void mask_module_irq(struct mtk_devapc_context *ctx, bool mask)
> u32 val;
> int i;
>
> - reg = ctx->infra_base + ctx->data->vio_mask_offset;
> + reg = ctx->base + ctx->data->vio_mask_offset;
>
> if (mask)
> val = GENMASK(31, 0);
> @@ -113,11 +113,11 @@ static int devapc_sync_vio_dbg(struct mtk_devapc_context *ctx)
> int ret;
> u32 val;
>
> - pd_vio_shift_sta_reg = ctx->infra_base +
> + pd_vio_shift_sta_reg = ctx->base +
> ctx->data->vio_shift_sta_offset;
> - pd_vio_shift_sel_reg = ctx->infra_base +
> + pd_vio_shift_sel_reg = ctx->base +
> ctx->data->vio_shift_sel_offset;
> - pd_vio_shift_con_reg = ctx->infra_base +
> + pd_vio_shift_con_reg = ctx->base +
> ctx->data->vio_shift_con_offset;
>
> /* Find the minimum shift group which has violation */
> @@ -159,8 +159,8 @@ static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx)
> void __iomem *vio_dbg0_reg;
> void __iomem *vio_dbg1_reg;
>
> - vio_dbg0_reg = ctx->infra_base + ctx->data->vio_dbg0_offset;
> - vio_dbg1_reg = ctx->infra_base + ctx->data->vio_dbg1_offset;
> + vio_dbg0_reg = ctx->base + ctx->data->vio_dbg0_offset;
> + vio_dbg1_reg = ctx->base + ctx->data->vio_dbg1_offset;
>
> vio_dbgs.vio_dbg0 = readl(vio_dbg0_reg);
> vio_dbgs.vio_dbg1 = readl(vio_dbg1_reg);
> @@ -198,7 +198,7 @@ static irqreturn_t devapc_violation_irq(int irq_number, void *data)
> */
> static void start_devapc(struct mtk_devapc_context *ctx)
> {
> - writel(BIT(31), ctx->infra_base + ctx->data->apc_con_offset);
> + writel(BIT(31), ctx->base + ctx->data->apc_con_offset);
>
> mask_module_irq(ctx, false);
> }
> @@ -210,7 +210,7 @@ static void stop_devapc(struct mtk_devapc_context *ctx)
> {
> mask_module_irq(ctx, true);
>
> - writel(BIT(2), ctx->infra_base + ctx->data->apc_con_offset);
> + writel(BIT(2), ctx->base + ctx->data->apc_con_offset);
> }
>
> static const struct mtk_devapc_data devapc_mt6779 = {
> @@ -249,8 +249,8 @@ static int mtk_devapc_probe(struct platform_device *pdev)
> ctx->data = of_device_get_match_data(&pdev->dev);
> ctx->dev = &pdev->dev;
>
> - ctx->infra_base = of_iomap(node, 0);
> - if (!ctx->infra_base)
> + ctx->base = of_iomap(node, 0);
> + if (!ctx->base)
> return -EINVAL;
>
> if (of_property_read_u32(node, "vio_idx_num", &ctx->vio_idx_num))
>
On 01/04/2021 08:38, Nina Wu wrote:
> From: Nina Wu <[email protected]>
>
> There are 3 debug info registers in new ICs while in legacy ones,
> we have only 2. When dumping the debug info, we need to check first
> if the 3rd debug register exists and then we can konw how to decipher
> the debug info.
>
> Signed-off-by: Nina Wu <[email protected]>
> ---
> drivers/soc/mediatek/mtk-devapc.c | 31 +++++++++++++++++++++++++++++--
> 1 file changed, 29 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c
> index bcf6e3c..af55c01 100644
> --- a/drivers/soc/mediatek/mtk-devapc.c
> +++ b/drivers/soc/mediatek/mtk-devapc.c
> @@ -26,9 +26,19 @@ struct mtk_devapc_vio_dbgs {
> u32 addr_h:4;
> u32 resv:4;
> } dbg0_bits;
> +
> + /* Not used, reference only */
> + struct {
> + u32 dmnid:6;
> + u32 vio_w:1;
> + u32 vio_r:1;
> + u32 addr_h:4;
> + u32 resv:20;
> + } dbg0_bits_ver2;
> };
>
> u32 vio_dbg1;
> + u32 vio_dbg2;
> };
>
> struct mtk_devapc_data {
> @@ -37,6 +47,7 @@ struct mtk_devapc_data {
> u32 vio_sta_offset;
> u32 vio_dbg0_offset;
> u32 vio_dbg1_offset;
> + u32 vio_dbg2_offset;
> u32 apc_con_offset;
> u32 vio_shift_sta_offset;
> u32 vio_shift_sel_offset;
> @@ -158,12 +169,29 @@ static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx)
> struct mtk_devapc_vio_dbgs vio_dbgs;
> void __iomem *vio_dbg0_reg;
> void __iomem *vio_dbg1_reg;
> + void __iomem *vio_dbg2_reg;
> + u32 vio_addr, bus_id;
>
> vio_dbg0_reg = ctx->base + ctx->data->vio_dbg0_offset;
> vio_dbg1_reg = ctx->base + ctx->data->vio_dbg1_offset;
> + vio_dbg2_reg = ctx->base + ctx->data->vio_dbg2_offset;
We should read this only if we have version2 of the devapc.
>
> vio_dbgs.vio_dbg0 = readl(vio_dbg0_reg);
> vio_dbgs.vio_dbg1 = readl(vio_dbg1_reg);
> + vio_dbgs.vio_dbg2 = readl(vio_dbg2_reg);
> +
> + if (!ctx->data->vio_dbg2_offset) {
I think we should add a version field to mtk_devapc_data to distinguish the two
of them.
> + /* arch version 1 */
> + bus_id = vio_dbgs.dbg0_bits.mstid;
> + vio_addr = vio_dbgs.vio_dbg1;
> + } else {
> + /* arch version 2 */
> + bus_id = vio_dbgs.vio_dbg1;
> + vio_addr = vio_dbgs.vio_dbg2;
> +
> + /* To align with the bit definition of arch_ver 1 */
> + vio_dbgs.vio_dbg0 = (vio_dbgs.vio_dbg0 << 16);
That's magic, better add another variable domain_id and do here:
domain_id = vio_dgbs.dbg0_bits_ver2.dmnid;
> + }
>
> /* Print violation information */
> if (vio_dbgs.dbg0_bits.vio_w)
> @@ -172,8 +200,7 @@ static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx)
> dev_info(ctx->dev, "Read Violation\n");
>
> dev_info(ctx->dev, "Bus ID:0x%x, Dom ID:0x%x, Vio Addr:0x%x\n",
> - vio_dbgs.dbg0_bits.mstid, vio_dbgs.dbg0_bits.dmnid,
> - vio_dbgs.vio_dbg1);
> + bus_id, vio_dbgs.dbg0_bits.dmnid, vio_addr);
> }
>
> /*
>
On 01/04/2021 08:38, Nina Wu wrote:
> From: Nina Wu <[email protected]>
>
> Add compatible to support mt8192.
>
> Signed-off-by: Nina Wu <[email protected]>
> ---
Looks good, I'd like to see DTS for this as well, although I understand it
depends on the clock patch series. Please note so in either below the '---' or
in a cover letter.
Regards,
Matthias
> drivers/soc/mediatek/mtk-devapc.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c
> index af55c01..a5c15b5 100644
> --- a/drivers/soc/mediatek/mtk-devapc.c
> +++ b/drivers/soc/mediatek/mtk-devapc.c
> @@ -251,11 +251,26 @@ static const struct mtk_devapc_data devapc_mt6779 = {
> .vio_shift_con_offset = 0xF20,
> };
>
> +static const struct mtk_devapc_data devapc_mt8192 = {
> + .vio_mask_offset = 0x0,
> + .vio_sta_offset = 0x400,
> + .vio_dbg0_offset = 0x900,
> + .vio_dbg1_offset = 0x904,
> + .vio_dbg2_offset = 0x908,
> + .apc_con_offset = 0xF00,
> + .vio_shift_sta_offset = 0xF20,
> + .vio_shift_sel_offset = 0xF30,
> + .vio_shift_con_offset = 0xF10,
> +};
> +
> static const struct of_device_id mtk_devapc_dt_match[] = {
> {
> .compatible = "mediatek,mt6779-devapc",
> .data = &devapc_mt6779,
> }, {
> + .compatible = "mediatek,mt8192-devapc",
> + .data = &devapc_mt8192,
> + }, {
> },
> };
>
>
Hi, Matthias
On Tue, 2021-04-06 at 15:41 +0200, Matthias Brugger wrote:
>
> On 01/04/2021 08:38, Nina Wu wrote:
> > From: Nina Wu <[email protected]>
> >
> > For new ICs, there are multiple devapc HWs for different subsys.
> > The number of devices controlled by each devapc (i.e. 'vio_idx_num'
> > in the code) varies.
> > We move this info from compatible data to DT so that we do not need
> > to add n compatible for a certain IC which has n devapc HWs with
> > different 'vio_idx_num', respectively.
> >
> > Signed-off-by: Nina Wu <[email protected]>
> > ---
> > drivers/soc/mediatek/mtk-devapc.c | 18 +++++++++---------
> > 1 file changed, 9 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c
> > index f1cea04..a0f6fbd 100644
> > --- a/drivers/soc/mediatek/mtk-devapc.c
> > +++ b/drivers/soc/mediatek/mtk-devapc.c
> > @@ -32,9 +32,6 @@ struct mtk_devapc_vio_dbgs {
> > };
> >
> > struct mtk_devapc_data {
> > - /* numbers of violation index */
> > - u32 vio_idx_num;
> > -
> > /* reg offset */
> > u32 vio_mask_offset;
> > u32 vio_sta_offset;
> > @@ -49,6 +46,7 @@ struct mtk_devapc_data {
> > struct mtk_devapc_context {
> > struct device *dev;
> > void __iomem *infra_base;
> > + u32 vio_idx_num;
>
> We should try to stay backwards compatible (newer kernel with older DTS). I
> think we don't need to move vio_idx_num to mtk_devapc_context. Just don't
> declare it in the per SoC match data. More details see below...
>
> > struct clk *infra_clk;
> > const struct mtk_devapc_data *data;
> > };
> > @@ -60,10 +58,10 @@ static void clear_vio_status(struct mtk_devapc_context *ctx)
> >
> > reg = ctx->infra_base + ctx->data->vio_sta_offset;
> >
> > - for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++)
> > + for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num - 1); i++)
> > writel(GENMASK(31, 0), reg + 4 * i);
> >
> > - writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, 0),
> > + writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num - 1), 0),
> > reg + 4 * i);
> > }
> >
> > @@ -80,15 +78,15 @@ static void mask_module_irq(struct mtk_devapc_context *ctx, bool mask)
> > else
> > val = 0;
> >
> > - for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++)
> > + for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num - 1); i++)
> > writel(val, reg + 4 * i);
> >
> > val = readl(reg + 4 * i);
> > if (mask)
> > - val |= GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1,
> > + val |= GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num - 1),
> > 0);
> > else
> > - val &= ~GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1,
> > + val &= ~GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num - 1),
> > 0);
> >
> > writel(val, reg + 4 * i);
> > @@ -216,7 +214,6 @@ static void stop_devapc(struct mtk_devapc_context *ctx)
> > }
> >
> > static const struct mtk_devapc_data devapc_mt6779 = {
> > - .vio_idx_num = 511,
> > .vio_mask_offset = 0x0,
> > .vio_sta_offset = 0x400,
> > .vio_dbg0_offset = 0x900,
> > @@ -256,6 +253,9 @@ static int mtk_devapc_probe(struct platform_device *pdev)
> > if (!ctx->infra_base)
> > return -EINVAL;
> >
> > + if (of_property_read_u32(node, "vio_idx_num", &ctx->vio_idx_num))
> > + return -EINVAL;
> > +
>
> ...only read the property if vio_idx_num == 0.
> What do you think?
>
> Regards,
> Matthias
>
Good idea. I will fix it in the next version.
Thanks
> > devapc_irq = irq_of_parse_and_map(node, 0);
> > if (!devapc_irq)
> > return -EINVAL;
> >
Hi, Matthias
On Tue, 2021-04-06 at 15:43 +0200, Matthias Brugger wrote:
> Regarding the commit subject:
> "soc: mediatek: devapc: rename variable for new IC support"
> maybe something like:
> "soc: mediatek: devapc: rename register variable infra_base"
>
> Other then that looks good to me.
>
OK. I will fix it in the next version.
Thanks
> On 01/04/2021 08:38, Nina Wu wrote:
> > From: Nina Wu <[email protected]>
> >
> > For new ICs, there are multiple devapc HWs for different subsys.
> > For example, there is devapc respectively for infra, peri, peri2, etc.
> > So we rename the variable 'infra_base' to 'base' for code readability.
> >
> > Signed-off-by: Nina Wu <[email protected]>
> > ---
> > drivers/soc/mediatek/mtk-devapc.c | 24 ++++++++++++------------
> > 1 file changed, 12 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c
> > index 68c3e35..bcf6e3c 100644
> > --- a/drivers/soc/mediatek/mtk-devapc.c
> > +++ b/drivers/soc/mediatek/mtk-devapc.c
> > @@ -45,7 +45,7 @@ struct mtk_devapc_data {
> >
> > struct mtk_devapc_context {
> > struct device *dev;
> > - void __iomem *infra_base;
> > + void __iomem *base;
> > u32 vio_idx_num;
> > struct clk *infra_clk;
> > const struct mtk_devapc_data *data;
> > @@ -56,7 +56,7 @@ static void clear_vio_status(struct mtk_devapc_context *ctx)
> > void __iomem *reg;
> > int i;
> >
> > - reg = ctx->infra_base + ctx->data->vio_sta_offset;
> > + reg = ctx->base + ctx->data->vio_sta_offset;
> >
> > for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num - 1); i++)
> > writel(GENMASK(31, 0), reg + 4 * i);
> > @@ -71,7 +71,7 @@ static void mask_module_irq(struct mtk_devapc_context *ctx, bool mask)
> > u32 val;
> > int i;
> >
> > - reg = ctx->infra_base + ctx->data->vio_mask_offset;
> > + reg = ctx->base + ctx->data->vio_mask_offset;
> >
> > if (mask)
> > val = GENMASK(31, 0);
> > @@ -113,11 +113,11 @@ static int devapc_sync_vio_dbg(struct mtk_devapc_context *ctx)
> > int ret;
> > u32 val;
> >
> > - pd_vio_shift_sta_reg = ctx->infra_base +
> > + pd_vio_shift_sta_reg = ctx->base +
> > ctx->data->vio_shift_sta_offset;
> > - pd_vio_shift_sel_reg = ctx->infra_base +
> > + pd_vio_shift_sel_reg = ctx->base +
> > ctx->data->vio_shift_sel_offset;
> > - pd_vio_shift_con_reg = ctx->infra_base +
> > + pd_vio_shift_con_reg = ctx->base +
> > ctx->data->vio_shift_con_offset;
> >
> > /* Find the minimum shift group which has violation */
> > @@ -159,8 +159,8 @@ static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx)
> > void __iomem *vio_dbg0_reg;
> > void __iomem *vio_dbg1_reg;
> >
> > - vio_dbg0_reg = ctx->infra_base + ctx->data->vio_dbg0_offset;
> > - vio_dbg1_reg = ctx->infra_base + ctx->data->vio_dbg1_offset;
> > + vio_dbg0_reg = ctx->base + ctx->data->vio_dbg0_offset;
> > + vio_dbg1_reg = ctx->base + ctx->data->vio_dbg1_offset;
> >
> > vio_dbgs.vio_dbg0 = readl(vio_dbg0_reg);
> > vio_dbgs.vio_dbg1 = readl(vio_dbg1_reg);
> > @@ -198,7 +198,7 @@ static irqreturn_t devapc_violation_irq(int irq_number, void *data)
> > */
> > static void start_devapc(struct mtk_devapc_context *ctx)
> > {
> > - writel(BIT(31), ctx->infra_base + ctx->data->apc_con_offset);
> > + writel(BIT(31), ctx->base + ctx->data->apc_con_offset);
> >
> > mask_module_irq(ctx, false);
> > }
> > @@ -210,7 +210,7 @@ static void stop_devapc(struct mtk_devapc_context *ctx)
> > {
> > mask_module_irq(ctx, true);
> >
> > - writel(BIT(2), ctx->infra_base + ctx->data->apc_con_offset);
> > + writel(BIT(2), ctx->base + ctx->data->apc_con_offset);
> > }
> >
> > static const struct mtk_devapc_data devapc_mt6779 = {
> > @@ -249,8 +249,8 @@ static int mtk_devapc_probe(struct platform_device *pdev)
> > ctx->data = of_device_get_match_data(&pdev->dev);
> > ctx->dev = &pdev->dev;
> >
> > - ctx->infra_base = of_iomap(node, 0);
> > - if (!ctx->infra_base)
> > + ctx->base = of_iomap(node, 0);
> > + if (!ctx->base)
> > return -EINVAL;
> >
> > if (of_property_read_u32(node, "vio_idx_num", &ctx->vio_idx_num))
> >
Hi, Matthias
On Tue, 2021-04-06 at 15:53 +0200, Matthias Brugger wrote:
>
> On 01/04/2021 08:38, Nina Wu wrote:
> > From: Nina Wu <[email protected]>
> >
> > There are 3 debug info registers in new ICs while in legacy ones,
> > we have only 2. When dumping the debug info, we need to check first
> > if the 3rd debug register exists and then we can konw how to decipher
> > the debug info.
> >
> > Signed-off-by: Nina Wu <[email protected]>
> > ---
> > drivers/soc/mediatek/mtk-devapc.c | 31 +++++++++++++++++++++++++++++--
> > 1 file changed, 29 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c
> > index bcf6e3c..af55c01 100644
> > --- a/drivers/soc/mediatek/mtk-devapc.c
> > +++ b/drivers/soc/mediatek/mtk-devapc.c
> > @@ -26,9 +26,19 @@ struct mtk_devapc_vio_dbgs {
> > u32 addr_h:4;
> > u32 resv:4;
> > } dbg0_bits;
> > +
> > + /* Not used, reference only */
> > + struct {
> > + u32 dmnid:6;
> > + u32 vio_w:1;
> > + u32 vio_r:1;
> > + u32 addr_h:4;
> > + u32 resv:20;
> > + } dbg0_bits_ver2;
> > };
> >
> > u32 vio_dbg1;
> > + u32 vio_dbg2;
> > };
> >
> > struct mtk_devapc_data {
> > @@ -37,6 +47,7 @@ struct mtk_devapc_data {
> > u32 vio_sta_offset;
> > u32 vio_dbg0_offset;
> > u32 vio_dbg1_offset;
> > + u32 vio_dbg2_offset;
> > u32 apc_con_offset;
> > u32 vio_shift_sta_offset;
> > u32 vio_shift_sel_offset;
> > @@ -158,12 +169,29 @@ static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx)
> > struct mtk_devapc_vio_dbgs vio_dbgs;
> > void __iomem *vio_dbg0_reg;
> > void __iomem *vio_dbg1_reg;
> > + void __iomem *vio_dbg2_reg;
> > + u32 vio_addr, bus_id;
> >
> > vio_dbg0_reg = ctx->base + ctx->data->vio_dbg0_offset;
> > vio_dbg1_reg = ctx->base + ctx->data->vio_dbg1_offset;
> > + vio_dbg2_reg = ctx->base + ctx->data->vio_dbg2_offset;
>
> We should read this only if we have version2 of the devapc.
>
You're right.
It is not good to read vio_dbg2_reg in version one. Even though we will
only get the value from offset 0 (which is not expected) instead of
doing any real harm. (like causing bus hang)
> >
> > vio_dbgs.vio_dbg0 = readl(vio_dbg0_reg);
> > vio_dbgs.vio_dbg1 = readl(vio_dbg1_reg);
> > + vio_dbgs.vio_dbg2 = readl(vio_dbg2_reg);
> > +
> > + if (!ctx->data->vio_dbg2_offset) {
>
> I think we should add a version field to mtk_devapc_data to distinguish the two
> of them.
OK.
I will try to add this field in the next version
>
> > + /* arch version 1 */
> > + bus_id = vio_dbgs.dbg0_bits.mstid;
> > + vio_addr = vio_dbgs.vio_dbg1;
> > + } else {
> > + /* arch version 2 */
> > + bus_id = vio_dbgs.vio_dbg1;
> > + vio_addr = vio_dbgs.vio_dbg2;
> > +
> > + /* To align with the bit definition of arch_ver 1 */
> > + vio_dbgs.vio_dbg0 = (vio_dbgs.vio_dbg0 << 16);
>
> That's magic, better add another variable domain_id and do here:
> domain_id = vio_dgbs.dbg0_bits_ver2.dmnid;
>
OK.
I will fix it up in the next version.
Thanks
> > + }
> >
> > /* Print violation information */
> > if (vio_dbgs.dbg0_bits.vio_w)
> > @@ -172,8 +200,7 @@ static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx)
> > dev_info(ctx->dev, "Read Violation\n");
> >
> > dev_info(ctx->dev, "Bus ID:0x%x, Dom ID:0x%x, Vio Addr:0x%x\n",
> > - vio_dbgs.dbg0_bits.mstid, vio_dbgs.dbg0_bits.dmnid,
> > - vio_dbgs.vio_dbg1);
> > + bus_id, vio_dbgs.dbg0_bits.dmnid, vio_addr);
> > }
> >
> > /*
> >
Hi, Matthias
On Tue, 2021-04-06 at 15:55 +0200, Matthias Brugger wrote:
>
> On 01/04/2021 08:38, Nina Wu wrote:
> > From: Nina Wu <[email protected]>
> >
> > Add compatible to support mt8192.
> >
> > Signed-off-by: Nina Wu <[email protected]>
> > ---
>
>
> Looks good, I'd like to see DTS for this as well, although I understand it
> depends on the clock patch series. Please note so in either below the '---' or
> in a cover letter.
>
> Regards,
> Matthias
>
I will add devapc nodes in DTS in the next version.
Thanks
>
> > drivers/soc/mediatek/mtk-devapc.c | 15 +++++++++++++++
> > 1 file changed, 15 insertions(+)
> >
> > diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c
> > index af55c01..a5c15b5 100644
> > --- a/drivers/soc/mediatek/mtk-devapc.c
> > +++ b/drivers/soc/mediatek/mtk-devapc.c
> > @@ -251,11 +251,26 @@ static const struct mtk_devapc_data devapc_mt6779 = {
> > .vio_shift_con_offset = 0xF20,
> > };
> >
> > +static const struct mtk_devapc_data devapc_mt8192 = {
> > + .vio_mask_offset = 0x0,
> > + .vio_sta_offset = 0x400,
> > + .vio_dbg0_offset = 0x900,
> > + .vio_dbg1_offset = 0x904,
> > + .vio_dbg2_offset = 0x908,
> > + .apc_con_offset = 0xF00,
> > + .vio_shift_sta_offset = 0xF20,
> > + .vio_shift_sel_offset = 0xF30,
> > + .vio_shift_con_offset = 0xF10,
> > +};
> > +
> > static const struct of_device_id mtk_devapc_dt_match[] = {
> > {
> > .compatible = "mediatek,mt6779-devapc",
> > .data = &devapc_mt6779,
> > }, {
> > + .compatible = "mediatek,mt8192-devapc",
> > + .data = &devapc_mt8192,
> > + }, {
> > },
> > };
> >
> >
On Thu, Apr 01, 2021 at 02:38:02PM +0800, Nina Wu wrote:
> From: Nina Wu <[email protected]>
Every change is an 'update'. Perhaps mention mt8192 in the subject.
>
> To support newer hardware architecture of devapc,
> update device tree bindings.
>
> Signed-off-by: Nina Wu <[email protected]>
> ---
> Documentation/devicetree/bindings/soc/mediatek/devapc.yaml | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
> index 31e4d3c..42b284e 100644
> --- a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
> +++ b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
> @@ -20,11 +20,17 @@ properties:
> compatible:
> enum:
> - mediatek,mt6779-devapc
> + - mediatek,mt8192-devapc
>
> reg:
> description: The base address of devapc register bank
> maxItems: 1
>
> + vio-idx-num:
Needs a vendor prefix.
> + description: The number of the devices controlled by devapc
> + $ref: /schemas/types.yaml#/definitions/uint32
> + maxItems: 1
> +
> interrupts:
> description: A single interrupt specifier
> maxItems: 1
> @@ -40,6 +46,7 @@ properties:
> required:
> - compatible
> - reg
> + - vio-idx-num
> - interrupts
> - clocks
> - clock-names
> @@ -54,6 +61,7 @@ examples:
> devapc: devapc@10207000 {
> compatible = "mediatek,mt6779-devapc";
> reg = <0x10207000 0x1000>;
> + vio-idx-num = <511>;
> interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
> clocks = <&infracfg_ao CLK_INFRA_DEVICE_APC>;
> clock-names = "devapc-infra-clock";
> --
> 2.6.4
>
Hi, Rob
On Thu, 2021-04-08 at 15:43 -0500, Rob Herring wrote:
> On Thu, Apr 01, 2021 at 02:38:02PM +0800, Nina Wu wrote:
> > From: Nina Wu <[email protected]>
>
> Every change is an 'update'. Perhaps mention mt8192 in the subject.
>
OK.
I will try to make it clear in the next version.
> >
> > To support newer hardware architecture of devapc,
> > update device tree bindings.
> >
> > Signed-off-by: Nina Wu <[email protected]>
> > ---
> > Documentation/devicetree/bindings/soc/mediatek/devapc.yaml | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
> > index 31e4d3c..42b284e 100644
> > --- a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
> > +++ b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
> > @@ -20,11 +20,17 @@ properties:
> > compatible:
> > enum:
> > - mediatek,mt6779-devapc
> > + - mediatek,mt8192-devapc
> >
> > reg:
> > description: The base address of devapc register bank
> > maxItems: 1
> >
> > + vio-idx-num:
>
> Needs a vendor prefix.
OK.
I will fix it in the next version.
Thanks.
>
> > + description: The number of the devices controlled by devapc
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + maxItems: 1
> > +
> > interrupts:
> > description: A single interrupt specifier
> > maxItems: 1
> > @@ -40,6 +46,7 @@ properties:
> > required:
> > - compatible
> > - reg
> > + - vio-idx-num
> > - interrupts
> > - clocks
> > - clock-names
> > @@ -54,6 +61,7 @@ examples:
> > devapc: devapc@10207000 {
> > compatible = "mediatek,mt6779-devapc";
> > reg = <0x10207000 0x1000>;
> > + vio-idx-num = <511>;
> > interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
> > clocks = <&infracfg_ao CLK_INFRA_DEVICE_APC>;
> > clock-names = "devapc-infra-clock";
> > --
> > 2.6.4
> >