From: Nina Wu <[email protected]>
For new ICs, there are multiple devapc HWs for different subsys.
We add a field 'vio-idx-num' in DT to indicate the number of
devices controlled by each devapc.
To be backward compatible with old ICs which have only one devapc
HW, this field is not required. The 'vio-idx-num' info will be set
in compatible data instead.
Signed-off-by: Nina Wu <[email protected]>
---
Documentation/devicetree/bindings/soc/mediatek/devapc.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
index 31e4d3c..909e524 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
@@ -20,11 +20,17 @@ properties:
compatible:
enum:
- mediatek,mt6779-devapc
+ - mediatek,mt8192-devapc
reg:
description: The base address of devapc register bank
maxItems: 1
+ mediatek,vio-idx-num:
+ description: The number of the devices controlled by devapc
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+
interrupts:
description: A single interrupt specifier
maxItems: 1
--
2.6.4
From: Nina Wu <[email protected]>
Add compatible to support mt8192.
Signed-off-by: Nina Wu <[email protected]>
---
drivers/soc/mediatek/mtk-devapc.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c
index bdc8fe9..84dd6a2 100644
--- a/drivers/soc/mediatek/mtk-devapc.c
+++ b/drivers/soc/mediatek/mtk-devapc.c
@@ -265,11 +265,27 @@ static const struct mtk_devapc_data devapc_mt6779 = {
.vio_shift_con_offset = 0xF20,
};
+static const struct mtk_devapc_data devapc_mt8192 = {
+ .version = 2,
+ .vio_mask_offset = 0x0,
+ .vio_sta_offset = 0x400,
+ .vio_dbg0_offset = 0x900,
+ .vio_dbg1_offset = 0x904,
+ .vio_dbg2_offset = 0x908,
+ .apc_con_offset = 0xF00,
+ .vio_shift_sta_offset = 0xF20,
+ .vio_shift_sel_offset = 0xF30,
+ .vio_shift_con_offset = 0xF10,
+};
+
static const struct of_device_id mtk_devapc_dt_match[] = {
{
.compatible = "mediatek,mt6779-devapc",
.data = &devapc_mt6779,
}, {
+ .compatible = "mediatek,mt8192-devapc",
+ .data = &devapc_mt8192,
+ }, {
},
};
--
2.6.4
From: Nina Wu <[email protected]>
For new ICs, there are multiple devapc HWs for different subsys.
They all share the same IRQ number.
Signed-off-by: Nina Wu <[email protected]>
---
drivers/soc/mediatek/mtk-devapc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c
index 71643d1..6d58a75 100644
--- a/drivers/soc/mediatek/mtk-devapc.c
+++ b/drivers/soc/mediatek/mtk-devapc.c
@@ -281,7 +281,7 @@ static int mtk_devapc_probe(struct platform_device *pdev)
return -EINVAL;
ret = devm_request_irq(&pdev->dev, devapc_irq, devapc_violation_irq,
- IRQF_TRIGGER_NONE, "devapc", ctx);
+ IRQF_TRIGGER_NONE | IRQF_SHARED, "devapc", ctx);
if (ret) {
clk_disable_unprepare(ctx->infra_clk);
return ret;
--
2.6.4
From: Nina Wu <[email protected]>
For new ICs, there are multiple devapc HWs for different subsys.
For example, there is devapc respectively for infra, peri, peri2, etc.
So we rename the variable 'infra_base' to 'base' for code readability.
Signed-off-by: Nina Wu <[email protected]>
---
drivers/soc/mediatek/mtk-devapc.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c
index 6d58a75..f5d63c5 100644
--- a/drivers/soc/mediatek/mtk-devapc.c
+++ b/drivers/soc/mediatek/mtk-devapc.c
@@ -48,7 +48,7 @@ struct mtk_devapc_data {
struct mtk_devapc_context {
struct device *dev;
- void __iomem *infra_base;
+ void __iomem *base;
struct clk *infra_clk;
const struct mtk_devapc_data *data;
@@ -61,7 +61,7 @@ static void clear_vio_status(struct mtk_devapc_context *ctx)
void __iomem *reg;
int i;
- reg = ctx->infra_base + ctx->data->vio_sta_offset;
+ reg = ctx->base + ctx->data->vio_sta_offset;
for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num) - 1; i++)
writel(GENMASK(31, 0), reg + 4 * i);
@@ -76,7 +76,7 @@ static void mask_module_irq(struct mtk_devapc_context *ctx, bool mask)
u32 val;
int i;
- reg = ctx->infra_base + ctx->data->vio_mask_offset;
+ reg = ctx->base + ctx->data->vio_mask_offset;
if (mask)
val = GENMASK(31, 0);
@@ -118,11 +118,11 @@ static int devapc_sync_vio_dbg(struct mtk_devapc_context *ctx)
int ret;
u32 val;
- pd_vio_shift_sta_reg = ctx->infra_base +
+ pd_vio_shift_sta_reg = ctx->base +
ctx->data->vio_shift_sta_offset;
- pd_vio_shift_sel_reg = ctx->infra_base +
+ pd_vio_shift_sel_reg = ctx->base +
ctx->data->vio_shift_sel_offset;
- pd_vio_shift_con_reg = ctx->infra_base +
+ pd_vio_shift_con_reg = ctx->base +
ctx->data->vio_shift_con_offset;
/* Find the minimum shift group which has violation */
@@ -164,8 +164,8 @@ static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx)
void __iomem *vio_dbg0_reg;
void __iomem *vio_dbg1_reg;
- vio_dbg0_reg = ctx->infra_base + ctx->data->vio_dbg0_offset;
- vio_dbg1_reg = ctx->infra_base + ctx->data->vio_dbg1_offset;
+ vio_dbg0_reg = ctx->base + ctx->data->vio_dbg0_offset;
+ vio_dbg1_reg = ctx->base + ctx->data->vio_dbg1_offset;
vio_dbgs.vio_dbg0 = readl(vio_dbg0_reg);
vio_dbgs.vio_dbg1 = readl(vio_dbg1_reg);
@@ -203,7 +203,7 @@ static irqreturn_t devapc_violation_irq(int irq_number, void *data)
*/
static void start_devapc(struct mtk_devapc_context *ctx)
{
- writel(BIT(31), ctx->infra_base + ctx->data->apc_con_offset);
+ writel(BIT(31), ctx->base + ctx->data->apc_con_offset);
mask_module_irq(ctx, false);
}
@@ -215,7 +215,7 @@ static void stop_devapc(struct mtk_devapc_context *ctx)
{
mask_module_irq(ctx, true);
- writel(BIT(2), ctx->infra_base + ctx->data->apc_con_offset);
+ writel(BIT(2), ctx->base + ctx->data->apc_con_offset);
}
static const struct mtk_devapc_data devapc_mt6779 = {
@@ -255,8 +255,8 @@ static int mtk_devapc_probe(struct platform_device *pdev)
ctx->data = of_device_get_match_data(&pdev->dev);
ctx->dev = &pdev->dev;
- ctx->infra_base = of_iomap(node, 0);
- if (!ctx->infra_base)
+ ctx->base = of_iomap(node, 0);
+ if (!ctx->base)
return -EINVAL;
/* Set vio_idx_num to default value.
--
2.6.4
From: Nina Wu <[email protected]>
There are 3 debug info registers in new ICs while in legacy ones,
we have only 2. We add a 'version' field in compatible data to
decide how we extract the debug info.
Signed-off-by: Nina Wu <[email protected]>
---
drivers/soc/mediatek/mtk-devapc.c | 43 +++++++++++++++++++++++++++++++++++----
1 file changed, 39 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c
index f5d63c5..bdc8fe9 100644
--- a/drivers/soc/mediatek/mtk-devapc.c
+++ b/drivers/soc/mediatek/mtk-devapc.c
@@ -26,12 +26,24 @@ struct mtk_devapc_vio_dbgs {
u32 addr_h:4;
u32 resv:4;
} dbg0_bits;
+
+ struct {
+ u32 dmnid:6;
+ u32 vio_w:1;
+ u32 vio_r:1;
+ u32 addr_h:4;
+ u32 resv:20;
+ } dbg0_bits_ver2;
};
u32 vio_dbg1;
+ u32 vio_dbg2;
};
struct mtk_devapc_data {
+ /* architecture version */
+ u32 version;
+
/* default numbers of violation index */
u32 vio_idx_num;
@@ -40,6 +52,7 @@ struct mtk_devapc_data {
u32 vio_sta_offset;
u32 vio_dbg0_offset;
u32 vio_dbg1_offset;
+ u32 vio_dbg2_offset;
u32 apc_con_offset;
u32 vio_shift_sta_offset;
u32 vio_shift_sel_offset;
@@ -163,22 +176,43 @@ static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx)
struct mtk_devapc_vio_dbgs vio_dbgs;
void __iomem *vio_dbg0_reg;
void __iomem *vio_dbg1_reg;
+ void __iomem *vio_dbg2_reg;
+ u32 vio_addr, bus_id, domain_id;
+ u32 vio_w, vio_r;
vio_dbg0_reg = ctx->base + ctx->data->vio_dbg0_offset;
vio_dbg1_reg = ctx->base + ctx->data->vio_dbg1_offset;
+ vio_dbg2_reg = ctx->base + ctx->data->vio_dbg2_offset;
vio_dbgs.vio_dbg0 = readl(vio_dbg0_reg);
vio_dbgs.vio_dbg1 = readl(vio_dbg1_reg);
+ if (ctx->data->version == 2U)
+ vio_dbgs.vio_dbg2 = readl(vio_dbg2_reg);
+
+ if (ctx->data->version == 1U) {
+ /* arch version 1 */
+ bus_id = vio_dbgs.dbg0_bits.mstid;
+ vio_addr = vio_dbgs.vio_dbg1;
+ domain_id = vio_dbgs.dbg0_bits.dmnid;
+ vio_w = vio_dbgs.dbg0_bits.vio_w;
+ vio_r = vio_dbgs.dbg0_bits.vio_r;
+ } else {
+ /* arch version 2 */
+ bus_id = vio_dbgs.vio_dbg1;
+ vio_addr = vio_dbgs.vio_dbg2;
+ domain_id = vio_dbgs.dbg0_bits_ver2.dmnid;
+ vio_w = vio_dbgs.dbg0_bits_ver2.vio_w;
+ vio_r = vio_dbgs.dbg0_bits_ver2.vio_r;
+ }
/* Print violation information */
- if (vio_dbgs.dbg0_bits.vio_w)
+ if (vio_w)
dev_info(ctx->dev, "Write Violation\n");
- else if (vio_dbgs.dbg0_bits.vio_r)
+ else if (vio_r)
dev_info(ctx->dev, "Read Violation\n");
dev_info(ctx->dev, "Bus ID:0x%x, Dom ID:0x%x, Vio Addr:0x%x\n",
- vio_dbgs.dbg0_bits.mstid, vio_dbgs.dbg0_bits.dmnid,
- vio_dbgs.vio_dbg1);
+ bus_id, domain_id, vio_addr);
}
/*
@@ -219,6 +253,7 @@ static void stop_devapc(struct mtk_devapc_context *ctx)
}
static const struct mtk_devapc_data devapc_mt6779 = {
+ .version = 1,
.vio_idx_num = 511,
.vio_mask_offset = 0x0,
.vio_sta_offset = 0x400,
--
2.6.4
From: Nina Wu <[email protected]>
Add devapc nodes to mt8192.
Signed-off-by: Nina Wu <[email protected]>
---
This patch depends on "Add dt-bindings of MT8192 clocks" [1]
and "Add mt8192 clock controllers" [2]
[1] https://patchwork.kernel.org/project/linux-mediatek/patch/[email protected]/
[2] https://patchwork.kernel.org/project/linux-mediatek/patch/[email protected]/
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 36 ++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index fe24cc6..4f5fb62 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -518,6 +518,33 @@
clock-names = "clk13m";
};
+ devapc_infra: devapc@10207000 {
+ compatible = "mediatek,mt8192-devapc";
+ reg = <0 0x10207000 0 0x1000>;
+ vio-idx-num = <367>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_DEVICE_APC>;
+ clock-names = "devapc-infra-clock";
+ };
+
+ devapc_peri: devapc@10274000 {
+ compatible = "mediatek,mt8192-devapc";
+ reg = <0 0x10274000 0 0x1000>;
+ vio-idx-num = <292>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_DEVICE_APC>;
+ clock-names = "devapc-infra-clock";
+ };
+
+ devapc_peri2: devapc@10275000 {
+ compatible = "mediatek,mt8192-devapc";
+ reg = <0 0x10275000 0 0x1000>;
+ vio-idx-num = <242>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_DEVICE_APC>;
+ clock-names = "devapc-infra-clock";
+ };
+
scp_adsp: syscon@10720000 {
compatible = "mediatek,mt8192-scp_adsp", "syscon";
reg = <0 0x10720000 0 0x1000>;
@@ -662,6 +689,15 @@
status = "disabled";
};
+ devapc_peri_par: devapc@11020000 {
+ compatible = "mediatek,mt8192-devapc";
+ reg = <0 0x11020000 0 0x1000>;
+ vio-idx-num = <58>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_INFRA_DEVICE_APC>;
+ clock-names = "devapc-infra-clock";
+ };
+
nor_flash: spi@11234000 {
compatible = "mediatek,mt8192-nor";
reg = <0 0x11234000 0 0xe0>;
--
2.6.4
From: Nina Wu <[email protected]>
For new ICs, there are multiple devapc HWs for different subsys.
The number of devices controlled by each devapc (i.e. 'vio_idx_num')
will be set in DT for per devapc node.
On the other hand, for old ICs which have only one devapc HW, the
'vio_idx_num' info is set in compatible data.
To be backward compatible, the 'vio_idx_num' in compatible data is set
as the default value. Only when the default value is 0 will we get the
'vio_idx_num' from DT.
Signed-off-by: Nina Wu <[email protected]>
---
drivers/soc/mediatek/mtk-devapc.c | 25 +++++++++++++++++++------
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c
index f1cea04..71643d1 100644
--- a/drivers/soc/mediatek/mtk-devapc.c
+++ b/drivers/soc/mediatek/mtk-devapc.c
@@ -32,7 +32,7 @@ struct mtk_devapc_vio_dbgs {
};
struct mtk_devapc_data {
- /* numbers of violation index */
+ /* default numbers of violation index */
u32 vio_idx_num;
/* reg offset */
@@ -51,6 +51,9 @@ struct mtk_devapc_context {
void __iomem *infra_base;
struct clk *infra_clk;
const struct mtk_devapc_data *data;
+
+ /* numbers of violation index */
+ u32 vio_idx_num;
};
static void clear_vio_status(struct mtk_devapc_context *ctx)
@@ -60,10 +63,10 @@ static void clear_vio_status(struct mtk_devapc_context *ctx)
reg = ctx->infra_base + ctx->data->vio_sta_offset;
- for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++)
+ for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num) - 1; i++)
writel(GENMASK(31, 0), reg + 4 * i);
- writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, 0),
+ writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num) - 1, 0),
reg + 4 * i);
}
@@ -80,15 +83,15 @@ static void mask_module_irq(struct mtk_devapc_context *ctx, bool mask)
else
val = 0;
- for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++)
+ for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num) - 1; i++)
writel(val, reg + 4 * i);
val = readl(reg + 4 * i);
if (mask)
- val |= GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1,
+ val |= GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num) - 1,
0);
else
- val &= ~GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1,
+ val &= ~GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num) - 1,
0);
writel(val, reg + 4 * i);
@@ -256,6 +259,16 @@ static int mtk_devapc_probe(struct platform_device *pdev)
if (!ctx->infra_base)
return -EINVAL;
+ /* Set vio_idx_num to default value.
+ * If the value is 0, get the info from DT.
+ */
+ ctx->vio_idx_num = ctx->data->vio_idx_num;
+ if (!ctx->vio_idx_num)
+ if (of_property_read_u32(node,
+ "vio-idx-num",
+ &ctx->vio_idx_num))
+ return -EINVAL;
+
devapc_irq = irq_of_parse_and_map(node, 0);
if (!devapc_irq)
return -EINVAL;
--
2.6.4
On Fri, Apr 09, 2021 at 04:19:31PM +0800, Nina Wu wrote:
> From: Nina Wu <[email protected]>
>
> For new ICs, there are multiple devapc HWs for different subsys.
> We add a field 'vio-idx-num' in DT to indicate the number of
> devices controlled by each devapc.
> To be backward compatible with old ICs which have only one devapc
> HW, this field is not required. The 'vio-idx-num' info will be set
> in compatible data instead.
>
> Signed-off-by: Nina Wu <[email protected]>
> ---
> Documentation/devicetree/bindings/soc/mediatek/devapc.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
> index 31e4d3c..909e524 100644
> --- a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
> +++ b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
> @@ -20,11 +20,17 @@ properties:
> compatible:
> enum:
> - mediatek,mt6779-devapc
> + - mediatek,mt8192-devapc
>
> reg:
> description: The base address of devapc register bank
> maxItems: 1
>
> + mediatek,vio-idx-num:
> + description: The number of the devices controlled by devapc
> + $ref: /schemas/types.yaml#/definitions/uint32
> + maxItems: 1
A uint32 is always 1 item, so drop. With that,
Reviewed-by: Rob Herring <[email protected]>
> +
> interrupts:
> description: A single interrupt specifier
> maxItems: 1
> --
> 2.6.4
>