QPIC_EBI2_ECC_BUF_CFG register got obsolete from QPIC V2.0 onwards.
Avoid writing this register if QPIC version is V2.0 or newer.
Also fixed nandc undeclared issue reported by,
Reported-by: kernel test robot <[email protected]>
Signed-off-by: Md Sadre Alam <[email protected]>
---
[V3]
* Fixed nandc undeclared issue.
drivers/mtd/nand/raw/qcom_nandc.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index a64fb6c..ee5985d 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -734,6 +734,7 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, i
{
struct nand_chip *chip = &host->chip;
u32 cmd, cfg0, cfg1, ecc_bch_cfg;
+ struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
if (read) {
if (host->use_ecc)
@@ -762,7 +763,8 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, i
nandc_set_reg(chip, NAND_DEV0_CFG0, cfg0);
nandc_set_reg(chip, NAND_DEV0_CFG1, cfg1);
nandc_set_reg(chip, NAND_DEV0_ECC_CFG, ecc_bch_cfg);
- nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
+ if (!nandc->props->qpic_v2)
+ nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
nandc_set_reg(chip, NAND_FLASH_STATUS, host->clrflashstatus);
nandc_set_reg(chip, NAND_READ_STATUS, host->clrreadstatus);
nandc_set_reg(chip, NAND_EXEC_CMD, 1);
@@ -1133,7 +1135,8 @@ static void config_nand_page_read(struct nand_chip *chip)
write_reg_dma(nandc, NAND_ADDR0, 2, 0);
write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
- write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
+ if (!nandc->props->qpic_v2)
+ write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
@@ -1191,8 +1194,9 @@ static void config_nand_page_write(struct nand_chip *chip)
write_reg_dma(nandc, NAND_ADDR0, 2, 0);
write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
- write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
- NAND_BAM_NEXT_SGL);
+ if (!nandc->props->qpic_v2)
+ write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
+ NAND_BAM_NEXT_SGL);
}
/*
@@ -1248,7 +1252,8 @@ static int nandc_param(struct qcom_nand_host *host)
| 2 << WR_RD_BSY_GAP
| 0 << WIDE_FLASH
| 1 << DEV0_CFG1_ECC_DISABLE);
- nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE);
+ if (!nandc->props->qpic_v2)
+ nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE);
/* configure CMD1 and VLD for ONFI param probing in QPIC v1 */
if (!nandc->props->qpic_v2) {
@@ -2689,7 +2694,8 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
| ecc_mode << ECC_MODE
| host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH;
- host->ecc_buf_cfg = 0x203 << NUM_STEPS;
+ if (!nandc->props->qpic_v2)
+ host->ecc_buf_cfg = 0x203 << NUM_STEPS;
host->clrflashstatus = FS_READY_BSY_N;
host->clrreadstatus = 0xc0;
--
2.7.4
Hello,
Md Sadre Alam <[email protected]> wrote on Mon, 7 Jun 2021
15:13:37 +0530:
> QPIC_EBI2_ECC_BUF_CFG register got obsolete from QPIC V2.0 onwards.
> Avoid writing this register if QPIC version is V2.0 or newer.
>
> Also fixed nandc undeclared issue reported by,
>
> Reported-by: kernel test robot <[email protected]>
This tag should only be added when you fix something that is already in
mainline. The Reported-by here points to v2, which makes no sense.
Please drop it.
> Signed-off-by: Md Sadre Alam <[email protected]>
> ---
> [V3]
> * Fixed nandc undeclared issue.
> drivers/mtd/nand/raw/qcom_nandc.c | 18 ++++++++++++------
> 1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
> index a64fb6c..ee5985d 100644
> --- a/drivers/mtd/nand/raw/qcom_nandc.c
> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
> @@ -734,6 +734,7 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, i
> {
> struct nand_chip *chip = &host->chip;
> u32 cmd, cfg0, cfg1, ecc_bch_cfg;
> + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>
> if (read) {
> if (host->use_ecc)
> @@ -762,7 +763,8 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, i
> nandc_set_reg(chip, NAND_DEV0_CFG0, cfg0);
> nandc_set_reg(chip, NAND_DEV0_CFG1, cfg1);
> nandc_set_reg(chip, NAND_DEV0_ECC_CFG, ecc_bch_cfg);
> - nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
> + if (!nandc->props->qpic_v2)
> + nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
> nandc_set_reg(chip, NAND_FLASH_STATUS, host->clrflashstatus);
> nandc_set_reg(chip, NAND_READ_STATUS, host->clrreadstatus);
> nandc_set_reg(chip, NAND_EXEC_CMD, 1);
> @@ -1133,7 +1135,8 @@ static void config_nand_page_read(struct nand_chip *chip)
>
> write_reg_dma(nandc, NAND_ADDR0, 2, 0);
> write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
> - write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
> + if (!nandc->props->qpic_v2)
> + write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
> write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
> write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
> NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
> @@ -1191,8 +1194,9 @@ static void config_nand_page_write(struct nand_chip *chip)
>
> write_reg_dma(nandc, NAND_ADDR0, 2, 0);
> write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
> - write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
> - NAND_BAM_NEXT_SGL);
> + if (!nandc->props->qpic_v2)
> + write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
> + NAND_BAM_NEXT_SGL);
> }
>
> /*
> @@ -1248,7 +1252,8 @@ static int nandc_param(struct qcom_nand_host *host)
> | 2 << WR_RD_BSY_GAP
> | 0 << WIDE_FLASH
> | 1 << DEV0_CFG1_ECC_DISABLE);
> - nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE);
> + if (!nandc->props->qpic_v2)
> + nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE);
>
> /* configure CMD1 and VLD for ONFI param probing in QPIC v1 */
> if (!nandc->props->qpic_v2) {
> @@ -2689,7 +2694,8 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
> | ecc_mode << ECC_MODE
> | host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH;
>
> - host->ecc_buf_cfg = 0x203 << NUM_STEPS;
> + if (!nandc->props->qpic_v2)
> + host->ecc_buf_cfg = 0x203 << NUM_STEPS;
>
> host->clrflashstatus = FS_READY_BSY_N;
> host->clrreadstatus = 0xc0;
Thanks,
Miquèl
On 2021-06-07 15:20, Miquel Raynal wrote:
> Hello,
>
> Md Sadre Alam <[email protected]> wrote on Mon, 7 Jun 2021
> 15:13:37 +0530:
>
>> QPIC_EBI2_ECC_BUF_CFG register got obsolete from QPIC V2.0 onwards.
>> Avoid writing this register if QPIC version is V2.0 or newer.
>>
>> Also fixed nandc undeclared issue reported by,
>>
>> Reported-by: kernel test robot <[email protected]>
>
> This tag should only be added when you fix something that is already in
> mainline. The Reported-by here points to v2, which makes no sense.
> Please drop it.
updated this V4 patch.
>
>> Signed-off-by: Md Sadre Alam <[email protected]>
>> ---
>> [V3]
>> * Fixed nandc undeclared issue.
>> drivers/mtd/nand/raw/qcom_nandc.c | 18 ++++++++++++------
>> 1 file changed, 12 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
>> b/drivers/mtd/nand/raw/qcom_nandc.c
>> index a64fb6c..ee5985d 100644
>> --- a/drivers/mtd/nand/raw/qcom_nandc.c
>> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
>> @@ -734,6 +734,7 @@ static void update_rw_regs(struct qcom_nand_host
>> *host, int num_cw, bool read, i
>> {
>> struct nand_chip *chip = &host->chip;
>> u32 cmd, cfg0, cfg1, ecc_bch_cfg;
>> + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>>
>> if (read) {
>> if (host->use_ecc)
>> @@ -762,7 +763,8 @@ static void update_rw_regs(struct qcom_nand_host
>> *host, int num_cw, bool read, i
>> nandc_set_reg(chip, NAND_DEV0_CFG0, cfg0);
>> nandc_set_reg(chip, NAND_DEV0_CFG1, cfg1);
>> nandc_set_reg(chip, NAND_DEV0_ECC_CFG, ecc_bch_cfg);
>> - nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
>> + if (!nandc->props->qpic_v2)
>> + nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
>> nandc_set_reg(chip, NAND_FLASH_STATUS, host->clrflashstatus);
>> nandc_set_reg(chip, NAND_READ_STATUS, host->clrreadstatus);
>> nandc_set_reg(chip, NAND_EXEC_CMD, 1);
>> @@ -1133,7 +1135,8 @@ static void config_nand_page_read(struct
>> nand_chip *chip)
>>
>> write_reg_dma(nandc, NAND_ADDR0, 2, 0);
>> write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
>> - write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
>> + if (!nandc->props->qpic_v2)
>> + write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
>> write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
>> write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
>> NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
>> @@ -1191,8 +1194,9 @@ static void config_nand_page_write(struct
>> nand_chip *chip)
>>
>> write_reg_dma(nandc, NAND_ADDR0, 2, 0);
>> write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
>> - write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
>> - NAND_BAM_NEXT_SGL);
>> + if (!nandc->props->qpic_v2)
>> + write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
>> + NAND_BAM_NEXT_SGL);
>> }
>>
>> /*
>> @@ -1248,7 +1252,8 @@ static int nandc_param(struct qcom_nand_host
>> *host)
>> | 2 << WR_RD_BSY_GAP
>> | 0 << WIDE_FLASH
>> | 1 << DEV0_CFG1_ECC_DISABLE);
>> - nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, 1 <<
>> ECC_CFG_ECC_DISABLE);
>> + if (!nandc->props->qpic_v2)
>> + nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, 1 <<
>> ECC_CFG_ECC_DISABLE);
>>
>> /* configure CMD1 and VLD for ONFI param probing in QPIC v1 */
>> if (!nandc->props->qpic_v2) {
>> @@ -2689,7 +2694,8 @@ static int qcom_nand_attach_chip(struct
>> nand_chip *chip)
>> | ecc_mode << ECC_MODE
>> | host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH;
>>
>> - host->ecc_buf_cfg = 0x203 << NUM_STEPS;
>> + if (!nandc->props->qpic_v2)
>> + host->ecc_buf_cfg = 0x203 << NUM_STEPS;
>>
>> host->clrflashstatus = FS_READY_BSY_N;
>> host->clrreadstatus = 0xc0;
>
>
> Thanks,
> Miquèl