2021-06-24 12:19:23

by Rajan Vaja

[permalink] [raw]
Subject: [PATCH v5 1/4] clk: zynqmp: Use firmware specific common clock flags

Currently firmware passes CCF specific flags to ZynqMP clock driver.
So firmware needs to be updated if CCF flags are changed. The firmware
should have its own 'flag number space' that is distinct from the
common clk framework's 'flag number space'. So define and use ZynqMP
specific common clock flags instead of using CCF flags.

Signed-off-by: Rajan Vaja <[email protected]>
---
drivers/clk/zynqmp/clk-gate-zynqmp.c | 4 +++-
drivers/clk/zynqmp/clk-mux-zynqmp.c | 4 +++-
drivers/clk/zynqmp/clk-zynqmp.h | 24 ++++++++++++++++++++
drivers/clk/zynqmp/clkc.c | 33 +++++++++++++++++++++++++++-
drivers/clk/zynqmp/divider.c | 5 +++--
drivers/clk/zynqmp/pll.c | 4 +++-
6 files changed, 68 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/zynqmp/clk-gate-zynqmp.c b/drivers/clk/zynqmp/clk-gate-zynqmp.c
index 10c9b889324f..695feaa82da5 100644
--- a/drivers/clk/zynqmp/clk-gate-zynqmp.c
+++ b/drivers/clk/zynqmp/clk-gate-zynqmp.c
@@ -121,7 +121,9 @@ struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,

init.name = name;
init.ops = &zynqmp_clk_gate_ops;
- init.flags = nodes->flag;
+
+ init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);
+
init.parent_names = parents;
init.num_parents = 1;

diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-mux-zynqmp.c
index 06194149be83..a49b1c586d5e 100644
--- a/drivers/clk/zynqmp/clk-mux-zynqmp.c
+++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c
@@ -120,7 +120,9 @@ struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
init.ops = &zynqmp_clk_mux_ro_ops;
else
init.ops = &zynqmp_clk_mux_ops;
- init.flags = nodes->flag;
+
+ init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);
+
init.parent_names = parents;
init.num_parents = num_parents;
mux->flags = nodes->type_flag;
diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h
index 5beeb41b29fa..974d3dae35a7 100644
--- a/drivers/clk/zynqmp/clk-zynqmp.h
+++ b/drivers/clk/zynqmp/clk-zynqmp.h
@@ -10,6 +10,28 @@

#include <linux/firmware/xlnx-zynqmp.h>

+/* Common Flags */
+/* must be gated across rate change */
+#define ZYNQMP_CLK_SET_RATE_GATE BIT(0)
+/* must be gated across re-parent */
+#define ZYNQMP_CLK_SET_PARENT_GATE BIT(1)
+/* propagate rate change up one level */
+#define ZYNQMP_CLK_SET_RATE_PARENT BIT(2)
+/* do not gate even if unused */
+#define ZYNQMP_CLK_IGNORE_UNUSED BIT(3)
+/* do not use the cached clk rate */
+#define ZYNQMP_CLK_GET_RATE_NOCACHE BIT(6)
+/* don't re-parent on rate change */
+#define ZYNQMP_CLK_SET_RATE_NO_REPARENT BIT(7)
+/* do not use the cached clk accuracy */
+#define ZYNQMP_CLK_GET_ACCURACY_NOCACHE BIT(8)
+/* recalc rates after notifications */
+#define ZYNQMP_CLK_RECALC_NEW_RATES BIT(9)
+/* clock needs to run to set rate */
+#define ZYNQMP_CLK_SET_RATE_UNGATE BIT(10)
+/* do not gate, ever */
+#define ZYNQMP_CLK_IS_CRITICAL BIT(11)
+
enum topology_type {
TYPE_INVALID,
TYPE_MUX,
@@ -33,6 +55,8 @@ struct clock_topology {
u8 custom_type_flag;
};

+unsigned long zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag);
+
struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
const char * const *parents,
u8 num_parents,
diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
index db8d0d7161ce..af06a195ec46 100644
--- a/drivers/clk/zynqmp/clkc.c
+++ b/drivers/clk/zynqmp/clkc.c
@@ -271,6 +271,34 @@ static int zynqmp_pm_clock_get_topology(u32 clock_id, u32 index,
return ret;
}

+unsigned long zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag)
+{
+ unsigned long ccf_flag = 0;
+
+ if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_GATE)
+ ccf_flag |= CLK_SET_RATE_GATE;
+ if (zynqmp_flag & ZYNQMP_CLK_SET_PARENT_GATE)
+ ccf_flag |= CLK_SET_PARENT_GATE;
+ if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_PARENT)
+ ccf_flag |= CLK_SET_RATE_PARENT;
+ if (zynqmp_flag & ZYNQMP_CLK_IGNORE_UNUSED)
+ ccf_flag |= CLK_IGNORE_UNUSED;
+ if (zynqmp_flag & ZYNQMP_CLK_GET_RATE_NOCACHE)
+ ccf_flag |= CLK_GET_RATE_NOCACHE;
+ if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_NO_REPARENT)
+ ccf_flag |= CLK_SET_RATE_NO_REPARENT;
+ if (zynqmp_flag & ZYNQMP_CLK_GET_ACCURACY_NOCACHE)
+ ccf_flag |= CLK_GET_ACCURACY_NOCACHE;
+ if (zynqmp_flag & ZYNQMP_CLK_RECALC_NEW_RATES)
+ ccf_flag |= CLK_RECALC_NEW_RATES;
+ if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_UNGATE)
+ ccf_flag |= CLK_SET_RATE_UNGATE;
+ if (zynqmp_flag & ZYNQMP_CLK_IS_CRITICAL)
+ ccf_flag |= CLK_IS_CRITICAL;
+
+ return ccf_flag;
+}
+
/**
* zynqmp_clk_register_fixed_factor() - Register fixed factor with the
* clock framework
@@ -292,6 +320,7 @@ struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id,
struct zynqmp_pm_query_data qdata = {0};
u32 ret_payload[PAYLOAD_ARG_CNT];
int ret;
+ unsigned long flag;

qdata.qid = PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS;
qdata.arg1 = clk_id;
@@ -303,9 +332,11 @@ struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id,
mult = ret_payload[1];
div = ret_payload[2];

+ flag = zynqmp_clk_map_common_ccf_flags(nodes->flag);
+
hw = clk_hw_register_fixed_factor(NULL, name,
parents[0],
- nodes->flag, mult,
+ flag, mult,
div);

return hw;
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index e9bf7958b821..0becdc0a8bff 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -312,8 +312,9 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,

init.name = name;
init.ops = &zynqmp_clk_divider_ops;
- /* CLK_FRAC is not defined in the common clk framework */
- init.flags = nodes->flag & ~CLK_FRAC;
+
+ init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);
+
init.parent_names = parents;
init.num_parents = 1;

diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c
index abe6afbf3407..e0bceb07740f 100644
--- a/drivers/clk/zynqmp/pll.c
+++ b/drivers/clk/zynqmp/pll.c
@@ -312,7 +312,9 @@ struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,

init.name = name;
init.ops = &zynqmp_pll_ops;
- init.flags = nodes->flag;
+
+ init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);
+
init.parent_names = parents;
init.num_parents = 1;

--
2.32.0.93.g670b81a


2021-06-25 23:25:07

by Stephen Boyd

[permalink] [raw]
Subject: Re: [PATCH v5 1/4] clk: zynqmp: Use firmware specific common clock flags

Quoting Rajan Vaja (2021-06-24 05:16:30)
> diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
> index db8d0d7161ce..af06a195ec46 100644
> --- a/drivers/clk/zynqmp/clkc.c
> +++ b/drivers/clk/zynqmp/clkc.c
> @@ -271,6 +271,34 @@ static int zynqmp_pm_clock_get_topology(u32 clock_id, u32 index,
> return ret;
> }
>
> +unsigned long zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag)
> +{
> + unsigned long ccf_flag = 0;
> +
> + if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_GATE)
> + ccf_flag |= CLK_SET_RATE_GATE;
> + if (zynqmp_flag & ZYNQMP_CLK_SET_PARENT_GATE)
> + ccf_flag |= CLK_SET_PARENT_GATE;
> + if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_PARENT)
> + ccf_flag |= CLK_SET_RATE_PARENT;
> + if (zynqmp_flag & ZYNQMP_CLK_IGNORE_UNUSED)
> + ccf_flag |= CLK_IGNORE_UNUSED;
> + if (zynqmp_flag & ZYNQMP_CLK_GET_RATE_NOCACHE)
> + ccf_flag |= CLK_GET_RATE_NOCACHE;

Does the firmware really use all these flags? Ideally we get rid of the
above two.

> + if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_NO_REPARENT)
> + ccf_flag |= CLK_SET_RATE_NO_REPARENT;
> + if (zynqmp_flag & ZYNQMP_CLK_GET_ACCURACY_NOCACHE)
> + ccf_flag |= CLK_GET_ACCURACY_NOCACHE;
> + if (zynqmp_flag & ZYNQMP_CLK_RECALC_NEW_RATES)
> + ccf_flag |= CLK_RECALC_NEW_RATES;

And this one.

> + if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_UNGATE)
> + ccf_flag |= CLK_SET_RATE_UNGATE;
> + if (zynqmp_flag & ZYNQMP_CLK_IS_CRITICAL)
> + ccf_flag |= CLK_IS_CRITICAL;

And this one.

I worry that supporting all these flags will mean we can never get rid
of them. And we currently don't support setting critical via DT, which
is essentially another firmware interface like this one.

> +
> + return ccf_flag;
> +}
> +
> /**
> * zynqmp_clk_register_fixed_factor() - Register fixed factor with the
> * clock framework

2021-06-28 07:01:32

by Rajan Vaja

[permalink] [raw]
Subject: RE: [PATCH v5 1/4] clk: zynqmp: Use firmware specific common clock flags

Hi Stephen,

> -----Original Message-----
> From: Stephen Boyd <[email protected]>
> Sent: Friday, June 25, 2021 4:22 PM
> To: Rajan Vaja <[email protected]>; [email protected]; [email protected];
> Michal Simek <[email protected]>; [email protected];
> [email protected]
> Cc: [email protected]; [email protected]; linux-
> [email protected]; Rajan Vaja <[email protected]>
> Subject: Re: [PATCH v5 1/4] clk: zynqmp: Use firmware specific common clock
> flags
>
> Quoting Rajan Vaja (2021-06-24 05:16:30)
> > diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
> > index db8d0d7161ce..af06a195ec46 100644
> > --- a/drivers/clk/zynqmp/clkc.c
> > +++ b/drivers/clk/zynqmp/clkc.c
> > @@ -271,6 +271,34 @@ static int zynqmp_pm_clock_get_topology(u32
> clock_id, u32 index,
> > return ret;
> > }
> >
> > +unsigned long zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag)
> > +{
> > + unsigned long ccf_flag = 0;
> > +
> > + if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_GATE)
> > + ccf_flag |= CLK_SET_RATE_GATE;
> > + if (zynqmp_flag & ZYNQMP_CLK_SET_PARENT_GATE)
> > + ccf_flag |= CLK_SET_PARENT_GATE;
> > + if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_PARENT)
> > + ccf_flag |= CLK_SET_RATE_PARENT;
> > + if (zynqmp_flag & ZYNQMP_CLK_IGNORE_UNUSED)
> > + ccf_flag |= CLK_IGNORE_UNUSED;
> > + if (zynqmp_flag & ZYNQMP_CLK_GET_RATE_NOCACHE)
> > + ccf_flag |= CLK_GET_RATE_NOCACHE;
>
> Does the firmware really use all these flags? Ideally we get rid of the
> above two.
>
> > + if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_NO_REPARENT)
> > + ccf_flag |= CLK_SET_RATE_NO_REPARENT;
> > + if (zynqmp_flag & ZYNQMP_CLK_GET_ACCURACY_NOCACHE)
> > + ccf_flag |= CLK_GET_ACCURACY_NOCACHE;
> > + if (zynqmp_flag & ZYNQMP_CLK_RECALC_NEW_RATES)
> > + ccf_flag |= CLK_RECALC_NEW_RATES;
>
> And this one.
>
> > + if (zynqmp_flag & ZYNQMP_CLK_SET_RATE_UNGATE)
> > + ccf_flag |= CLK_SET_RATE_UNGATE;
> > + if (zynqmp_flag & ZYNQMP_CLK_IS_CRITICAL)
> > + ccf_flag |= CLK_IS_CRITICAL;
>
> And this one.
>
> I worry that supporting all these flags will mean we can never get rid
> of them. And we currently don't support setting critical via DT, which
> is essentially another firmware interface like this one.
[Rajan] firmware is using below flags:
ZYNQMP_CLK_SET_RATE_GATE
ZYNQMP_CLK_SET_PARENT_GATE
ZYNQMP_CLK_SET_RATE_PARENT
ZYNQMP_CLK_IGNORE_UNUSED
ZYNQMP_CLK_SET_RATE_NO_REPARENT
ZYNQMP_CLK_IS_CRITICAL

Other flags are unused. I will remove unused flags in next version.

Thanks,
Rajan
>
> > +
> > + return ccf_flag;
> > +}
> > +
> > /**
> > * zynqmp_clk_register_fixed_factor() - Register fixed factor with the
> > * clock framework