2021-12-27 13:32:35

by qizhong cheng

Subject: [PATCH v3] PCI: mediatek: Assert PERST# for 100ms for power and clock to stabilize

Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
be delayed 100ms (TPVPERL) for the power and clock to become stable.

Signed-off-by: qizhong cheng <[email protected]>
Acked-by: Pali Rohár <[email protected]>
---

v3:
- Change subject.

v2:
- Typo fix.
- Rewrap into one paragraph.

drivers/pci/controller/pcie-mediatek.c | 7 +++++++
1 file changed, 7 insertions(+)

diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index 2f3f974977a3..b18935e8da89 100644
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -702,6 +702,13 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
*/
writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);

+ /*
+ * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
+ * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
+ * be delayed 100ms (TPVPERL) for the power and clock to become stable.
+ */
+ msleep(100);
+
/* De-assert PHY, PE, PIPE, MAC and configuration reset */
val = readl(port->base + PCIE_RST_CTRL);
val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
--
2.25.1

2022-01-07 10:22:57

by Lorenzo Pieralisi

Subject: Re: [PATCH v3] PCI: mediatek: Assert PERST# for 100ms for power and clock to stabilize

On Mon, 27 Dec 2021 21:31:10 +0800, qizhong cheng wrote:
> Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
> 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
> be delayed 100ms (TPVPERL) for the power and clock to become stable.
>
>

Applied to pci/mediatek, thanks!

[1/1] PCI: mediatek: Assert PERST# for 100ms for power and clock to stabilize
https://git.kernel.org/lpieralisi/pci/c/65ace9a85f

Thanks,
Lorenzo