This series is to add DSI PHY tuning support in Qualcomm Snapdragon
SoCs with 10nm DSI PHY e.g. SC7180
In most cases the default values of DSI PHY tuning registers
should be sufficient as they are fully optimized. However, in
some cases (for example, where extreme board parasitics cause
the eye shape to degrade), the override bits can be used to
improve the signal quality.
Different DSI PHY versions have different configurations to adjust the
drive strength, drive level, de-emphasis, etc. The current series has only
those configuration options supported by 10nm PHY, e.g. drive strength and
drive level. The number of registers to configure the drive strength are
different for 7nm PHY. The design can be extended to other DSI PHY versions
if required, as each PHY version can have its callback to get the input
from DT and prepare register values.
Changes in v2:
- Addressed dt-bindings comments (Stephen Boyd, Dmitry Baryshkov)
- Split into generic code and 10nm-specific part (Dmitry Baryshkov)
- Fix the backward compatibility (Dmitry Baryshkov)
Changes in v3:
- Addressed dt-bindings comments (Rob Herring, Dmitry Baryshkov)
- Address comments for phy tuning data structure (Dmitry Baryshkov)
- s/ops.tuning_cfg_init/ops.parse_dt_properties (Dmitry Baryshkov)
Changes in v4:
- Fixed dt_binding_check error (Rob Herring's bot)
- Return error in case of out of range values (Dmitry Baryshkov)
- Return error if dt property is present but parsing is failing
Changes in v5:
- Fixed missing printk arg
Rajeev Nandan (3):
dt-bindings: msm/dsi: Add 10nm dsi phy tuning properties
drm/msm/dsi: Add dsi phy tuning configuration support
drm/msm/dsi: Add 10nm dsi phy tuning configuration support
.../bindings/display/msm/dsi-phy-10nm.yaml | 36 +++++++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 6 ++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 4 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 118 +++++++++++++++++++--
4 files changed, 158 insertions(+), 6 deletions(-)
--
2.7.4
In most cases, the default values of DSI PHY tuning registers should be
sufficient as they are fully optimized. However, in some cases where
extreme board parasitics cause the eye shape to degrade, the override
bits can be used to improve the signal quality.
The general guidelines for DSI PHY tuning include:
- High and moderate data rates may benefit from the drive strength and
drive level tuning.
- Drive strength tuning will affect the output impedance and may be used
for matching optimization.
- Drive level tuning will affect the output levels without affecting the
impedance.
The clock and data lanes have a calibration circuitry feature. The drive
strength tuning can be done by adjusting rescode offset for hstop/hsbot,
and the drive level tuning can be done by adjusting the LDO output level
for the HSTX drive.
Signed-off-by: Rajeev Nandan <[email protected]>
---
Changes in v2:
- More details in the commit text (Stephen Boyd)
- Use human understandable values (Stephen Boyd, Dmitry Baryshkov)
- Do not take values that are going to be unused (Dmitry Baryshkov)
Changes in v3:
- Use "qcom," prefix (Dmitry Baryshkov)
- Remove encoding from phy-drive-ldo-level (Dmitry Baryshkov)
- Use negative values instead of two's complement (Dmitry, Rob Herring)
Changes in v4:
- Fix dt_binding_check error (Rob Herring's bot)
Changes in v5:
- None
.../bindings/display/msm/dsi-phy-10nm.yaml | 36 ++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
index 4399715..2d5a766 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
@@ -35,6 +35,38 @@ properties:
Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
+ qcom,phy-rescode-offset-top:
+ $ref: /schemas/types.yaml#/definitions/int8-array
+ minItems: 5
+ maxItems: 5
+ description:
+ Integer array of offset for pull-up legs rescode for all five lanes.
+ To offset the drive strength from the calibrated value in an increasing
+ manner, -32 is the weakest and +31 is the strongest.
+ items:
+ minimum: -32
+ maximum: 31
+
+ qcom,phy-rescode-offset-bot:
+ $ref: /schemas/types.yaml#/definitions/int8-array
+ minItems: 5
+ maxItems: 5
+ description:
+ Integer array of offset for pull-down legs rescode for all five lanes.
+ To offset the drive strength from the calibrated value in a decreasing
+ manner, -32 is the weakest and +31 is the strongest.
+ items:
+ minimum: -32
+ maximum: 31
+
+ qcom,phy-drive-ldo-level:
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ description:
+ The PHY LDO has an amplitude tuning feature to adjust the LDO output
+ for the HSTX drive. Use supported levels (mV) to offset the drive level
+ from the default value.
+ enum: [ 375, 400, 425, 450, 475, 500 ]
+
required:
- compatible
- reg
@@ -64,5 +96,9 @@ examples:
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "ref";
+
+ qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
+ qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
+ qcom,phy-drive-ldo-level = <400>;
};
...
--
2.7.4
On Mon, 31 Jan 2022 01:45:17 +0530, Rajeev Nandan wrote:
> In most cases, the default values of DSI PHY tuning registers should be
> sufficient as they are fully optimized. However, in some cases where
> extreme board parasitics cause the eye shape to degrade, the override
> bits can be used to improve the signal quality.
>
> The general guidelines for DSI PHY tuning include:
> - High and moderate data rates may benefit from the drive strength and
> drive level tuning.
> - Drive strength tuning will affect the output impedance and may be used
> for matching optimization.
> - Drive level tuning will affect the output levels without affecting the
> impedance.
>
> The clock and data lanes have a calibration circuitry feature. The drive
> strength tuning can be done by adjusting rescode offset for hstop/hsbot,
> and the drive level tuning can be done by adjusting the LDO output level
> for the HSTX drive.
>
> Signed-off-by: Rajeev Nandan <[email protected]>
> ---
>
> Changes in v2:
> - More details in the commit text (Stephen Boyd)
> - Use human understandable values (Stephen Boyd, Dmitry Baryshkov)
> - Do not take values that are going to be unused (Dmitry Baryshkov)
>
> Changes in v3:
> - Use "qcom," prefix (Dmitry Baryshkov)
> - Remove encoding from phy-drive-ldo-level (Dmitry Baryshkov)
> - Use negative values instead of two's complement (Dmitry, Rob Herring)
>
> Changes in v4:
> - Fix dt_binding_check error (Rob Herring's bot)
>
> Changes in v5:
> - None
>
> .../bindings/display/msm/dsi-phy-10nm.yaml | 36 ++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
Reviewed-by: Rob Herring <[email protected]>