Add YAML binding for Cortex A7 PLL clock in Qualcomm
platforms like SDX65.
Signed-off-by: Rohit Agarwal <[email protected]>
---
Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
index 8666e99..b8889dc 100644
--- a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
@@ -10,13 +10,14 @@ maintainers:
- Manivannan Sadhasivam <[email protected]>
description:
- The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high
+ The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
frequency clock to the CPU.
properties:
compatible:
enum:
- qcom,sdx55-a7pll
+ - qcom,sdx65-a7pll
reg:
maxItems: 1
--
2.7.4
On Mon, Feb 14, 2022 at 12:27:49PM +0530, Rohit Agarwal wrote:
> Add YAML binding for Cortex A7 PLL clock in Qualcomm
> platforms like SDX65.
>
> Signed-off-by: Rohit Agarwal <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Thanks,
Mani
> ---
> Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
> index 8666e99..b8889dc 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
> @@ -10,13 +10,14 @@ maintainers:
> - Manivannan Sadhasivam <[email protected]>
>
> description:
> - The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high
> + The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
> frequency clock to the CPU.
>
> properties:
> compatible:
> enum:
> - qcom,sdx55-a7pll
> + - qcom,sdx65-a7pll
>
> reg:
> maxItems: 1
> --
> 2.7.4
>