2022-03-21 22:05:01

by Srinivasa Rao Mandadapu

Subject: [PATCH v5 3/3] arm64: dts: qcom: sc7280: add lpass lpi pin controller node

Add LPASS LPI pinctrl node required for Audio functionality on sc7280
based platforms.

Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
Co-developed-by: Venkata Prasad Potturu <[email protected]>
Signed-off-by: Venkata Prasad Potturu <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 147 +++++++++++++++++++++++++++++++++++
1 file changed, 147 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 8d8cec5..499299a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -1987,6 +1987,153 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};

+ lpass_tlmm: pinctrl@33c0000 {
+ compatible = "qcom,sc7280-lpass-lpi-pinctrl";
+ reg = <0 0x33c0000 0x0 0x20000>,
+ <0 0x3550000 0x0 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpass_tlmm 0 0 15>;
+
+ #clock-cells = <1>;
+
+ dmic01_active: dmic01-active {
+ clk {
+ pins = "gpio6";
+ function = "dmic1_clk";
+ drive-strength = <8>;
+ output-high;
+ };
+
+ data {
+ pins = "gpio7";
+ function = "dmic1_data";
+ drive-strength = <8>;
+ };
+ };
+
+ dmic01_sleep: dmic01-sleep {
+ clk {
+ pins = "gpio6";
+ function = "dmic1_clk";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+
+ data {
+ pins = "gpio7";
+ function = "dmic1_data";
+ drive-strength = <2>;
+ pull-down;
+ };
+ };
+
+ dmic23_active: dmic02-active {
+ clk {
+ pins = "gpio8";
+ function = "dmic2_clk";
+ drive-strength = <8>;
+ output-high;
+ };
+
+ data {
+ pins = "gpio9";
+ function = "dmic2_data";
+ drive-strength = <8>;
+ };
+ };
+
+ dmic23_sleep: dmic02-sleep {
+ clk {
+ pins = "gpio8";
+ function = "dmic2_clk";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+
+ data {
+ pins = "gpio9";
+ function = "dmic2_data";
+ drive-strength = <2>;
+ pull-down;
+ };
+ };
+
+ rx_swr_active: rx-swr-active {
+ clk {
+ pins = "gpio3";
+ function = "swr_rx_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data {
+ pins = "gpio4", "gpio5";
+ function = "swr_rx_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ rx_swr_sleep: rx-swr-sleep {
+ clk {
+ pins = "gpio3";
+ function = "swr_rx_clk";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+
+ data {
+ pins = "gpio4", "gpio5";
+ function = "swr_rx_data";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ tx_swr_active: tx-swr-active {
+ clk {
+ pins = "gpio0";
+ function = "swr_tx_clk";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+
+ data {
+ pins = "gpio1", "gpio2", "gpio14";
+ function = "swr_tx_data";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ tx_swr_sleep: tx-swr-sleep {
+ clk {
+ pins = "gpio0";
+ function = "swr_tx_clk";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+
+ data {
+ pins = "gpio1", "gpio2", "gpio14";
+ function = "swr_tx_data";
+ drive-strength = <2>;
+ input-enable;
+ bias-bus-hold;
+ };
+ };
+ };
+
gpu: gpu@3d00000 {
compatible = "qcom,adreno-635.0", "qcom,adreno";
reg = <0 0x03d00000 0 0x40000>,
--
2.7.4

2022-03-21 22:25:00

by Stephen Boyd

Subject: Re: [PATCH v5 3/3] arm64: dts: qcom: sc7280: add lpass lpi pin controller node

Quoting Srinivasa Rao Mandadapu (2022-03-21 04:59:19)
> Add LPASS LPI pinctrl node required for Audio functionality on sc7280
> based platforms.
>
> Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
> Co-developed-by: Venkata Prasad Potturu <[email protected]>
> Signed-off-by: Venkata Prasad Potturu <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 147 +++++++++++++++++++++++++++++++++++
> 1 file changed, 147 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 8d8cec5..499299a 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1987,6 +1987,153 @@
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> + lpass_tlmm: pinctrl@33c0000 {
> + compatible = "qcom,sc7280-lpass-lpi-pinctrl";
> + reg = <0 0x33c0000 0x0 0x20000>,
> + <0 0x3550000 0x0 0x10000>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&lpass_tlmm 0 0 15>;
> +
> + #clock-cells = <1>;
> +
> + dmic01_active: dmic01-active {
> + clk {
> + pins = "gpio6";
> + function = "dmic1_clk";
> + drive-strength = <8>;
> + output-high;

The rule of thumb is that drive strength, output/input, and bias
properties should be in the board file, because the board layout decides
the drive strength, the output level could be inverted on the board, and
the biasing could be done externally (or not) via pullup/pulldowns on
the net. The gpio driver should be able to make pins into inputs
automatically when the gpio is requested and used so having input or
output is typically wrong and should be handled by the consumer driver.

> + };
> +
> + data {
> + pins = "gpio7";
> + function = "dmic1_data";

So in the end I'd expect to only see pins and function properties in the
SoC dtsi file.

> + drive-strength = <8>;
> + };
> + };
> +
> + dmic01_sleep: dmic01-sleep {
> + clk {
> + pins = "gpio6";
> + function = "dmic1_clk";

2022-04-05 05:17:52

by Srinivasa Rao Mandadapu

Subject: Re: [PATCH v5 3/3] arm64: dts: qcom: sc7280: add lpass lpi pin controller node

On 3/22/2022 1:56 AM, Stephen Boyd wrote:
> Quoting Srinivasa Rao Mandadapu (2022-03-21 04:59:19)
>> Add LPASS LPI pinctrl node required for Audio functionality on sc7280
>> based platforms.
>>
>> Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
>> Co-developed-by: Venkata Prasad Potturu <[email protected]>
>> Signed-off-by: Venkata Prasad Potturu <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 147 +++++++++++++++++++++++++++++++++++
>> 1 file changed, 147 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 8d8cec5..499299a 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -1987,6 +1987,153 @@
>> qcom,bcm-voters = <&apps_bcm_voter>;
>> };
>>
>> + lpass_tlmm: pinctrl@33c0000 {
>> + compatible = "qcom,sc7280-lpass-lpi-pinctrl";
>> + reg = <0 0x33c0000 0x0 0x20000>,
>> + <0 0x3550000 0x0 0x10000>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + gpio-ranges = <&lpass_tlmm 0 0 15>;
>> +
>> + #clock-cells = <1>;
>> +
>> + dmic01_active: dmic01-active {
>> + clk {
>> + pins = "gpio6";
>> + function = "dmic1_clk";
>> + drive-strength = <8>;
>> + output-high;
> The rule of thumb is that drive strength, output/input, and bias
> properties should be in the board file, because the board layout decides
> the drive strength, the output level could be inverted on the board, and
> the biasing could be done externally (or not) via pullup/pulldowns on
> the net. The gpio driver should be able to make pins into inputs
> automatically when the gpio is requested and used so having input or
> output is typically wrong and should be handled by the consumer driver.
Okay. will re arrange accordingly and remove output-high property.
>
>> + };
>> +
>> + data {
>> + pins = "gpio7";
>> + function = "dmic1_data";
> So in the end I'd expect to only see pins and function properties in the
> SoC dtsi file.
Okay.
>
>> + drive-strength = <8>;
>> + };
>> + };
>> +
>> + dmic01_sleep: dmic01-sleep {
>> + clk {
>> + pins = "gpio6";
>> + function = "dmic1_clk";