Use TOD_READ_SECONDARY for extts to keep TOD_READ_PRIMARY
for gettime and settime exclusively
Signed-off-by: Min Li <[email protected]>
---
drivers/ptp/ptp_clockmatrix.c | 303 +++++++++++++++++++++++++--------------
drivers/ptp/ptp_clockmatrix.h | 5 +
include/linux/mfd/idt8a340_reg.h | 12 +-
3 files changed, 209 insertions(+), 111 deletions(-)
diff --git a/drivers/ptp/ptp_clockmatrix.c b/drivers/ptp/ptp_clockmatrix.c
index 08e429a..0e8e698 100644
--- a/drivers/ptp/ptp_clockmatrix.c
+++ b/drivers/ptp/ptp_clockmatrix.c
@@ -239,73 +239,101 @@ static int wait_for_boot_status_ready(struct idtcm *idtcm)
return -EBUSY;
}
-static int _idtcm_set_scsr_read_trig(struct idtcm_channel *channel,
- enum scsr_read_trig_sel trig, u8 ref)
+static int arm_tod_read_trig_sel_refclk(struct idtcm_channel *channel, u8 ref)
{
struct idtcm *idtcm = channel->idtcm;
- u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_PRIMARY_CMD);
- u8 val;
+ u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_SECONDARY_CMD);
+ u8 val = 0;
int err;
- if (trig == SCSR_TOD_READ_TRIG_SEL_REFCLK) {
- err = idtcm_read(idtcm, channel->tod_read_primary,
- TOD_READ_PRIMARY_SEL_CFG_0, &val, sizeof(val));
- if (err)
- return err;
-
- val &= ~(WR_REF_INDEX_MASK << WR_REF_INDEX_SHIFT);
- val |= (ref << WR_REF_INDEX_SHIFT);
+ val &= ~(WR_REF_INDEX_MASK << WR_REF_INDEX_SHIFT);
+ val |= (ref << WR_REF_INDEX_SHIFT);
- err = idtcm_write(idtcm, channel->tod_read_primary,
- TOD_READ_PRIMARY_SEL_CFG_0, &val, sizeof(val));
- if (err)
- return err;
- }
-
- err = idtcm_read(idtcm, channel->tod_read_primary,
- tod_read_cmd, &val, sizeof(val));
+ err = idtcm_write(idtcm, channel->tod_read_secondary,
+ TOD_READ_SECONDARY_SEL_CFG_0, &val, sizeof(val));
if (err)
return err;
- val &= ~(TOD_READ_TRIGGER_MASK << TOD_READ_TRIGGER_SHIFT);
- val |= (trig << TOD_READ_TRIGGER_SHIFT);
- val &= ~TOD_READ_TRIGGER_MODE; /* single shot */
+ val = 0 | (SCSR_TOD_READ_TRIG_SEL_REFCLK << TOD_READ_TRIGGER_SHIFT);
+
+ err = idtcm_write(idtcm, channel->tod_read_secondary, tod_read_cmd,
+ &val, sizeof(val));
+
+ if (err)
+ dev_err(idtcm->dev, "%s: err = %d", __func__, err);
- err = idtcm_write(idtcm, channel->tod_read_primary,
- tod_read_cmd, &val, sizeof(val));
return err;
}
-static int idtcm_enable_extts(struct idtcm_channel *channel, u8 todn, u8 ref,
- bool enable)
+static bool is_single_shot(u8 mask)
{
- struct idtcm *idtcm = channel->idtcm;
- u8 old_mask = idtcm->extts_mask;
- u8 mask = 1 << todn;
+ /* Treat single bit ToD masks as continuous trigger */
+ if ((mask == 1) || (mask == 2) || (mask == 4) || (mask == 8))
+ return false;
+ else
+ return true;
+}
+
+static int idtcm_extts_enable(struct idtcm_channel *channel,
+ struct ptp_clock_request *rq, int on)
+{
+ u8 index = rq->extts.index;
+ struct idtcm *idtcm;
+ u8 mask = 1 << index;
int err = 0;
+ u8 old_mask;
+ int ref;
- if (todn >= MAX_TOD)
+ idtcm = channel->idtcm;
+ old_mask = idtcm->extts_mask;
+
+ /* Reject requests with unsupported flags */
+ if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
+ PTP_RISING_EDGE |
+ PTP_FALLING_EDGE |
+ PTP_STRICT_FLAGS))
+ return -EOPNOTSUPP;
+
+ /* Reject requests to enable time stamping on falling edge */
+ if ((rq->extts.flags & PTP_ENABLE_FEATURE) &&
+ (rq->extts.flags & PTP_FALLING_EDGE))
+ return -EOPNOTSUPP;
+
+ if (index >= MAX_TOD)
return -EINVAL;
- if (enable) {
- if (ref > 0xF) /* E_REF_CLK15 */
- return -EINVAL;
- if (idtcm->extts_mask & mask)
- return 0;
- err = _idtcm_set_scsr_read_trig(&idtcm->channel[todn],
- SCSR_TOD_READ_TRIG_SEL_REFCLK,
- ref);
+ if (on) {
+ /* Support triggering more than one TOD_0/1/2/3 by same pin */
+ /* Use the pin configured for the channel */
+ ref = ptp_find_pin(channel->ptp_clock, PTP_PF_EXTTS, channel->tod);
+
+ if (ref < 0) {
+ dev_err(idtcm->dev, "%s: No valid pin found for TOD%d!\n",
+ __func__, channel->tod);
+ return -EBUSY;
+ }
+
+ err = arm_tod_read_trig_sel_refclk(&idtcm->channel[index], ref);
+
if (err == 0) {
idtcm->extts_mask |= mask;
- idtcm->event_channel[todn] = channel;
- idtcm->channel[todn].refn = ref;
+ idtcm->event_channel[index] = channel;
+ idtcm->channel[index].refn = ref;
+ idtcm->extts_single_shot = is_single_shot(idtcm->extts_mask);
+
+ if (old_mask)
+ return 0;
+
+ schedule_delayed_work(&idtcm->extts_work,
+ msecs_to_jiffies(EXTTS_PERIOD_MS));
}
- } else
+ } else {
idtcm->extts_mask &= ~mask;
+ idtcm->extts_single_shot = is_single_shot(idtcm->extts_mask);
- if (old_mask == 0 && idtcm->extts_mask)
- schedule_delayed_work(&idtcm->extts_work,
- msecs_to_jiffies(EXTTS_PERIOD_MS));
+ if (idtcm->extts_mask == 0)
+ cancel_delayed_work(&idtcm->extts_work);
+ }
return err;
}
@@ -371,6 +399,34 @@ static void wait_for_chip_ready(struct idtcm *idtcm)
"Continuing while SYS APLL/DPLL is not locked");
}
+static int _idtcm_gettime_triggered(struct idtcm_channel *channel,
+ struct timespec64 *ts)
+{
+ struct idtcm *idtcm = channel->idtcm;
+ u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_SECONDARY_CMD);
+ u8 buf[TOD_BYTE_COUNT];
+ u8 trigger;
+ int err;
+
+ err = idtcm_read(idtcm, channel->tod_read_secondary,
+ tod_read_cmd, &trigger, sizeof(trigger));
+ if (err)
+ return err;
+
+ if (trigger & TOD_READ_TRIGGER_MASK)
+ return -EBUSY;
+
+ err = idtcm_read(idtcm, channel->tod_read_secondary,
+ TOD_READ_SECONDARY_BASE, buf, sizeof(buf));
+
+ if (err)
+ return err;
+
+ err = char_array_to_timespec(buf, sizeof(buf), ts);
+
+ return err;
+}
+
static int _idtcm_gettime(struct idtcm_channel *channel,
struct timespec64 *ts, u8 timeout)
{
@@ -396,7 +452,7 @@ static int _idtcm_gettime(struct idtcm_channel *channel,
} while (trigger & TOD_READ_TRIGGER_MASK);
err = idtcm_read(idtcm, channel->tod_read_primary,
- TOD_READ_PRIMARY, buf, sizeof(buf));
+ TOD_READ_PRIMARY_BASE, buf, sizeof(buf));
if (err)
return err;
@@ -415,65 +471,40 @@ static int idtcm_extts_check_channel(struct idtcm *idtcm, u8 todn)
extts_channel = &idtcm->channel[todn];
ptp_channel = idtcm->event_channel[todn];
+
if (extts_channel == ptp_channel)
dco_delay = ptp_channel->dco_delay;
- err = _idtcm_gettime(extts_channel, &ts, 1);
- if (err == 0) {
- event.type = PTP_CLOCK_EXTTS;
- event.index = todn;
- event.timestamp = timespec64_to_ns(&ts) - dco_delay;
- ptp_clock_event(ptp_channel->ptp_clock, &event);
- }
- return err;
-}
+ err = _idtcm_gettime_triggered(extts_channel, &ts);
-static u8 idtcm_enable_extts_mask(struct idtcm_channel *channel,
- u8 extts_mask, bool enable)
-{
- struct idtcm *idtcm = channel->idtcm;
- int i, err;
+ if (err)
+ return err;
- for (i = 0; i < MAX_TOD; i++) {
- u8 mask = 1 << i;
- u8 refn = idtcm->channel[i].refn;
-
- if (extts_mask & mask) {
- /* check extts before disabling it */
- if (enable == false) {
- err = idtcm_extts_check_channel(idtcm, i);
- /* trigger happened so we won't re-enable it */
- if (err == 0)
- extts_mask &= ~mask;
- }
- (void)idtcm_enable_extts(channel, i, refn, enable);
- }
- }
+ /* Triggered - save timestamp */
+ event.type = PTP_CLOCK_EXTTS;
+ event.index = todn;
+ event.timestamp = timespec64_to_ns(&ts) - dco_delay;
+ ptp_clock_event(ptp_channel->ptp_clock, &event);
- return extts_mask;
+ return err;
}
static int _idtcm_gettime_immediate(struct idtcm_channel *channel,
struct timespec64 *ts)
{
struct idtcm *idtcm = channel->idtcm;
- u8 extts_mask = 0;
+
+ u16 tod_read_cmd = IDTCM_FW_REG(idtcm->fw_ver, V520, TOD_READ_PRIMARY_CMD);
+ u8 val = (SCSR_TOD_READ_TRIG_SEL_IMMEDIATE << TOD_READ_TRIGGER_SHIFT);
int err;
- /* Disable extts */
- if (idtcm->extts_mask) {
- extts_mask = idtcm_enable_extts_mask(channel, idtcm->extts_mask,
- false);
- }
+ err = idtcm_write(idtcm, channel->tod_read_primary,
+ tod_read_cmd, &val, sizeof(val));
- err = _idtcm_set_scsr_read_trig(channel,
- SCSR_TOD_READ_TRIG_SEL_IMMEDIATE, 0);
- if (err == 0)
- err = _idtcm_gettime(channel, ts, 10);
+ if (err)
+ return err;
- /* Re-enable extts */
- if (extts_mask)
- idtcm_enable_extts_mask(channel, extts_mask, true);
+ err = _idtcm_gettime(channel, ts, 10);
return err;
}
@@ -1557,8 +1588,8 @@ static s32 phase_pull_in_scaled_ppm(s32 current_ppm, s32 phase_pull_in_ppb)
/* ppb = scaled_ppm * 125 / 2^13 */
/* scaled_ppm = ppb * 2^13 / 125 */
- s64 max_scaled_ppm = div_s64((s64)PHASE_PULL_IN_MAX_PPB << 13, 125);
- s64 scaled_ppm = div_s64((s64)phase_pull_in_ppb << 13, 125);
+ s64 max_scaled_ppm = (PHASE_PULL_IN_MAX_PPB << 13) / 125;
+ s64 scaled_ppm = (phase_pull_in_ppb << 13) / 125;
current_ppm += scaled_ppm;
@@ -1699,9 +1730,12 @@ static int initialize_dco_operating_mode(struct idtcm_channel *channel)
/* PTP Hardware Clock interface */
-/*
+/**
* Maximum absolute value for write phase offset in picoseconds
*
+ * @channel: channel
+ * @delta_ns: delta in nanoseconds
+ *
* Destination signed register is 32-bit register in resolution of 50ps
*
* 0x7fffffff * 50 = 2147483647 * 50 = 107374182350
@@ -1958,8 +1992,7 @@ static int idtcm_enable(struct ptp_clock_info *ptp,
err = idtcm_perout_enable(channel, &rq->perout, true);
break;
case PTP_CLK_REQ_EXTTS:
- err = idtcm_enable_extts(channel, rq->extts.index,
- rq->extts.rsv[0], on);
+ err = idtcm_extts_enable(channel, rq, on);
break;
default:
break;
@@ -1982,13 +2015,6 @@ static int idtcm_enable_tod(struct idtcm_channel *channel)
u8 cfg;
int err;
- /* STEELAI-366 - Temporary workaround for ts2phc compatibility */
- if (0) {
- err = idtcm_output_mask_enable(channel, false);
- if (err)
- return err;
- }
-
/*
* Start the TOD clock ticking.
*/
@@ -2038,17 +2064,35 @@ static void idtcm_set_version_info(struct idtcm *idtcm)
product_id, hw_rev_id, config_select);
}
+static int idtcm_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
+ enum ptp_pin_function func, unsigned int chan)
+{
+ switch (func) {
+ case PTP_PF_NONE:
+ case PTP_PF_EXTTS:
+ break;
+ case PTP_PF_PEROUT:
+ case PTP_PF_PHYSYNC:
+ return -1;
+ }
+ return 0;
+}
+
+static struct ptp_pin_desc pin_config[MAX_TOD][MAX_REF_CLK];
+
static const struct ptp_clock_info idtcm_caps = {
.owner = THIS_MODULE,
.max_adj = 244000,
.n_per_out = 12,
.n_ext_ts = MAX_TOD,
+ .n_pins = MAX_REF_CLK,
.adjphase = &idtcm_adjphase,
.adjfine = &idtcm_adjfine,
.adjtime = &idtcm_adjtime,
.gettime64 = &idtcm_gettime,
.settime64 = &idtcm_settime,
.enable = &idtcm_enable,
+ .verify = &idtcm_verify_pin,
.do_aux_work = &idtcm_work_handler,
};
@@ -2057,12 +2101,14 @@ static const struct ptp_clock_info idtcm_caps_deprecated = {
.max_adj = 244000,
.n_per_out = 12,
.n_ext_ts = MAX_TOD,
+ .n_pins = MAX_REF_CLK,
.adjphase = &idtcm_adjphase,
.adjfine = &idtcm_adjfine,
.adjtime = &idtcm_adjtime_deprecated,
.gettime64 = &idtcm_gettime,
.settime64 = &idtcm_settime_deprecated,
.enable = &idtcm_enable,
+ .verify = &idtcm_verify_pin,
.do_aux_work = &idtcm_work_handler,
};
@@ -2173,9 +2219,10 @@ static u32 idtcm_get_dco_delay(struct idtcm_channel *channel)
if (n == 0)
n = 1;
- fodFreq = (u32)div_u64(m, n);
+ fodFreq = m / n;
+
if (fodFreq >= 500000000)
- return 18 * (u32)div_u64(NSEC_PER_SEC, fodFreq);
+ return 18 * (u64)NSEC_PER_SEC / fodFreq;
return 0;
}
@@ -2188,24 +2235,28 @@ static int configure_channel_tod(struct idtcm_channel *channel, u32 index)
switch (index) {
case 0:
channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_0);
+ channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_0);
channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_0);
channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_0);
channel->sync_src = SYNC_SOURCE_DPLL0_TOD_PPS;
break;
case 1:
channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_1);
+ channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_1);
channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_1);
channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_1);
channel->sync_src = SYNC_SOURCE_DPLL1_TOD_PPS;
break;
case 2:
channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_2);
+ channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_2);
channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_2);
channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_2);
channel->sync_src = SYNC_SOURCE_DPLL2_TOD_PPS;
break;
case 3:
channel->tod_read_primary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_PRIMARY_3);
+ channel->tod_read_secondary = IDTCM_FW_REG(fw_ver, V520, TOD_READ_SECONDARY_3);
channel->tod_write = IDTCM_FW_REG(fw_ver, V520, TOD_WRITE_3);
channel->tod_n = IDTCM_FW_REG(fw_ver, V520, TOD_3);
channel->sync_src = SYNC_SOURCE_DPLL3_TOD_PPS;
@@ -2221,6 +2272,7 @@ static int idtcm_enable_channel(struct idtcm *idtcm, u32 index)
{
struct idtcm_channel *channel;
int err;
+ int i;
if (!(index < MAX_TOD))
return -EINVAL;
@@ -2248,6 +2300,17 @@ static int idtcm_enable_channel(struct idtcm *idtcm, u32 index)
snprintf(channel->caps.name, sizeof(channel->caps.name),
"IDT CM TOD%u", index);
+ channel->caps.pin_config = pin_config[index];
+
+ for (i = 0; i < channel->caps.n_pins; ++i) {
+ struct ptp_pin_desc *ppd = &channel->caps.pin_config[i];
+
+ snprintf(ppd->name, sizeof(ppd->name), "input_ref%d", i);
+ ppd->index = i;
+ ppd->func = PTP_PF_NONE;
+ ppd->chan = index;
+ }
+
err = initialize_dco_operating_mode(channel);
if (err)
return err;
@@ -2302,26 +2365,40 @@ static int idtcm_enable_extts_channel(struct idtcm *idtcm, u32 index)
static void idtcm_extts_check(struct work_struct *work)
{
struct idtcm *idtcm = container_of(work, struct idtcm, extts_work.work);
- int err, i;
+ struct idtcm_channel *channel;
+ u8 mask;
+ int err;
+ int i;
if (idtcm->extts_mask == 0)
return;
mutex_lock(idtcm->lock);
+
for (i = 0; i < MAX_TOD; i++) {
- u8 mask = 1 << i;
+ mask = 1 << i;
+
+ if ((idtcm->extts_mask & mask) == 0)
+ continue;
- if (idtcm->extts_mask & mask) {
- err = idtcm_extts_check_channel(idtcm, i);
+ err = idtcm_extts_check_channel(idtcm, i);
+
+ if (err == 0) {
/* trigger clears itself, so clear the mask */
- if (err == 0)
+ if (idtcm->extts_single_shot) {
idtcm->extts_mask &= ~mask;
+ } else {
+ /* Re-arm */
+ channel = &idtcm->channel[i];
+ arm_tod_read_trig_sel_refclk(channel, channel->refn);
+ }
}
}
if (idtcm->extts_mask)
schedule_delayed_work(&idtcm->extts_work,
msecs_to_jiffies(EXTTS_PERIOD_MS));
+
mutex_unlock(idtcm->lock);
}
@@ -2342,6 +2419,11 @@ static void set_default_masks(struct idtcm *idtcm)
idtcm->tod_mask = DEFAULT_TOD_MASK;
idtcm->extts_mask = 0;
+ idtcm->channel[0].tod = 0;
+ idtcm->channel[1].tod = 1;
+ idtcm->channel[2].tod = 2;
+ idtcm->channel[3].tod = 3;
+
idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL;
idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL;
idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL;
@@ -2420,10 +2502,11 @@ static int idtcm_remove(struct platform_device *pdev)
{
struct idtcm *idtcm = platform_get_drvdata(pdev);
- ptp_clock_unregister_all(idtcm);
-
+ idtcm->extts_mask = 0;
cancel_delayed_work_sync(&idtcm->extts_work);
+ ptp_clock_unregister_all(idtcm);
+
return 0;
}
diff --git a/drivers/ptp/ptp_clockmatrix.h b/drivers/ptp/ptp_clockmatrix.h
index 0f3059a..4379650 100644
--- a/drivers/ptp/ptp_clockmatrix.h
+++ b/drivers/ptp/ptp_clockmatrix.h
@@ -10,11 +10,13 @@
#include <linux/ktime.h>
#include <linux/mfd/idt8a340_reg.h>
+#include <linux/ptp_clock.h>
#include <linux/regmap.h>
#define FW_FILENAME "idtcm.bin"
#define MAX_TOD (4)
#define MAX_PLL (8)
+#define MAX_REF_CLK (16)
#define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL)
@@ -90,6 +92,7 @@ struct idtcm_channel {
u16 dpll_ctrl_n;
u16 dpll_phase_pull_in;
u16 tod_read_primary;
+ u16 tod_read_secondary;
u16 tod_write;
u16 tod_n;
u16 hw_dpll_n;
@@ -105,6 +108,7 @@ struct idtcm_channel {
/* last input trigger for extts */
u8 refn;
u8 pll;
+ u8 tod;
u16 output_mask;
};
@@ -116,6 +120,7 @@ struct idtcm {
enum fw_version fw_ver;
/* Polls for external time stamps */
u8 extts_mask;
+ bool extts_single_shot;
struct delayed_work extts_work;
/* Remember the ptp channel to report extts */
struct idtcm_channel *event_channel[MAX_TOD];
diff --git a/include/linux/mfd/idt8a340_reg.h b/include/linux/mfd/idt8a340_reg.h
index a18c153..0c70608 100644
--- a/include/linux/mfd/idt8a340_reg.h
+++ b/include/linux/mfd/idt8a340_reg.h
@@ -407,7 +407,7 @@
#define TOD_READ_PRIMARY_0 0xcc40
#define TOD_READ_PRIMARY_0_V520 0xcc50
/* 8-bit subns, 32-bit ns, 48-bit seconds */
-#define TOD_READ_PRIMARY 0x0000
+#define TOD_READ_PRIMARY_BASE 0x0000
/* Counter increments after TOD write is completed */
#define TOD_READ_PRIMARY_COUNTER 0x000b
/* Read trigger configuration */
@@ -424,6 +424,16 @@
#define TOD_READ_SECONDARY_0 0xcc90
#define TOD_READ_SECONDARY_0_V520 0xcca0
+/* 8-bit subns, 32-bit ns, 48-bit seconds */
+#define TOD_READ_SECONDARY_BASE 0x0000
+/* Counter increments after TOD write is completed */
+#define TOD_READ_SECONDARY_COUNTER 0x000b
+/* Read trigger configuration */
+#define TOD_READ_SECONDARY_SEL_CFG_0 0x000c
+/* Read trigger selection */
+#define TOD_READ_SECONDARY_CMD 0x000e
+#define TOD_READ_SECONDARY_CMD_V520 0x000f
+
#define TOD_READ_SECONDARY_1 0xcca0
#define TOD_READ_SECONDARY_1_V520 0xccb0
#define TOD_READ_SECONDARY_2 0xccb0
--
2.7.4
Also removes PEROUT_ENABLE_OUTPUT_MASK
Signed-off-by: Min Li <[email protected]>
---
drivers/ptp/ptp_clockmatrix.c | 32 ++------------------------------
drivers/ptp/ptp_clockmatrix.h | 2 --
2 files changed, 2 insertions(+), 32 deletions(-)
diff --git a/drivers/ptp/ptp_clockmatrix.c b/drivers/ptp/ptp_clockmatrix.c
index 0e8e698..7f324fd 100644
--- a/drivers/ptp/ptp_clockmatrix.c
+++ b/drivers/ptp/ptp_clockmatrix.c
@@ -1363,43 +1363,15 @@ static int idtcm_output_enable(struct idtcm_channel *channel,
return idtcm_write(idtcm, (u16)base, OUT_CTRL_1, &val, sizeof(val));
}
-static int idtcm_output_mask_enable(struct idtcm_channel *channel,
- bool enable)
-{
- u16 mask;
- int err;
- u8 outn;
-
- mask = channel->output_mask;
- outn = 0;
-
- while (mask) {
- if (mask & 0x1) {
- err = idtcm_output_enable(channel, enable, outn);
- if (err)
- return err;
- }
-
- mask >>= 0x1;
- outn++;
- }
-
- return 0;
-}
-
static int idtcm_perout_enable(struct idtcm_channel *channel,
struct ptp_perout_request *perout,
bool enable)
{
struct idtcm *idtcm = channel->idtcm;
- unsigned int flags = perout->flags;
struct timespec64 ts = {0, 0};
int err;
- if (flags == PEROUT_ENABLE_OUTPUT_MASK)
- err = idtcm_output_mask_enable(channel, enable);
- else
- err = idtcm_output_enable(channel, enable, perout->index);
+ err = idtcm_output_enable(channel, enable, perout->index);
if (err) {
dev_err(idtcm->dev, "Unable to set output enable");
@@ -1903,7 +1875,7 @@ static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta)
int err;
if (channel->phase_pull_in == true)
- return 0;
+ return -EBUSY;
mutex_lock(idtcm->lock);
diff --git a/drivers/ptp/ptp_clockmatrix.h b/drivers/ptp/ptp_clockmatrix.h
index 4379650..bf1e49409 100644
--- a/drivers/ptp/ptp_clockmatrix.h
+++ b/drivers/ptp/ptp_clockmatrix.h
@@ -54,8 +54,6 @@
#define LOCK_TIMEOUT_MS (2000)
#define LOCK_POLL_INTERVAL_MS (10)
-#define PEROUT_ENABLE_OUTPUT_MASK (0xdeadbeef)
-
#define IDTCM_MAX_WRITE_COUNT (512)
#define PHASE_PULL_IN_MAX_PPB (144000)
--
2.7.4
Hi Min,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on net/master]
url: https://github.com/intel-lab-lkp/linux/commits/Min-Li/ptp-ptp_clockmatrix-Add-PTP_CLK_REQ_EXTTS-support/20220427-033506
base: https://git.kernel.org/pub/scm/linux/kernel/git/davem/net.git acb16b395c3f3d7502443e0c799c2b42df645642
config: mips-allmodconfig (https://download.01.org/0day-ci/archive/20220427/[email protected]/config)
compiler: mips-linux-gcc (GCC) 11.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/afadc4edd1bf64b40cb61b38dedf67354baeb147
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Min-Li/ptp-ptp_clockmatrix-Add-PTP_CLK_REQ_EXTTS-support/20220427-033506
git checkout afadc4edd1bf64b40cb61b38dedf67354baeb147
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.3.0 make.cross W=1 O=build_dir ARCH=mips SHELL=/bin/bash drivers/iio/imu/ drivers/ptp/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <[email protected]>
All warnings (new ones prefixed by >>):
>> drivers/ptp/ptp_clockmatrix.c:1734: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* Maximum absolute value for write phase offset in picoseconds
vim +1734 drivers/ptp/ptp_clockmatrix.c
3a6ba7dc779935 Vincent Cheng 2019-10-31 1732
afadc4edd1bf64 Min Li 2022-04-26 1733 /**
da9facf1c18252 Min Li 2021-09-13 @1734 * Maximum absolute value for write phase offset in picoseconds
da9facf1c18252 Min Li 2021-09-13 1735 *
afadc4edd1bf64 Min Li 2022-04-26 1736 * @channel: channel
afadc4edd1bf64 Min Li 2022-04-26 1737 * @delta_ns: delta in nanoseconds
afadc4edd1bf64 Min Li 2022-04-26 1738 *
425d2b1c563826 Vincent Cheng 2020-05-01 1739 * Destination signed register is 32-bit register in resolution of 50ps
425d2b1c563826 Vincent Cheng 2020-05-01 1740 *
425d2b1c563826 Vincent Cheng 2020-05-01 1741 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350
425d2b1c563826 Vincent Cheng 2020-05-01 1742 */
425d2b1c563826 Vincent Cheng 2020-05-01 1743 static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)
425d2b1c563826 Vincent Cheng 2020-05-01 1744 {
425d2b1c563826 Vincent Cheng 2020-05-01 1745 struct idtcm *idtcm = channel->idtcm;
425d2b1c563826 Vincent Cheng 2020-05-01 1746 int err;
425d2b1c563826 Vincent Cheng 2020-05-01 1747 u8 i;
425d2b1c563826 Vincent Cheng 2020-05-01 1748 u8 buf[4] = {0};
425d2b1c563826 Vincent Cheng 2020-05-01 1749 s32 phase_50ps;
425d2b1c563826 Vincent Cheng 2020-05-01 1750 s64 offset_ps;
425d2b1c563826 Vincent Cheng 2020-05-01 1751
da9facf1c18252 Min Li 2021-09-13 1752 if (channel->mode != PTP_PLL_MODE_WRITE_PHASE) {
da9facf1c18252 Min Li 2021-09-13 1753 err = channel->configure_write_phase(channel);
425d2b1c563826 Vincent Cheng 2020-05-01 1754 if (err)
425d2b1c563826 Vincent Cheng 2020-05-01 1755 return err;
425d2b1c563826 Vincent Cheng 2020-05-01 1756 }
425d2b1c563826 Vincent Cheng 2020-05-01 1757
425d2b1c563826 Vincent Cheng 2020-05-01 1758 offset_ps = (s64)delta_ns * 1000;
425d2b1c563826 Vincent Cheng 2020-05-01 1759
425d2b1c563826 Vincent Cheng 2020-05-01 1760 /*
425d2b1c563826 Vincent Cheng 2020-05-01 1761 * Check for 32-bit signed max * 50:
425d2b1c563826 Vincent Cheng 2020-05-01 1762 *
425d2b1c563826 Vincent Cheng 2020-05-01 1763 * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350
425d2b1c563826 Vincent Cheng 2020-05-01 1764 */
425d2b1c563826 Vincent Cheng 2020-05-01 1765 if (offset_ps > MAX_ABS_WRITE_PHASE_PICOSECONDS)
425d2b1c563826 Vincent Cheng 2020-05-01 1766 offset_ps = MAX_ABS_WRITE_PHASE_PICOSECONDS;
425d2b1c563826 Vincent Cheng 2020-05-01 1767 else if (offset_ps < -MAX_ABS_WRITE_PHASE_PICOSECONDS)
425d2b1c563826 Vincent Cheng 2020-05-01 1768 offset_ps = -MAX_ABS_WRITE_PHASE_PICOSECONDS;
425d2b1c563826 Vincent Cheng 2020-05-01 1769
7260d1c8fd8667 Min Li 2020-12-08 1770 phase_50ps = div_s64(offset_ps, 50);
425d2b1c563826 Vincent Cheng 2020-05-01 1771
425d2b1c563826 Vincent Cheng 2020-05-01 1772 for (i = 0; i < 4; i++) {
425d2b1c563826 Vincent Cheng 2020-05-01 1773 buf[i] = phase_50ps & 0xff;
425d2b1c563826 Vincent Cheng 2020-05-01 1774 phase_50ps >>= 8;
425d2b1c563826 Vincent Cheng 2020-05-01 1775 }
425d2b1c563826 Vincent Cheng 2020-05-01 1776
425d2b1c563826 Vincent Cheng 2020-05-01 1777 err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE,
425d2b1c563826 Vincent Cheng 2020-05-01 1778 buf, sizeof(buf));
425d2b1c563826 Vincent Cheng 2020-05-01 1779
425d2b1c563826 Vincent Cheng 2020-05-01 1780 return err;
425d2b1c563826 Vincent Cheng 2020-05-01 1781 }
425d2b1c563826 Vincent Cheng 2020-05-01 1782
--
0-DAY CI Kernel Test Service
https://01.org/lkp
Hi Min,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on net/master]
url: https://github.com/intel-lab-lkp/linux/commits/Min-Li/ptp-ptp_clockmatrix-Add-PTP_CLK_REQ_EXTTS-support/20220427-033506
base: https://git.kernel.org/pub/scm/linux/kernel/git/davem/net.git acb16b395c3f3d7502443e0c799c2b42df645642
config: i386-randconfig-a012-20220425 (https://download.01.org/0day-ci/archive/20220427/[email protected]/config)
compiler: gcc-11 (Debian 11.2.0-20) 11.2.0
reproduce (this is a W=1 build):
# https://github.com/intel-lab-lkp/linux/commit/afadc4edd1bf64b40cb61b38dedf67354baeb147
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Min-Li/ptp-ptp_clockmatrix-Add-PTP_CLK_REQ_EXTTS-support/20220427-033506
git checkout afadc4edd1bf64b40cb61b38dedf67354baeb147
# save the config file
mkdir build_dir && cp config build_dir/.config
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <[email protected]>
All errors (new ones prefixed by >>):
ld: drivers/ptp/ptp_clockmatrix.o: in function `idtcm_get_dco_delay':
>> drivers/ptp/ptp_clockmatrix.c:2222: undefined reference to `__udivdi3'
>> ld: drivers/ptp/ptp_clockmatrix.c:2225: undefined reference to `__udivdi3'
vim +2222 drivers/ptp/ptp_clockmatrix.c
2191
2192 /*
2193 * Compensate for the PTP DCO input-to-output delay.
2194 * This delay is 18 FOD cycles.
2195 */
2196 static u32 idtcm_get_dco_delay(struct idtcm_channel *channel)
2197 {
2198 struct idtcm *idtcm = channel->idtcm;
2199 u8 mbuf[8] = {0};
2200 u8 nbuf[2] = {0};
2201 u32 fodFreq;
2202 int err;
2203 u64 m;
2204 u16 n;
2205
2206 err = idtcm_read(idtcm, channel->dpll_ctrl_n,
2207 DPLL_CTRL_DPLL_FOD_FREQ, mbuf, 6);
2208 if (err)
2209 return 0;
2210
2211 err = idtcm_read(idtcm, channel->dpll_ctrl_n,
2212 DPLL_CTRL_DPLL_FOD_FREQ + 6, nbuf, 2);
2213 if (err)
2214 return 0;
2215
2216 m = get_unaligned_le64(mbuf);
2217 n = get_unaligned_le16(nbuf);
2218
2219 if (n == 0)
2220 n = 1;
2221
> 2222 fodFreq = m / n;
2223
2224 if (fodFreq >= 500000000)
> 2225 return 18 * (u64)NSEC_PER_SEC / fodFreq;
2226
2227 return 0;
2228 }
2229
--
0-DAY CI Kernel Test Service
https://01.org/lkp
Hi Min,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on net/master]
url: https://github.com/intel-lab-lkp/linux/commits/Min-Li/ptp-ptp_clockmatrix-Add-PTP_CLK_REQ_EXTTS-support/20220427-033506
base: https://git.kernel.org/pub/scm/linux/kernel/git/davem/net.git acb16b395c3f3d7502443e0c799c2b42df645642
config: i386-randconfig-a013-20220425 (https://download.01.org/0day-ci/archive/20220427/[email protected]/config)
compiler: gcc-11 (Debian 11.2.0-20) 11.2.0
reproduce (this is a W=1 build):
# https://github.com/intel-lab-lkp/linux/commit/afadc4edd1bf64b40cb61b38dedf67354baeb147
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Min-Li/ptp-ptp_clockmatrix-Add-PTP_CLK_REQ_EXTTS-support/20220427-033506
git checkout afadc4edd1bf64b40cb61b38dedf67354baeb147
# save the config file
mkdir build_dir && cp config build_dir/.config
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <[email protected]>
All errors (new ones prefixed by >>):
ld: drivers/ptp/ptp_clockmatrix.o: in function `idtcm_enable_channel':
>> ptp_clockmatrix.c:(.text+0x2394): undefined reference to `__udivdi3'
>> ld: ptp_clockmatrix.c:(.text+0x23b0): undefined reference to `__udivdi3'
--
0-DAY CI Kernel Test Service
https://01.org/lkp