LinuxLists.cc - [V2] tty: serial: qcom-geni-serial: Fix get_clk_div_rate() which otherwise could return a sub-optimal clock rate.

2022-06-29 10:26:20

Subject: [V2] tty: serial: qcom-geni-serial: Fix get_clk_div_rate() which otherwise could return a sub-optimal clock rate.

In the logic around call to clk_round_rate(), for some corner conditions,
get_clk_div_rate() could return an sub-optimal clock rate. Also, if an
exact clock rate was not found lowest clock was being returned.

Search for suitable clock rate in 2 steps
a) exact match or within 2% tolerance
b) within 5% tolerance
This also takes care of corner conditions.

Reported-by: kernel test robot <[email protected]>
Fixes: c2194bc999d4 ("tty: serial: qcom-geni-serial: Remove uart frequency table. Instead, find suitable frequency with call to clk_round_rate")
Signed-off-by: Vijaya Krishna Nivarthi <[email protected]>
---
v2: removed minor optimisations to make more readable
v1: intial patch contained slightly complicated logic
---
drivers/tty/serial/qcom_geni_serial.c | 122 +++++++++++++++++++++++++---------
1 file changed, 90 insertions(+), 32 deletions(-)

diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c
index 2e23b65..d0696d1 100644
--- a/drivers/tty/serial/qcom_geni_serial.c
+++ b/drivers/tty/serial/qcom_geni_serial.c
@@ -943,52 +943,111 @@ static int qcom_geni_serial_startup(struct uart_port *uport)
return 0;
}

-static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud,
- unsigned int sampling_rate, unsigned int *clk_div)
+static unsigned long find_clk_rate_in_tol(struct clk *clk, unsigned int desired_clk,
+ unsigned int *clk_div, unsigned int percent_tol, bool exact_match)
{
+ unsigned long freq;
+ unsigned long div, maxdiv, new_div;
+ u64 mult;
unsigned long ser_clk;
- unsigned long desired_clk;
- unsigned long freq, prev;
- unsigned long div, maxdiv;
- int64_t mult;
-
- desired_clk = baud * sampling_rate;
- if (!desired_clk) {
- pr_err("%s: Invalid frequency\n", __func__);
- return 0;
- }
+ unsigned long test_freq, offset, new_freq;

+ ser_clk = 0;
maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT;
- prev = 0;
+ div = 1;

- for (div = 1; div <= maxdiv; div++) {
- mult = div * desired_clk;
- if (mult > ULONG_MAX)
+ while (div <= maxdiv) {
+ mult = (u64)div * desired_clk;
+ if (mult != (unsigned long)mult)
break;

- freq = clk_round_rate(clk, (unsigned long)mult);
+ /*
+ * Loop requesting a freq within tolerance and possibly exact freq.
+ *
+ * We'll keep track of the lowest freq inexact match we found
+ * but always try to find a perfect match. NOTE: this algorithm
+ * could miss a slightly better freq if there's more than one
+ * freq between (freq - offset) and (freq) but (freq) can't be made
+ * exactly, but that's OK.
+ *
+ * This absolutely relies on the fact that the Qualcomm clock
+ * driver always rounds up.
+ * We make use of exact_match as an I/O param.
+ */
+
+ /* look only for exact match if within tolerance is already found */
+ if (ser_clk)
+ offset = 0;
+ else
+ offset = div_u64(mult * percent_tol, 100);
+
+ test_freq = mult - offset;
+ freq = clk_round_rate(clk, test_freq);
+
+ /*
+ * A dead-on freq is an insta-win
+ */
if (!(freq % desired_clk)) {
ser_clk = freq;
- break;
+ *clk_div = freq / desired_clk;
+ return ser_clk;
}

- if (!prev)
- ser_clk = freq;
- else if (prev == freq)
- break;
+ if (!ser_clk) {
+ new_div = DIV_ROUND_CLOSEST(freq, desired_clk);
+ new_freq = new_div * desired_clk;
+ offset = (new_freq * percent_tol) / 100;
+
+ if (new_freq - offset <= freq && freq <= new_freq + offset) {
+ /* Save the first (lowest freq) within tolerance */
+ ser_clk = freq;
+ *clk_div = new_div;
+ /* no more search for exact match required in 2nd run */
+ if (!exact_match)
+ break;
+ }
+ }

- prev = freq;
+ div = freq / desired_clk + 1;
+
+ /*
+ * Only time clock framework doesn't round up is if
+ * we're past the max clock rate. We're done searching
+ * if that's the case.
+ */
+ if (freq < test_freq)
+ break;
}

- if (!ser_clk) {
- pr_err("%s: Can't find matching DFS entry for baud %d\n",
- __func__, baud);
- return ser_clk;
+ return ser_clk;
+}
+
+static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud,
+ unsigned int sampling_rate, unsigned int *clk_div)
+{
+ unsigned long ser_clk;
+ unsigned long desired_clk;
+
+ desired_clk = baud * sampling_rate;
+ if (!desired_clk) {
+ pr_err("%s: Invalid frequency\n", __func__);
+ return 0;
}

- *clk_div = ser_clk / desired_clk;
- if (!(*clk_div))
- *clk_div = 1;
+ ser_clk = 0;
+ /*
+ * try to find exact clock rate or within 2% tolerance,
+ * then within 5% tolerance
+ */
+ ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 2, true);
+ if (!ser_clk)
+ ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 5, false);
+
+ if (!ser_clk)
+ pr_err("Couldn't find suitable clock rate for %d\n", desired_clk);
+ else
+ pr_debug("desired_clk-%d, ser_clk-%d, clk_div-%d\n",
+ desired_clk, ser_clk, *clk_div);

return ser_clk;
}
@@ -1021,8 +1080,7 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport,
if (ver >= QUP_SE_VERSION_2_5)
sampling_rate /= 2;

- clk_rate = get_clk_div_rate(port->se.clk, baud,
- sampling_rate, &clk_div);
+ clk_rate = get_clk_div_rate(port->se.clk, baud, sampling_rate, &clk_div);
if (!clk_rate)
goto out_restart_rx;

--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by the Linux Foundation.

2022-06-29 13:47:07

Hi,

On Wed, Jul 6, 2022 at 10:44 AM Vijaya Krishna Nivarthi
<[email protected]> wrote:
>
> Hi,
>
>
> On 7/6/2022 8:56 PM, Doug Anderson wrote:
> > Hi,
> >
> > On Mon, Jul 4, 2022 at 11:57 AM Vijaya Krishna Nivarthi (Temp)
> > <[email protected]> wrote:
> >> Hi,
> >>
> >>
> >>> -----Original Message-----
> >>> From: Doug Anderson <[email protected]>
> >>> Sent: Friday, July 1, 2022 8:38 PM
> >>> To: Vijaya Krishna Nivarthi (Temp) (QUIC) <[email protected]>
> >>> Cc: Andy Gross <[email protected]>; [email protected]; Konrad
> >>> Dybcio <[email protected]>; Greg Kroah-Hartman
> >>> <[email protected]>; Jiri Slaby <[email protected]>; linux-arm-
> >>> msm <[email protected]>; [email protected]; LKML
> >>> <[email protected]>; Mukesh Savaliya (QUIC)
> >>> <[email protected]>; Matthias Kaehlcke <[email protected]>;
> >>> Stephen Boyd <[email protected]>
> >>> Subject: Re: [V2] tty: serial: qcom-geni-serial: Fix get_clk_div_rate() which
> >>> otherwise could return a sub-optimal clock rate.
> >>>
> >>> WARNING: This email originated from outside of Qualcomm. Please be wary
> >>> of any links or attachments, and do not enable macros.
> >>>
> >>> Hi,
> >>>
> >>> On Fri, Jul 1, 2022 at 4:04 AM Vijaya Krishna Nivarthi (Temp) (QUIC)
> >>> <[email protected]> wrote:
> >>>> Hi,
> >>>>
> >>>>
> >>>>> -----Original Message-----
> >>>>> From: Doug Anderson <[email protected]>
> >>>>> Sent: Thursday, June 30, 2022 4:45 AM
> >>>>> To: Vijaya Krishna Nivarthi (Temp) (QUIC)
> >>>>> <[email protected]>
> >>>>> Cc: Andy Gross <[email protected]>; [email protected];
> >>>>> Konrad Dybcio <[email protected]>; Greg Kroah-Hartman
> >>>>> <[email protected]>; Jiri Slaby <[email protected]>;
> >>>>> linux-arm- msm <[email protected]>;
> >>>>> [email protected]; LKML <[email protected]>;
> >>>>> Mukesh Savaliya (QUIC) <[email protected]>; Matthias
> >>>>> Kaehlcke <[email protected]>; Stephen Boyd
> >>> <[email protected]>
> >>>>> Subject: Re: [V2] tty: serial: qcom-geni-serial: Fix
> >>>>> get_clk_div_rate() which otherwise could return a sub-optimal clock rate.
> >>>>>
> >>>>>
> >>>>>
> >>>>>> + /* Save the first (lowest freq) within tolerance */
> >>>>>> + ser_clk = freq;
> >>>>>> + *clk_div = new_div;
> >>>>>> + /* no more search for exact match required in 2nd run
> >>> */
> >>>>>> + if (!exact_match)
> >>>>>> + break;
> >>>>>> + }
> >>>>>> + }
> >>>>>>
> >>>>>> - prev = freq;
> >>>>>> + div = freq / desired_clk + 1;
> >>>>> Can't you infinite loop now?
> >>>>>
> >>>>> Start with:
> >>>>>
> >>>>> desired_clk = 10000
> >>>>> div = 1
> >>>>> percent_tol = 2
> >>>>>
> >>>>>
> >>>>> Now:
> >>>>>
> >>>>> mult = 10000
> >>>>> offset = 200
> >>>>> test_freq = 9800
> >>>>> freq = 9800
> >>>>> div = 9800 / 10000 + 1 = 0 + 1 = 1
> >>>>>
> >>>>> ...and then you'll loop again with "div = 1", won't you? ...or did I
> >>>>> get something wrong in my analysis? This is the reason my proposed
> >>>>> algorithm had two loops.
> >>>>>
> >>>>>
> >>>> I went back to your proposed algorithm and made couple of simple
> >>> changes, and it seemed like what we need.
> >>>> a) look only for exact match once a clock rate within tolerance is
> >>>> found
> >>>> b) swap test_freq and freq at end of while loops to make it run as
> >>>> desired
> >>>>
> >>>>
> >>>> maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT;
> >>>> div = 1;
> >>>>
> >>>> while (div < maxdiv) {
> >>>> mult = (unsigned long long)div * desired_clk;
> >>>> if (mult != (unsigned long)mult)
> >>>> break;
> >>>>
> >>>> if (ser_clk)
> >>>> offset = 0;
> >>>> ===================a=====================
> >>>> else
> >>>> offset = div_u64(mult * percent_tol, 100);
> >>>>
> >>>> /*
> >>>> * Loop requesting (freq - 2%) and possibly (freq).
> >>>> *
> >>>> * We'll keep track of the lowest freq inexact match we found
> >>>> * but always try to find a perfect match. NOTE: this algorithm
> >>>> * could miss a slightly better freq if there's more than one
> >>>> * freq between (freq - 2%) and (freq) but (freq) can't be made
> >>>> * exactly, but that's OK.
> >>>> *
> >>>> * This absolutely relies on the fact that the Qualcomm clock
> >>>> * driver always rounds up.
> >>>> */
> >>>> test_freq = mult - offset;
> >>>> while (test_freq <= mult) {
> >>>> freq = clk_round_rate(clk, test_freq);
> >>>>
> >>>> /*
> >>>> * A dead-on freq is an insta-win. This implicitly
> >>>> * handles when "freq == mult"
> >>>> */
> >>>> if (!(freq % desired_clk)) {
> >>>> *clk_div = freq / desired_clk;
> >>>> return freq;
> >>>> }
> >>>>
> >>>> /*
> >>>> * Only time clock framework doesn't round up is if
> >>>> * we're past the max clock rate. We're done searching
> >>>> * if that's the case.
> >>>> */
> >>>> if (freq < test_freq)
> >>>> return ser_clk;
> >>>>
> >>>> /* Save the first (lowest freq) within tolerance */
> >>>> if (!ser_clk && freq <= mult + offset) {
> >>>> ser_clk = freq;
> >>>> *clk_div = div;
> >>>> }
> >>>>
> >>>> /*
> >>>> * If we already rounded up past mult then this will
> >>>> * cause the loop to exit. If not then this will run
> >>>> * the loop a second time with exactly mult.
> >>>> */
> >>>> test_freq = max(test_freq + 1, mult);
> >>>> ====b====
> >>>> }
> >>>>
> >>>> /*
> >>>> * freq will always be bigger than mult by at least 1.
> >>>> * That means we can get the next divider with a DIV_ROUND_UP.
> >>>> * This has the advantage of skipping by a whole bunch of divs
> >>>> * If the clock framework already bypassed them.
> >>>> */
> >>>> div = DIV_ROUND_UP(freq, desired_clk);
> >>>> ===b==
> >>>> }
> >>>>
> >>>>
> >>>> Will also drop exact_match now.
> >>>>
> >>>> Will upload v3 after testing.
> >>> The more I've been thinking about it, the more I wonder if we even need the
> >>> special case of looking for an exact match at all. It feels like we should choose
> >>> one: we either look for the best match or we look for the one with the
> >>> lowest clock source rate. The weird half-half approach that we have right
> >>> now feels like over-engineering and complicates things.
> >>>
> >>> How about this (again, only lightly tested). Worst case if we _truly_ need a
> >>> close-to-exact match we could pass a tolerance of 0 in and we'd get
> >>> something that's nearly exact, though I'm not suggesting we actually do that.
> >>> If we think 2% is good enough then we should just accept the first (and
> >>> lowest clock rate) 2% match we find.
> >>>
> >>> abs_tol = div_u64((u64)desired_clk * percent_tol, 100);
> >>> maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT;
> >>> div = 1;
> >>> while (div <= maxdiv) {
> >>> mult = (u64)div * desired_clk;
> >>> if (mult != (unsigned long)mult)
> >>> break;
> >>>
> >>> offset = div * abs_tol;
> >>> freq = clk_round_rate(clk, mult - offset);
> >>>
> >>> /* Can only get lower if we're done */
> >>> if (freq < mult - offset)
> >>> break;
> >>>
> >>> /*
> >>> * Re-calculate div in case rounding skipped rates but we
> >>> * ended up at a good one, then check for a match.
> >>> */
> >>> div = DIV_ROUND_CLOSEST(freq, desired_clk);
> >>> achieved = DIV_ROUND_CLOSEST(freq, div);
> >>> if (achieved <= desired_clk + abs_tol &&
> >>> achieved >= desired_clk - abs_tol) {
> >>> *clk_div = div;
> >>> return freq;
> >>> }
> >>>
> >>> /*
> >>> * Always increase div by at least one, but we'll go more than
> >>> * one if clk_round_rate() gave us something higher.
> >>> */
> >>> div = DIV_ROUND_UP(max(freq, (unsigned long)mult) + 1, desired_clk);
> >> Wouldn’t DIV_ROUND_UP(freq, desired_clk) suffice here?
> >> freq >= mult-offset, else we would have hit break.
> > No. As you say, freq >= "mult-offset". That means that freq could be
> > == "mult-offset", right? If offset > 0 then freq could be < mult. Then
> > your DIV_ROUND_UP() would just take you right back to where you
> > started the loop with and you'd end up with an infinite loop, wouldn't
> > you?
> >
> Probably No.
>
> ( (freq >= mult-offset) && (freq <= mult) ) =>
>
> ( (freq >= mult-offset) && (freq <= mult+offset) )
>
> would mean that
>
> div = DIV_ROUND_CLOSEST(freq, desired_clk);
> evaluates to original div and we are within tolerance and hence we can return and hence don't even reach DIV_ROUND_UP?
>
> Please note that freq can skip any multiples and land up anywhere.
>
> As long as it has not gone beyond clock rate table, either it lands
> within tolerance of nearest multiple of desired_clk (in which case we
> return)
>
> OR
>
> We move on to next div = (freq/desired_clk + 1)

Ah, you are correct. So just:

div = DIV_ROUND_UP(freq, desired_clk);

...because freq _has_ to be greater than mult. If it was < "mult -
offset" we would have ended the loop. If it was between "mult -
offset" and "mult + offset" (inclusive) then we would have success. So
freq must be > "mult + offset" at the end of the loop.

-Doug

2022-07-07 19:44:24

by Vijaya Krishna Nivarthi

[permalink] [raw]

Subject: Re: [V2] tty: serial: qcom-geni-serial: Fix get_clk_div_rate() which otherwise could return a sub-optimal clock rate.

On 7/6/2022 11:51 PM, Doug Anderson wrote:
> Hi,
>
> On Wed, Jul 6, 2022 at 10:44 AM Vijaya Krishna Nivarthi
> <[email protected]> wrote:
>> Hi,
>>
>>
>> On 7/6/2022 8:56 PM, Doug Anderson wrote:
>>> Hi,
>>>
>>> On Mon, Jul 4, 2022 at 11:57 AM Vijaya Krishna Nivarthi (Temp)
>>> <[email protected]> wrote:
>>>> Hi,
>>>>
>>>>
>>>>> -----Original Message-----
>>>>> From: Doug Anderson <[email protected]>
>>>>> Sent: Friday, July 1, 2022 8:38 PM
>>>>> To: Vijaya Krishna Nivarthi (Temp) (QUIC) <[email protected]>
>>>>> Cc: Andy Gross <[email protected]>; [email protected]; Konrad
>>>>> Dybcio <[email protected]>; Greg Kroah-Hartman
>>>>> <[email protected]>; Jiri Slaby <[email protected]>; linux-arm-
>>>>> msm <[email protected]>; [email protected]; LKML
>>>>> <[email protected]>; Mukesh Savaliya (QUIC)
>>>>> <[email protected]>; Matthias Kaehlcke <[email protected]>;
>>>>> Stephen Boyd <[email protected]>
>>>>> Subject: Re: [V2] tty: serial: qcom-geni-serial: Fix get_clk_div_rate() which
>>>>> otherwise could return a sub-optimal clock rate.
>>>>>
>>>>> WARNING: This email originated from outside of Qualcomm. Please be wary
>>>>> of any links or attachments, and do not enable macros.
>>>>>
>>>>> Hi,
>>>>>
>>>>> On Fri, Jul 1, 2022 at 4:04 AM Vijaya Krishna Nivarthi (Temp) (QUIC)
>>>>> <[email protected]> wrote:
>>>>>
> Ah, you are correct. So just:
>
> div = DIV_ROUND_UP(freq, desired_clk);
>
> ...because freq _has_ to be greater than mult. If it was < "mult -
> offset" we would have ended the loop. If it was between "mult -
> offset" and "mult + offset" (inclusive) then we would have success. So
> freq must be > "mult + offset" at the end of the loop.
>
> -Doug

Thank you, uploaded V3.