Here's a bunch of fixes for PHY related DT issues found while amending
the current QMP PHY schema:
https://lore.kernel.org/r/[email protected]
Included are also some cleanups of the MS8996 PCIe PHY node which make
the node match the new binding example.
Note that none of these depend on any additions to the binding (e.g. the
deprecation of the lane suffix) even if some of issues would not be
found when validating against the current schema.
Johan
Johan Hovold (14):
arm64: dts: qcom: sc7280: drop PCIe PHY clock index
arm64: dts: qcom: sm8250: add missing PCIe PHY clock-cells
arm64: dts: qcom: ipq6018: drop USB PHY clock index
arm64: dts: qcom: ipq8074: drop USB PHY clock index
arm64: dts: qcom: msm8996: drop USB PHY clock index
arm64: dts: qcom: msm8998: drop USB PHY clock index
arm64: dts: qcom: sm8350: drop USB PHY clock index
arm64: dts: qcom: sm8450: drop USB PHY clock index
arm64: dts: qcom: sc8280xp: drop UFS PHY clock-cells
arm64: dts: qcom: sm8250: drop UFS PHY clock-cells
arm64: dts: qcom: sm8450: drop UFS PHY clock-cells
arm64: dts: qcom: msm8996: add missing PCIe PHY clock-cells
arm64: dts: qcom: msm8996: use non-empty ranges for PCIe PHYs
arm64: dts: qcom: msm8996: clean up PCIe PHY node
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +-
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 +-
arch/arm64/boot/dts/qcom/msm8996.dtsi | 53 +++++++++++++++-----------
arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 +-
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 -
arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 +++
arch/arm64/boot/dts/qcom/sm8350.dtsi | 5 +--
arch/arm64/boot/dts/qcom/sm8450.dtsi | 3 +-
9 files changed, 46 insertions(+), 35 deletions(-)
--
2.35.1
The QMP USB PHY provides a single clock so drop the redundant clock
index.
Signed-off-by: Johan Hovold <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 758c45bbbe78..2511e70d66ef 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -2080,7 +2080,7 @@ usb1_ssphy: phy@c010200 {
<0xc010600 0x128>,
<0xc010800 0x200>;
#phy-cells = <0>;
- #clock-cells = <1>;
+ #clock-cells = <0>;
clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
--
2.35.1
Add the missing '#clock-cells' properties to the PCIe QMP PHY nodes.
Signed-off-by: Johan Hovold <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 53e0b57c13e4..f45a6cca397f 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -1892,6 +1892,8 @@ pcie0_lane: phy@1c06200 {
clock-names = "pipe0";
#phy-cells = <0>;
+
+ #clock-cells = <0>;
clock-output-names = "pcie_0_pipe_clk";
};
};
@@ -1998,6 +2000,8 @@ pcie1_lane: phy@1c0e200 {
clock-names = "pipe0";
#phy-cells = <0>;
+
+ #clock-cells = <0>;
clock-output-names = "pcie_1_pipe_clk";
};
};
@@ -2104,6 +2108,8 @@ pcie2_lane: phy@1c16200 {
clock-names = "pipe0";
#phy-cells = <0>;
+
+ #clock-cells = <0>;
clock-output-names = "pcie_2_pipe_clk";
};
};
--
2.35.1
The QMP UFS PHY provides more than one symbol clock and would need an
index to differentiate the clocks, but none of this is described by the
binding currently.
Drop the incorrect '#clock-cells' property for now.
Signed-off-by: Johan Hovold <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index c06c95c0c557..e91766e4c6f7 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -3092,7 +3092,6 @@ ufs_mem_phy_lanes: phy@1d87400 {
<0 0x01d87800 0 0x108>,
<0 0x01d87a00 0 0x1e0>;
#phy-cells = <0>;
- #clock-cells = <0>;
};
};
--
2.35.1
Clean up the PCIe PHY nodes by using a non-empty ranges property.
Signed-off-by: Johan Hovold <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index b670d0412760..16869bb7d625 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -590,7 +590,7 @@ pcie_phy: phy@34000 {
reg = <0x00034000 0x488>;
#address-cells = <1>;
#size-cells = <1>;
- ranges;
+ ranges = <0x0 0x00034000 0x4000>;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
@@ -603,10 +603,10 @@ pcie_phy: phy@34000 {
reset-names = "phy", "common", "cfg";
status = "disabled";
- pciephy_0: phy@35000 {
- reg = <0x00035000 0x130>,
- <0x00035200 0x200>,
- <0x00035400 0x1dc>;
+ pciephy_0: phy@1000 {
+ reg = <0x1000 0x130>,
+ <0x1200 0x200>,
+ <0x1400 0x1dc>;
#phy-cells = <0>;
#clock-cells = <0>;
@@ -617,10 +617,10 @@ pciephy_0: phy@35000 {
reset-names = "lane0";
};
- pciephy_1: phy@36000 {
- reg = <0x00036000 0x130>,
- <0x00036200 0x200>,
- <0x00036400 0x1dc>;
+ pciephy_1: phy@2000 {
+ reg = <0x2000 0x130>,
+ <0x2200 0x200>,
+ <0x2400 0x1dc>;
#phy-cells = <0>;
#clock-cells = <0>;
@@ -631,10 +631,10 @@ pciephy_1: phy@36000 {
reset-names = "lane1";
};
- pciephy_2: phy@37000 {
- reg = <0x00037000 0x130>,
- <0x00037200 0x200>,
- <0x00037400 0x1dc>;
+ pciephy_2: phy@3000 {
+ reg = <0x3000 0x130>,
+ <0x3200 0x200>,
+ <0x3400 0x1dc>;
#phy-cells = <0>;
#clock-cells = <0>;
--
2.35.1
The QMP USB PHY provides a single clock so drop the redundant clock
index.
Signed-off-by: Johan Hovold <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 743cba9b683c..7e399d739cd9 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2381,7 +2381,7 @@ usb_1_ssphy: phy@88e9200 {
<0 0x088e9800 0 0x200>,
<0 0x088e9a00 0 0x100>;
#phy-cells = <0>;
- #clock-cells = <1>;
+ #clock-cells = <0>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
@@ -2411,7 +2411,7 @@ usb_2_ssphy: phy@88ebe00 {
<0 0x088ec000 0 0x200>,
<0 0x088eb200 0 0x1100>;
#phy-cells = <0>;
- #clock-cells = <1>;
+ #clock-cells = <0>;
clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_uni_phy_pipe_clk_src";
--
2.35.1
Clean up the PCIe PHY node by renaming the wrapper node and grouping the
child node properties.
Signed-off-by: Johan Hovold <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 27 +++++++++++++++++----------
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 16869bb7d625..98a4cad89e9f 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -585,7 +585,7 @@ soc: soc {
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
- pcie_phy: phy@34000 {
+ pcie_phy: phy-wrapper@34000 {
compatible = "qcom,msm8996-qmp-pcie-phy";
reg = <0x00034000 0x488>;
#address-cells = <1>;
@@ -601,48 +601,55 @@ pcie_phy: phy@34000 {
<&gcc GCC_PCIE_PHY_COM_BCR>,
<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
reset-names = "phy", "common", "cfg";
+
status = "disabled";
pciephy_0: phy@1000 {
reg = <0x1000 0x130>,
<0x1200 0x200>,
<0x1400 0x1dc>;
- #phy-cells = <0>;
- #clock-cells = <0>;
- clock-output-names = "pcie_0_pipe_clk_src";
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "pipe0";
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "lane0";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_0_pipe_clk_src";
+
+ #phy-cells = <0>;
};
pciephy_1: phy@2000 {
reg = <0x2000 0x130>,
<0x2200 0x200>,
<0x2400 0x1dc>;
- #phy-cells = <0>;
- #clock-cells = <0>;
- clock-output-names = "pcie_1_pipe_clk_src";
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
clock-names = "pipe1";
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "lane1";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_1_pipe_clk_src";
+
+ #phy-cells = <0>;
};
pciephy_2: phy@3000 {
reg = <0x3000 0x130>,
<0x3200 0x200>,
<0x3400 0x1dc>;
- #phy-cells = <0>;
- #clock-cells = <0>;
- clock-output-names = "pcie_2_pipe_clk_src";
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
clock-names = "pipe2";
resets = <&gcc GCC_PCIE_2_PHY_BCR>;
reset-names = "lane2";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_2_pipe_clk_src";
+
+ #phy-cells = <0>;
};
};
--
2.35.1
The QMP UFS PHY provides more than one symbol clock and would need an
index to differentiate the clocks, but none of this is described by the
binding currently.
Drop the incorrect '#clock-cells' property for now.
Signed-off-by: Johan Hovold <[email protected]>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 345a19a6e874..ce4df4e814fe 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -1447,7 +1447,6 @@ ufs_mem_phy_lanes: phy@1d87400 {
<0 0x01d87800 0 0x108>,
<0 0x01d87a00 0 0x1e0>;
#phy-cells = <0>;
- #clock-cells = <0>;
};
};
@@ -1517,7 +1516,6 @@ ufs_card_phy_lanes: phy@1da7400 {
<0 0x01da7800 0 0x108>,
<0 0x01da7a00 0 0x1e0>;
#phy-cells = <0>;
- #clock-cells = <0>;
};
};
--
2.35.1
The QMP UFS PHY provides more than one symbol clock and would need an
index to differentiate the clocks, but none of this is described by the
binding currently.
Drop the incorrect '#clock-cells' property for now.
Signed-off-by: Johan Hovold <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 7e399d739cd9..57f5ece8b741 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2148,7 +2148,6 @@ ufs_mem_phy_lanes: phy@1d87400 {
<0 0x01d87800 0 0x108>,
<0 0x01d87a00 0 0x1e0>;
#phy-cells = <0>;
- #clock-cells = <0>;
};
};
--
2.35.1
The QMP PCIe PHY provides a single clock so drop the redundant clock
index.
Signed-off-by: Johan Hovold <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index e66fc67de206..b0ae2dbba50f 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -818,7 +818,7 @@ gcc: clock-controller@100000 {
reg = <0 0x00100000 0 0x1f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
- <0>, <&pcie1_lane 0>,
+ <0>, <&pcie1_lane>,
<0>, <0>, <0>, <0>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
"pcie_0_pipe_clk", "pcie_1_pipe_clk",
@@ -2110,7 +2110,7 @@ pcie1_lane: phy@1c0e200 {
clock-names = "pipe0";
#phy-cells = <0>;
- #clock-cells = <1>;
+ #clock-cells = <0>;
clock-output-names = "pcie_1_pipe_clk";
};
};
--
2.35.1
The QMP PCIe PHY provides a single clock so drop the redundant clock
index from the first PCIe PHY and add the missing '#clock-cells'
properties to the second and third PHY nodes.
Signed-off-by: Johan Hovold <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 34fd0c68b6e8..b670d0412760 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -609,7 +609,7 @@ pciephy_0: phy@35000 {
<0x00035400 0x1dc>;
#phy-cells = <0>;
- #clock-cells = <1>;
+ #clock-cells = <0>;
clock-output-names = "pcie_0_pipe_clk_src";
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "pipe0";
@@ -623,6 +623,7 @@ pciephy_1: phy@36000 {
<0x00036400 0x1dc>;
#phy-cells = <0>;
+ #clock-cells = <0>;
clock-output-names = "pcie_1_pipe_clk_src";
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
clock-names = "pipe1";
@@ -636,6 +637,7 @@ pciephy_2: phy@37000 {
<0x00037400 0x1dc>;
#phy-cells = <0>;
+ #clock-cells = <0>;
clock-output-names = "pcie_2_pipe_clk_src";
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
clock-names = "pipe2";
--
2.35.1
The QMP USB PHY provides a single clock so drop the redundant clock
index.
Signed-off-by: Johan Hovold <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 7d08fad76371..c06c95c0c557 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -2001,7 +2001,7 @@ usb_1_ssphy: phy@88e9200 {
<0 0x088e9800 0 0x200>,
<0 0x088e9a00 0 0x100>;
#phy-cells = <0>;
- #clock-cells = <1>;
+ #clock-cells = <0>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
--
2.35.1
The QMP USB PHY provides a single clock so drop the redundant clock
index.
Signed-off-by: Johan Hovold <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 9932186f7ceb..34fd0c68b6e8 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -2769,7 +2769,7 @@ ssusb_phy_0: phy@7410200 {
<0x07410600 0x1a8>;
#phy-cells = <0>;
- #clock-cells = <1>;
+ #clock-cells = <0>;
clock-output-names = "usb3_phy_pipe_clk_src";
clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
clock-names = "pipe0";
--
2.35.1
The QMP USB PHY provides a single clock so drop the redundant clock
index.
Signed-off-by: Johan Hovold <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 4c38b15c6fd4..f9c15b3adbfb 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -130,7 +130,7 @@ usb1_ssphy: phy@58200 {
<0x00058800 0x1f8>, /* PCS */
<0x00058600 0x044>; /* PCS misc*/
#phy-cells = <0>;
- #clock-cells = <1>;
+ #clock-cells = <0>;
clocks = <&gcc GCC_USB1_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "gcc_usb1_pipe_clk_src";
@@ -173,7 +173,7 @@ usb0_ssphy: phy@78200 {
<0x00078800 0x1f8>, /* PCS */
<0x00078600 0x044>; /* PCS misc*/
#phy-cells = <0>;
- #clock-cells = <1>;
+ #clock-cells = <0>;
clocks = <&gcc GCC_USB0_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "gcc_usb0_pipe_clk_src";
--
2.35.1
On 05/07/2022 14:40, Johan Hovold wrote:
> Add the missing '#clock-cells' properties to the PCIe QMP PHY nodes.
>
> Signed-off-by: Johan Hovold <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
--
With best wishes
Dmitry
On 05/07/2022 14:40, Johan Hovold wrote:
> The QMP PCIe PHY provides a single clock so drop the redundant clock
> index.
>
> Signed-off-by: Johan Hovold <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
--
With best wishes
Dmitry
On 05/07/2022 14:40, Johan Hovold wrote:
> The QMP USB PHY provides a single clock so drop the redundant clock
> index.
>
> Signed-off-by: Johan Hovold <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
--
With best wishes
Dmitry
On Tue, Jul 05, 2022 at 03:42:08PM +0300, Dmitry Baryshkov wrote:
> On 05/07/2022 14:40, Johan Hovold wrote:
> > The QMP PCIe PHY provides a single clock so drop the redundant clock
> > index.
> >
> > Signed-off-by: Johan Hovold <[email protected]>
>
> Hmm. After checking the source code, the clocks entry of the phy@1c0e000
> node also needs to be fixed.
I assume you meant pci@1c08000 here? Thanks for catching that!
> And also maybe:
>
> Fixes: bd7d507935ca ("arm64: dts: qcom: sc7280: Add pcie clock support")
> Fixes: 92e0ee9f83b3 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related
> nodes")
Maybe, I'm a bit reluctant to add a Fixes tags for these even if they do
violate the binding. But sure, why not.
> > ---
> > arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > index e66fc67de206..b0ae2dbba50f 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > @@ -818,7 +818,7 @@ gcc: clock-controller@100000 {
> > reg = <0 0x00100000 0 0x1f0000>;
> > clocks = <&rpmhcc RPMH_CXO_CLK>,
> > <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
> > - <0>, <&pcie1_lane 0>,
> > + <0>, <&pcie1_lane>,
> > <0>, <0>, <0>, <0>;
> > clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
> > "pcie_0_pipe_clk", "pcie_1_pipe_clk",
> > @@ -2110,7 +2110,7 @@ pcie1_lane: phy@1c0e200 {
> > clock-names = "pipe0";
> >
> > #phy-cells = <0>;
> > - #clock-cells = <1>;
> > + #clock-cells = <0>;
> > clock-output-names = "pcie_1_pipe_clk";
> > };
> > };
Johan
On 05/07/2022 14:40, Johan Hovold wrote:
> The QMP PCIe PHY provides a single clock so drop the redundant clock
> index.
>
> Signed-off-by: Johan Hovold <[email protected]>
Hmm. After checking the source code, the clocks entry of the phy@1c0e000
node also needs to be fixed.
And also maybe:
Fixes: bd7d507935ca ("arm64: dts: qcom: sc7280: Add pcie clock support")
Fixes: 92e0ee9f83b3 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related
nodes")
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index e66fc67de206..b0ae2dbba50f 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -818,7 +818,7 @@ gcc: clock-controller@100000 {
> reg = <0 0x00100000 0 0x1f0000>;
> clocks = <&rpmhcc RPMH_CXO_CLK>,
> <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
> - <0>, <&pcie1_lane 0>,
> + <0>, <&pcie1_lane>,
> <0>, <0>, <0>, <0>;
> clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
> "pcie_0_pipe_clk", "pcie_1_pipe_clk",
> @@ -2110,7 +2110,7 @@ pcie1_lane: phy@1c0e200 {
> clock-names = "pipe0";
>
> #phy-cells = <0>;
> - #clock-cells = <1>;
> + #clock-cells = <0>;
> clock-output-names = "pcie_1_pipe_clk";
> };
> };
--
With best wishes
Dmitry
On 05/07/2022 14:40, Johan Hovold wrote:
> The QMP USB PHY provides a single clock so drop the redundant clock
> index.
>
> Signed-off-by: Johan Hovold <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
--
With best wishes
Dmitry
On 05/07/2022 14:40, Johan Hovold wrote:
> The QMP UFS PHY provides more than one symbol clock and would need an
> index to differentiate the clocks, but none of this is described by the
> binding currently.
>
> Drop the incorrect '#clock-cells' property for now.
Could you please take a glance whether
https://lore.kernel.org/linux-arm-msm/[email protected]/
makes a sense to the sc8280xp platform?
>
> Signed-off-by: Johan Hovold <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 345a19a6e874..ce4df4e814fe 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -1447,7 +1447,6 @@ ufs_mem_phy_lanes: phy@1d87400 {
> <0 0x01d87800 0 0x108>,
> <0 0x01d87a00 0 0x1e0>;
> #phy-cells = <0>;
> - #clock-cells = <0>;
> };
> };
>
> @@ -1517,7 +1516,6 @@ ufs_card_phy_lanes: phy@1da7400 {
> <0 0x01da7800 0 0x108>,
> <0 0x01da7a00 0 0x1e0>;
> #phy-cells = <0>;
> - #clock-cells = <0>;
> };
> };
>
--
With best wishes
Dmitry
On 05/07/2022 14:40, Johan Hovold wrote:
> Add the missing '#clock-cells' properties to the PCIe QMP PHY nodes.
>
> Signed-off-by: Johan Hovold <[email protected]>
Fixes: e53bdfc00977 ("arm64: dts: qcom: sm8250: Add PCIe support")
> ---
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index 53e0b57c13e4..f45a6cca397f 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -1892,6 +1892,8 @@ pcie0_lane: phy@1c06200 {
> clock-names = "pipe0";
>
> #phy-cells = <0>;
> +
> + #clock-cells = <0>;
> clock-output-names = "pcie_0_pipe_clk";
> };
> };
> @@ -1998,6 +2000,8 @@ pcie1_lane: phy@1c0e200 {
> clock-names = "pipe0";
>
> #phy-cells = <0>;
> +
> + #clock-cells = <0>;
> clock-output-names = "pcie_1_pipe_clk";
> };
> };
> @@ -2104,6 +2108,8 @@ pcie2_lane: phy@1c16200 {
> clock-names = "pipe0";
>
> #phy-cells = <0>;
> +
> + #clock-cells = <0>;
> clock-output-names = "pcie_2_pipe_clk";
> };
> };
--
With best wishes
Dmitry
On 05/07/2022 14:40, Johan Hovold wrote:
> The QMP USB PHY provides a single clock so drop the redundant clock
> index.
>
> Signed-off-by: Johan Hovold <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
> --
With best wishes
Dmitry
On 05/07/2022 14:40, Johan Hovold wrote:
> Clean up the PCIe PHY nodes by using a non-empty ranges property.
A matter of taste, but nevertheless:
Reviewed-by: Dmitry Baryshkov <[email protected]>
>
> Signed-off-by: Johan Hovold <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 26 +++++++++++++-------------
> 1 file changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index b670d0412760..16869bb7d625 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -590,7 +590,7 @@ pcie_phy: phy@34000 {
> reg = <0x00034000 0x488>;
> #address-cells = <1>;
> #size-cells = <1>;
> - ranges;
> + ranges = <0x0 0x00034000 0x4000>;
>
> clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
> <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
> @@ -603,10 +603,10 @@ pcie_phy: phy@34000 {
> reset-names = "phy", "common", "cfg";
> status = "disabled";
>
> - pciephy_0: phy@35000 {
> - reg = <0x00035000 0x130>,
> - <0x00035200 0x200>,
> - <0x00035400 0x1dc>;
> + pciephy_0: phy@1000 {
> + reg = <0x1000 0x130>,
> + <0x1200 0x200>,
> + <0x1400 0x1dc>;
> #phy-cells = <0>;
>
> #clock-cells = <0>;
> @@ -617,10 +617,10 @@ pciephy_0: phy@35000 {
> reset-names = "lane0";
> };
>
> - pciephy_1: phy@36000 {
> - reg = <0x00036000 0x130>,
> - <0x00036200 0x200>,
> - <0x00036400 0x1dc>;
> + pciephy_1: phy@2000 {
> + reg = <0x2000 0x130>,
> + <0x2200 0x200>,
> + <0x2400 0x1dc>;
> #phy-cells = <0>;
>
> #clock-cells = <0>;
> @@ -631,10 +631,10 @@ pciephy_1: phy@36000 {
> reset-names = "lane1";
> };
>
> - pciephy_2: phy@37000 {
> - reg = <0x00037000 0x130>,
> - <0x00037200 0x200>,
> - <0x00037400 0x1dc>;
> + pciephy_2: phy@3000 {
> + reg = <0x3000 0x130>,
> + <0x3200 0x200>,
> + <0x3400 0x1dc>;
> #phy-cells = <0>;
>
> #clock-cells = <0>;
--
With best wishes
Dmitry
On 05/07/2022 14:40, Johan Hovold wrote:
> The QMP USB PHY provides a single clock so drop the redundant clock
> index.
>
> Signed-off-by: Johan Hovold <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
However please note
https://lore.kernel.org/linux-arm-msm/[email protected]/
(for this and the last patch).
> ---
> arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> index 758c45bbbe78..2511e70d66ef 100644
> --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> @@ -2080,7 +2080,7 @@ usb1_ssphy: phy@c010200 {
> <0xc010600 0x128>,
> <0xc010800 0x200>;
> #phy-cells = <0>;
> - #clock-cells = <1>;
> + #clock-cells = <0>;
> clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
> clock-names = "pipe0";
> clock-output-names = "usb3_phy_pipe_clk_src";
--
With best wishes
Dmitry
On Tue, 5 Jul 2022 at 15:51, Johan Hovold <[email protected]> wrote:
>
> On Tue, Jul 05, 2022 at 03:42:08PM +0300, Dmitry Baryshkov wrote:
> > On 05/07/2022 14:40, Johan Hovold wrote:
> > > The QMP PCIe PHY provides a single clock so drop the redundant clock
> > > index.
> > >
> > > Signed-off-by: Johan Hovold <[email protected]>
> >
> > Hmm. After checking the source code, the clocks entry of the phy@1c0e000
> > node also needs to be fixed.
>
> I assume you meant pci@1c08000 here? Thanks for catching that!
>
> > And also maybe:
> >
> > Fixes: bd7d507935ca ("arm64: dts: qcom: sc7280: Add pcie clock support")
> > Fixes: 92e0ee9f83b3 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related
> > nodes")
>
> Maybe, I'm a bit reluctant to add a Fixes tags for these even if they do
> violate the binding. But sure, why not.
Yep, I'm also in doubt here. In this case this is more logical. I'd
allow you to decide then.
>
> > > ---
> > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++--
> > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > index e66fc67de206..b0ae2dbba50f 100644
> > > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > @@ -818,7 +818,7 @@ gcc: clock-controller@100000 {
> > > reg = <0 0x00100000 0 0x1f0000>;
> > > clocks = <&rpmhcc RPMH_CXO_CLK>,
> > > <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
> > > - <0>, <&pcie1_lane 0>,
> > > + <0>, <&pcie1_lane>,
> > > <0>, <0>, <0>, <0>;
> > > clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
> > > "pcie_0_pipe_clk", "pcie_1_pipe_clk",
> > > @@ -2110,7 +2110,7 @@ pcie1_lane: phy@1c0e200 {
> > > clock-names = "pipe0";
> > >
> > > #phy-cells = <0>;
> > > - #clock-cells = <1>;
> > > + #clock-cells = <0>;
> > > clock-output-names = "pcie_1_pipe_clk";
> > > };
> > > };
>
> Johan
--
With best wishes
Dmitry
On Tue, 5 Jul 2022 13:40:18 +0200, Johan Hovold wrote:
> Here's a bunch of fixes for PHY related DT issues found while amending
> the current QMP PHY schema:
>
> https://lore.kernel.org/r/[email protected]
>
> Included are also some cleanups of the MS8996 PCIe PHY node which make
> the node match the new binding example.
>
> [...]
Applied, thanks!
[01/14] arm64: dts: qcom: sc7280: drop PCIe PHY clock index
commit: 531c738fb36069d60aff267a0b25533a35d59fd0
[02/14] arm64: dts: qcom: sm8250: add missing PCIe PHY clock-cells
commit: d9fd162ce764c227fcfd4242f6c1639895a9481f
[03/14] arm64: dts: qcom: ipq6018: drop USB PHY clock index
commit: 9215a64a0776c4797ed08520655fba7e85530156
[04/14] arm64: dts: qcom: ipq8074: drop USB PHY clock index
commit: de9e7f77d8694ed6f5064fe865711b5f8321c09d
[05/14] arm64: dts: qcom: msm8996: drop USB PHY clock index
(no commit info)
[06/14] arm64: dts: qcom: msm8998: drop USB PHY clock index
commit: ed9cbbcb8c6a1925db7995214602c6a8983ff870
[07/14] arm64: dts: qcom: sm8350: drop USB PHY clock index
commit: af5515543b9b5999d547f4f2afcad95f0aff5b1d
[08/14] arm64: dts: qcom: sm8450: drop USB PHY clock index
commit: 0aaa0a9a4745ff4b4ffeed80ce3463c9c8c0f693
[09/14] arm64: dts: qcom: sc8280xp: drop UFS PHY clock-cells
commit: 119feff14672af57cc62d2e1350a34e4aa3c5f10
[10/14] arm64: dts: qcom: sm8250: drop UFS PHY clock-cells
commit: be18bc7bd9e82e2d08095d9ed0d9978dcb707e7c
[11/14] arm64: dts: qcom: sm8450: drop UFS PHY clock-cells
commit: e30d9f1e58c0f860b8a740c63527106146f0f3fd
[12/14] arm64: dts: qcom: msm8996: add missing PCIe PHY clock-cells
(no commit info)
[13/14] arm64: dts: qcom: msm8996: use non-empty ranges for PCIe PHYs
commit: 3a5da59af38d77088aa5226208cca0beb9125485
[14/14] arm64: dts: qcom: msm8996: clean up PCIe PHY node
commit: 02d99d4cfe0984ea05edfbcbae2c9660a05f7b11
Best regards,
--
Bjorn Andersson <[email protected]>
On Tue, Jul 05, 2022 at 04:09:14PM +0300, Dmitry Baryshkov wrote:
> On 05/07/2022 14:40, Johan Hovold wrote:
> > The QMP USB PHY provides a single clock so drop the redundant clock
> > index.
> >
> > Signed-off-by: Johan Hovold <[email protected]>
>
> Reviewed-by: Dmitry Baryshkov <[email protected]>
>
> However please note
> https://lore.kernel.org/linux-arm-msm/[email protected]/
> (for this and the last patch).
Ah, I had not seen that one. Bjorn appears to have applied your series
before this one so these two patches became empty and were dropped.
Thanks for reviewing!
Johan