[v7]
* Fix commit text of [5/5]. Remove '.' from Fixes tag.
[v6]
* Add [1], [2] to handle the regmap overlap of lpasscc and lpass_aon
[v5]
* Fix the fail path and add pm_runtime_disable().
[v4]
* Fix the "fixes" tag.
[v3]
* Remove the maxItems from reg property.
[v2]
* Update/fix the YAML for reg property against each compatible.
[v1]
* Add support for clock gating resets for lpass audio clock
controller & MCLKs.
Satya Priya (2):
dt-bindings: clock: Add "qcom,adsp-pil-mode" property
clk: qcom: lpass: Handle the regmap overlap of lpasscc and lpass_aon
Taniya Das (3):
dt-bindings: clock: Add resets for LPASS audio clock controller for
SC7280
dt-bindings: clock: Add support for external MCLKs for LPASS on SC7280
clk: qcom: lpass: Add support for resets & external mclk for SC7280
.../bindings/clock/qcom,sc7280-lpasscc.yaml | 6 +-
.../bindings/clock/qcom,sc7280-lpasscorecc.yaml | 26 ++++++++-
drivers/clk/qcom/lpassaudiocc-sc7280.c | 66 +++++++++++++++++++++-
drivers/clk/qcom/lpasscc-sc7280.c | 44 ---------------
drivers/clk/qcom/lpasscorecc-sc7280.c | 33 +++++++++++
.../dt-bindings/clock/qcom,lpassaudiocc-sc7280.h | 5 ++
.../dt-bindings/clock/qcom,lpasscorecc-sc7280.h | 2 +
7 files changed, 130 insertions(+), 52 deletions(-)
--
2.7.4
From: Taniya Das <[email protected]>
The clock gating control for TX/RX/WSA core bus clocks would be required
to be reset(moved from hardware control) from audio core driver. Thus
add the support for the reset clocks.
Update the lpass_aon_cc_main_rcg_clk_src ops to park the RCG at XO after
disable as this clock signal is used by hardware to turn ON memories in
LPASS. Also add the external mclk to interface external MI2S.
Fixes: a9dd26639d05 ("clk: qcom: lpass: Add support for LPASS clock controller for SC7280")
Signed-off-by: Taniya Das <[email protected]>
---
drivers/clk/qcom/lpassaudiocc-sc7280.c | 22 +++++++++++++++++++++-
drivers/clk/qcom/lpasscorecc-sc7280.c | 33 +++++++++++++++++++++++++++++++++
2 files changed, 54 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpassaudiocc-sc7280.c
index 6067328..063e036 100644
--- a/drivers/clk/qcom/lpassaudiocc-sc7280.c
+++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c
@@ -23,6 +23,7 @@
#include "clk-regmap-mux.h"
#include "common.h"
#include "gdsc.h"
+#include "reset.h"
enum {
P_BI_TCXO,
@@ -248,7 +249,7 @@ static struct clk_rcg2 lpass_aon_cc_main_rcg_clk_src = {
.parent_data = lpass_aon_cc_parent_data_0,
.num_parents = ARRAY_SIZE(lpass_aon_cc_parent_data_0),
.flags = CLK_OPS_PARENT_ENABLE,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -703,6 +704,18 @@ static const struct qcom_cc_desc lpass_audio_cc_sc7280_desc = {
.num_clks = ARRAY_SIZE(lpass_audio_cc_sc7280_clocks),
};
+static const struct qcom_reset_map lpass_audio_cc_sc7280_resets[] = {
+ [LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
+ [LPASS_AUDIO_SWR_TX_CGCR] = { 0xa8, 1 },
+ [LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 },
+};
+
+static const struct qcom_cc_desc lpass_audio_cc_reset_sc7280_desc = {
+ .config = &lpass_audio_cc_sc7280_regmap_config,
+ .resets = lpass_audio_cc_sc7280_resets,
+ .num_resets = ARRAY_SIZE(lpass_audio_cc_sc7280_resets),
+};
+
static const struct of_device_id lpass_audio_cc_sc7280_match_table[] = {
{ .compatible = "qcom,sc7280-lpassaudiocc" },
{ }
@@ -779,6 +792,13 @@ static int lpass_audio_cc_sc7280_probe(struct platform_device *pdev)
return ret;
}
+ ret = qcom_cc_probe_by_index(pdev, 1, &lpass_audio_cc_reset_sc7280_desc);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to register LPASS AUDIO CC Resets\n");
+ pm_runtime_disable(&pdev->dev);
+ return ret;
+ }
+
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_put_autosuspend(&pdev->dev);
pm_runtime_put_sync(&pdev->dev);
diff --git a/drivers/clk/qcom/lpasscorecc-sc7280.c b/drivers/clk/qcom/lpasscorecc-sc7280.c
index 1f1f1bd..6ad19b0 100644
--- a/drivers/clk/qcom/lpasscorecc-sc7280.c
+++ b/drivers/clk/qcom/lpasscorecc-sc7280.c
@@ -190,6 +190,19 @@ static struct clk_rcg2 lpass_core_cc_ext_if1_clk_src = {
},
};
+static struct clk_rcg2 lpass_core_cc_ext_mclk0_clk_src = {
+ .cmd_rcgr = 0x20000,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = lpass_core_cc_parent_map_0,
+ .freq_tbl = ftbl_lpass_core_cc_ext_if0_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "lpass_core_cc_ext_mclk0_clk_src",
+ .parent_data = lpass_core_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(lpass_core_cc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
static struct clk_branch lpass_core_cc_core_clk = {
.halt_reg = 0x1f000,
@@ -283,6 +296,24 @@ static struct clk_branch lpass_core_cc_lpm_mem0_core_clk = {
},
};
+static struct clk_branch lpass_core_cc_ext_mclk0_clk = {
+ .halt_reg = 0x20014,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x20014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "lpass_core_cc_ext_mclk0_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &lpass_core_cc_ext_mclk0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch lpass_core_cc_sysnoc_mport_core_clk = {
.halt_reg = 0x23000,
.halt_check = BRANCH_HALT_VOTED,
@@ -326,6 +357,8 @@ static struct clk_regmap *lpass_core_cc_sc7280_clocks[] = {
[LPASS_CORE_CC_LPM_CORE_CLK] = &lpass_core_cc_lpm_core_clk.clkr,
[LPASS_CORE_CC_LPM_MEM0_CORE_CLK] = &lpass_core_cc_lpm_mem0_core_clk.clkr,
[LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK] = &lpass_core_cc_sysnoc_mport_core_clk.clkr,
+ [LPASS_CORE_CC_EXT_MCLK0_CLK] = &lpass_core_cc_ext_mclk0_clk.clkr,
+ [LPASS_CORE_CC_EXT_MCLK0_CLK_SRC] = &lpass_core_cc_ext_mclk0_clk_src.clkr,
};
static struct regmap_config lpass_core_cc_sc7280_regmap_config = {
--
2.7.4
The LPASS Peripheral loader clocks would be used to bring
LPASS out of reset, when this property is present.
This is a cleanup done to handle overlap of regmap of
lpasscc and lpass_aon blocks. As a part of this, remove
the "cc" regmap from lpasscc node.
Signed-off-by: Satya Priya <[email protected]>
Signed-off-by: Taniya Das <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
---
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml | 6 ++----
.../devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml | 7 +++++++
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
index 47028d7..633887d 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
@@ -36,13 +36,11 @@ properties:
items:
- description: LPASS qdsp6ss register
- description: LPASS top-cc register
- - description: LPASS cc register
reg-names:
items:
- const: qdsp6ss
- const: top_cc
- - const: cc
required:
- compatible
@@ -59,8 +57,8 @@ examples:
#include <dt-bindings/clock/qcom,lpass-sc7280.h>
clock-controller@3000000 {
compatible = "qcom,sc7280-lpasscc";
- reg = <0x03000000 0x40>, <0x03c04000 0x4>, <0x03389000 0x24>;
- reg-names = "qdsp6ss", "top_cc", "cc";
+ reg = <0x03000000 0x40>, <0x03c04000 0x4>;
+ reg-names = "qdsp6ss", "top_cc";
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface";
#clock-cells = <1>;
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
index bad9135..5ccfb24 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
@@ -41,6 +41,12 @@ properties:
reg:
maxItems: 1
+ qcom,adsp-pil-mode:
+ description:
+ Indicates if the LPASS would be brought out of reset using
+ peripheral loader.
+ type: boolean
+
required:
- compatible
- reg
@@ -165,6 +171,7 @@ examples:
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
<&lpasscore LPASS_CORE_CC_CORE_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao","iface";
+ qcom,adsp-pil-mode;
#clock-cells = <1>;
#power-domain-cells = <1>;
};
--
2.7.4
Why is [email protected] left off this clk patch series?
Quoting Satya Priya (2022-07-27 01:27:57)
> From: Taniya Das <[email protected]>
>
> The clock gating control for TX/RX/WSA core bus clocks would be required
> to be reset(moved from hardware control) from audio core driver. Thus
> add the support for the reset clocks.
>
> Update the lpass_aon_cc_main_rcg_clk_src ops to park the RCG at XO after
> disable as this clock signal is used by hardware to turn ON memories in
> LPASS. Also add the external mclk to interface external MI2S.
>
> Fixes: a9dd26639d05 ("clk: qcom: lpass: Add support for LPASS clock controller for SC7280")
> Signed-off-by: Taniya Das <[email protected]>
> ---
Reviewed-by: Stephen Boyd <[email protected]>
On Wed 27 Jul 03:27 CDT 2022, Satya Priya wrote:
> The LPASS Peripheral loader clocks would be used to bring
> LPASS out of reset, when this property is present.
>
Can you please elaborate on what you mean here?
When this property is set you assume that remoteproc is used to boot the
LPASS and therefor some clocks should be handled differently?
This needs to be written in a way that someone outside of your project
can understand the purpose.
> This is a cleanup done to handle overlap of regmap of
> lpasscc and lpass_aon blocks. As a part of this, remove
> the "cc" regmap from lpasscc node.
>
"regmap" is an implementation detail, the binding change should describe
the changes to the representation of the hardware description.
Thanks,
Bjorn
> Signed-off-by: Satya Priya <[email protected]>
> Signed-off-by: Taniya Das <[email protected]>
> Reviewed-by: Rob Herring <[email protected]>
> Reviewed-by: Stephen Boyd <[email protected]>
> ---
> Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml | 6 ++----
> .../devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml | 7 +++++++
> 2 files changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
> index 47028d7..633887d 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
> @@ -36,13 +36,11 @@ properties:
> items:
> - description: LPASS qdsp6ss register
> - description: LPASS top-cc register
> - - description: LPASS cc register
>
> reg-names:
> items:
> - const: qdsp6ss
> - const: top_cc
> - - const: cc
>
> required:
> - compatible
> @@ -59,8 +57,8 @@ examples:
> #include <dt-bindings/clock/qcom,lpass-sc7280.h>
> clock-controller@3000000 {
> compatible = "qcom,sc7280-lpasscc";
> - reg = <0x03000000 0x40>, <0x03c04000 0x4>, <0x03389000 0x24>;
> - reg-names = "qdsp6ss", "top_cc", "cc";
> + reg = <0x03000000 0x40>, <0x03c04000 0x4>;
> + reg-names = "qdsp6ss", "top_cc";
> clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
> clock-names = "iface";
> #clock-cells = <1>;
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
> index bad9135..5ccfb24 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
> @@ -41,6 +41,12 @@ properties:
> reg:
> maxItems: 1
>
> + qcom,adsp-pil-mode:
> + description:
> + Indicates if the LPASS would be brought out of reset using
> + peripheral loader.
> + type: boolean
> +
> required:
> - compatible
> - reg
> @@ -165,6 +171,7 @@ examples:
> clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
> <&lpasscore LPASS_CORE_CC_CORE_CLK>;
> clock-names = "bi_tcxo", "bi_tcxo_ao","iface";
> + qcom,adsp-pil-mode;
> #clock-cells = <1>;
> #power-domain-cells = <1>;
> };
> --
> 2.7.4
>
On 8/10/2022 2:49 AM, Bjorn Andersson wrote:
> On Wed 27 Jul 03:27 CDT 2022, Satya Priya wrote:
>
>> The LPASS Peripheral loader clocks would be used to bring
>> LPASS out of reset, when this property is present.
>>
> Can you please elaborate on what you mean here?
>
> When this property is set you assume that remoteproc is used to boot the
> LPASS and therefor some clocks should be handled differently?
Yes, you are right, I'll add this to the description.
> This needs to be written in a way that someone outside of your project
> can understand the purpose.
>
>> This is a cleanup done to handle overlap of regmap of
>> lpasscc and lpass_aon blocks. As a part of this, remove
>> the "cc" regmap from lpasscc node.
>>
> "regmap" is an implementation detail, the binding change should describe
> the changes to the representation of the hardware description.
Okay I'll remove the last part from description while re-posting.
> Thanks,
> Bjorn
>
>> Signed-off-by: Satya Priya <[email protected]>
>> Signed-off-by: Taniya Das <[email protected]>
>> Reviewed-by: Rob Herring <[email protected]>
>> Reviewed-by: Stephen Boyd <[email protected]>
>> ---
>> Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml | 6 ++----
>> .../devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml | 7 +++++++
>> 2 files changed, 9 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
>> index 47028d7..633887d 100644
>> --- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
>> +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
>> @@ -36,13 +36,11 @@ properties:
>> items:
>> - description: LPASS qdsp6ss register
>> - description: LPASS top-cc register
>> - - description: LPASS cc register
>>
>> reg-names:
>> items:
>> - const: qdsp6ss
>> - const: top_cc
>> - - const: cc
>>
>> required:
>> - compatible
>> @@ -59,8 +57,8 @@ examples:
>> #include <dt-bindings/clock/qcom,lpass-sc7280.h>
>> clock-controller@3000000 {
>> compatible = "qcom,sc7280-lpasscc";
>> - reg = <0x03000000 0x40>, <0x03c04000 0x4>, <0x03389000 0x24>;
>> - reg-names = "qdsp6ss", "top_cc", "cc";
>> + reg = <0x03000000 0x40>, <0x03c04000 0x4>;
>> + reg-names = "qdsp6ss", "top_cc";
>> clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
>> clock-names = "iface";
>> #clock-cells = <1>;
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
>> index bad9135..5ccfb24 100644
>> --- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
>> +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
>> @@ -41,6 +41,12 @@ properties:
>> reg:
>> maxItems: 1
>>
>> + qcom,adsp-pil-mode:
>> + description:
>> + Indicates if the LPASS would be brought out of reset using
>> + peripheral loader.
>> + type: boolean
>> +
>> required:
>> - compatible
>> - reg
>> @@ -165,6 +171,7 @@ examples:
>> clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
>> <&lpasscore LPASS_CORE_CC_CORE_CLK>;
>> clock-names = "bi_tcxo", "bi_tcxo_ao","iface";
>> + qcom,adsp-pil-mode;
>> #clock-cells = <1>;
>> #power-domain-cells = <1>;
>> };
>> --
>> 2.7.4
>>