This patchset adds more clocks support for the Qualcomm SM8550 SoC,
It adds the TCSR clock controller driver and the rpmh clocks.
Changes since v4:
* dropped the patches 1, 3, 4 and 5 since they are already applied.
* replaced DEFINE_CLK_RPMH_FIXED with DEFINE_CLK_FIXED_FACTOR
in clk-rpmh.c
* changed TCSR clock controller driver compatible string to
qcom,sm8550-tcsr
* renamed the TCSR bindings header and schema files to match
qcom,sm8550-tcsr
To: Andy Gross <[email protected]>
To: Bjorn Andersson <[email protected]>
To: Konrad Dybcio <[email protected]>
To: Michael Turquette <[email protected]>
To: Stephen Boyd <[email protected]>
To: Rob Herring <[email protected]>
To: Krzysztof Kozlowski <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Abel Vesa (5):
dt-bindings: clock: Add SM8550 TCSR CC clocks
dt-bindings: clock: Add RPMHCC for SM8550
dt-bindings: clock: qcom,rpmh: Add CXO PAD clock IDs
clk: qcom: rpmh: Add support for SM8550 rpmh clocks
clk: qcom: Add TCSR clock driver for SM8550
.../bindings/clock/qcom,rpmhcc.yaml | 1 +
.../bindings/clock/qcom,sm8550-tcsr.yaml | 53 +++++
drivers/clk/qcom/Kconfig | 7 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-rpmh.c | 110 ++++++++--
drivers/clk/qcom/tcsrcc-sm8550.c | 192 ++++++++++++++++++
include/dt-bindings/clock/qcom,rpmh.h | 2 +
include/dt-bindings/clock/qcom,sm8550-tcsr.h | 18 ++
8 files changed, 364 insertions(+), 20 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
create mode 100644 drivers/clk/qcom/tcsrcc-sm8550.c
create mode 100644 include/dt-bindings/clock/qcom,sm8550-tcsr.h
--
2.34.1
Adds the RPMH clocks present in SM8550 SoC.
Signed-off-by: Abel Vesa <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/clk-rpmh.c | 110 +++++++++++++++++++++++++++++-------
1 file changed, 90 insertions(+), 20 deletions(-)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index 2c2ef4b6d130..ce81c76ed0fd 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -130,6 +130,34 @@ static DEFINE_MUTEX(rpmh_clk_lock);
}, \
}
+#define DEFINE_CLK_FIXED_FACTOR(_name, _parent_name, _div) \
+ static struct clk_fixed_factor clk_fixed_factor##_##_name = { \
+ .mult = 1, \
+ .div = _div, \
+ .hw.init = &(struct clk_init_data){ \
+ .ops = &clk_fixed_factor_ops, \
+ .name = #_name, \
+ .parent_data = &(const struct clk_parent_data){ \
+ .fw_name = #_parent_name, \
+ .name = #_parent_name, \
+ }, \
+ .num_parents = 1, \
+ }, \
+ }; \
+ static struct clk_fixed_factor clk_fixed_factor##_##_name##_ao = { \
+ .mult = 1, \
+ .div = _div, \
+ .hw.init = &(struct clk_init_data){ \
+ .ops = &clk_fixed_factor_ops, \
+ .name = #_name "_ao", \
+ .parent_data = &(const struct clk_parent_data){ \
+ .fw_name = #_parent_name "_ao", \
+ .name = #_parent_name "_ao", \
+ }, \
+ .num_parents = 1, \
+ }, \
+ }
+
static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw)
{
return container_of(_hw, struct clk_rpmh, hw);
@@ -345,6 +373,8 @@ DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 2);
DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 4);
DEFINE_CLK_RPMH_ARC(qlink, "qphy.lvl", 0x1, 4);
+DEFINE_CLK_FIXED_FACTOR(bi_tcxo_div2, bi_tcxo, 2);
+
DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a2, "lnbclka1", 2);
DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a2, "lnbclka2", 2);
DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a2, "lnbclka3", 2);
@@ -366,6 +396,16 @@ DEFINE_CLK_RPMH_VRM(rf_clk2, _d, "rfclkd2", 1);
DEFINE_CLK_RPMH_VRM(rf_clk3, _d, "rfclkd3", 1);
DEFINE_CLK_RPMH_VRM(rf_clk4, _d, "rfclkd4", 1);
+DEFINE_CLK_RPMH_VRM(clk1, _a1, "clka1", 1);
+DEFINE_CLK_RPMH_VRM(clk2, _a1, "clka2", 1);
+DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1);
+DEFINE_CLK_RPMH_VRM(clk4, _a1, "clka4", 1);
+DEFINE_CLK_RPMH_VRM(clk5, _a1, "clka5", 1);
+
+DEFINE_CLK_RPMH_VRM(clk6, _a2, "clka6", 2);
+DEFINE_CLK_RPMH_VRM(clk7, _a2, "clka7", 2);
+DEFINE_CLK_RPMH_VRM(clk8, _a2, "clka8", 2);
+
DEFINE_CLK_RPMH_VRM(div_clk1, _div2, "divclka1", 2);
DEFINE_CLK_RPMH_BCM(ce, "CE0");
@@ -576,6 +616,33 @@ static const struct clk_rpmh_desc clk_rpmh_sm8450 = {
.num_clks = ARRAY_SIZE(sm8450_rpmh_clocks),
};
+static struct clk_hw *sm8550_rpmh_clocks[] = {
+ [RPMH_CXO_PAD_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
+ [RPMH_CXO_PAD_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
+ [RPMH_CXO_CLK] = &clk_fixed_factor_bi_tcxo_div2.hw,
+ [RPMH_CXO_CLK_A] = &clk_fixed_factor_bi_tcxo_div2_ao.hw,
+ [RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw,
+ [RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw,
+ [RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a2.hw,
+ [RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a2_ao.hw,
+ [RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw,
+ [RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw,
+ [RPMH_RF_CLK1] = &clk_rpmh_clk1_a1.hw,
+ [RPMH_RF_CLK1_A] = &clk_rpmh_clk1_a1_ao.hw,
+ [RPMH_RF_CLK2] = &clk_rpmh_clk2_a1.hw,
+ [RPMH_RF_CLK2_A] = &clk_rpmh_clk2_a1_ao.hw,
+ [RPMH_RF_CLK3] = &clk_rpmh_clk3_a1.hw,
+ [RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a1_ao.hw,
+ [RPMH_RF_CLK4] = &clk_rpmh_clk4_a1.hw,
+ [RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a1_ao.hw,
+ [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
+};
+
+static const struct clk_rpmh_desc clk_rpmh_sm8550 = {
+ .clks = sm8550_rpmh_clocks,
+ .num_clks = ARRAY_SIZE(sm8550_rpmh_clocks),
+};
+
static struct clk_hw *sc7280_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
@@ -683,29 +750,31 @@ static int clk_rpmh_probe(struct platform_device *pdev)
name = hw_clks[i]->init->name;
- rpmh_clk = to_clk_rpmh(hw_clks[i]);
- res_addr = cmd_db_read_addr(rpmh_clk->res_name);
- if (!res_addr) {
- dev_err(&pdev->dev, "missing RPMh resource address for %s\n",
- rpmh_clk->res_name);
- return -ENODEV;
- }
+ if (hw_clks[i]->init->ops != &clk_fixed_factor_ops) {
+ rpmh_clk = to_clk_rpmh(hw_clks[i]);
+ res_addr = cmd_db_read_addr(rpmh_clk->res_name);
+ if (!res_addr) {
+ dev_err(&pdev->dev, "missing RPMh resource address for %s\n",
+ rpmh_clk->res_name);
+ return -ENODEV;
+ }
- data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len);
- if (IS_ERR(data)) {
- ret = PTR_ERR(data);
- dev_err(&pdev->dev,
- "error reading RPMh aux data for %s (%d)\n",
- rpmh_clk->res_name, ret);
- return ret;
- }
+ data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len);
+ if (IS_ERR(data)) {
+ ret = PTR_ERR(data);
+ dev_err(&pdev->dev,
+ "error reading RPMh aux data for %s (%d)\n",
+ rpmh_clk->res_name, ret);
+ return ret;
+ }
- /* Convert unit from Khz to Hz */
- if (aux_data_len == sizeof(*data))
- rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL;
+ /* Convert unit from Khz to Hz */
+ if (aux_data_len == sizeof(*data))
+ rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL;
- rpmh_clk->res_addr += res_addr;
- rpmh_clk->dev = &pdev->dev;
+ rpmh_clk->res_addr += res_addr;
+ rpmh_clk->dev = &pdev->dev;
+ }
ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]);
if (ret) {
@@ -741,6 +810,7 @@ static const struct of_device_id clk_rpmh_match_table[] = {
{ .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
{ .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350},
{ .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450},
+ { .compatible = "qcom,sm8550-rpmh-clk", .data = &clk_rpmh_sm8550},
{ .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280},
{ }
};
--
2.34.1
Add bindings documentation for clock TCSR driver on SM8550.
Signed-off-by: Abel Vesa <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
.../bindings/clock/qcom,sm8550-tcsr.yaml | 53 +++++++++++++++++++
include/dt-bindings/clock/qcom,sm8550-tcsr.h | 18 +++++++
2 files changed, 71 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
create mode 100644 include/dt-bindings/clock/qcom,sm8550-tcsr.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
new file mode 100644
index 000000000000..15176b0457d1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm TCSR Clock Controller on SM8550
+
+maintainers:
+ - Bjorn Andersson <[email protected]>
+
+description: |
+ Qualcomm TCSR clock control module provides the clocks, resets and
+ power domains on SM8550
+
+ See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h
+
+properties:
+ compatible:
+ const: qcom,sm8550-tcsr
+
+ clocks:
+ items:
+ - description: Board XO source
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+
+ clock-controller@1fc0000 {
+ compatible = "qcom,sm8550-tcsr";
+ reg = <0x1fc0000 0x30000>;
+ clocks = <&rpmhcc RPMH_CXO_PAD_CLK>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+...
diff --git a/include/dt-bindings/clock/qcom,sm8550-tcsr.h b/include/dt-bindings/clock/qcom,sm8550-tcsr.h
new file mode 100644
index 000000000000..091cb76f953a
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm8550-tcsr.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Linaro Limited
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8550_H
+#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8550_H
+
+/* TCSR CC clocks */
+#define TCSR_PCIE_0_CLKREF_EN 0
+#define TCSR_PCIE_1_CLKREF_EN 1
+#define TCSR_UFS_CLKREF_EN 2
+#define TCSR_UFS_PAD_CLKREF_EN 3
+#define TCSR_USB2_CLKREF_EN 4
+#define TCSR_USB3_CLKREF_EN 5
+
+#endif
--
2.34.1
On 06/12/2022 13:56, Abel Vesa wrote:
> Add bindings documentation for clock TCSR driver on SM8550.
>
> Signed-off-by: Abel Vesa <[email protected]>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../bindings/clock/qcom,sm8550-tcsr.yaml | 53 +++++++++++++++++++
> include/dt-bindings/clock/qcom,sm8550-tcsr.h | 18 +++++++
> 2 files changed, 71 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
> create mode 100644 include/dt-bindings/clock/qcom,sm8550-tcsr.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
> new file mode 100644
> index 000000000000..15176b0457d1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
> @@ -0,0 +1,53 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm TCSR Clock Controller on SM8550
> +
> +maintainers:
> + - Bjorn Andersson <[email protected]>
> +
> +description: |
> + Qualcomm TCSR clock control module provides the clocks, resets and
> + power domains on SM8550
> +
> + See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h
> +
> +properties:
> + compatible:
> + const: qcom,sm8550-tcsr
This still misses syscon. Did you send it before we talk on IRC?
Best regards,
Krzysztof
On Tue, Dec 06, 2022 at 02:56:31PM +0200, Abel Vesa wrote:
> Add bindings documentation for clock TCSR driver on SM8550.
>
> Signed-off-by: Abel Vesa <[email protected]>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../bindings/clock/qcom,sm8550-tcsr.yaml | 53 +++++++++++++++++++
> include/dt-bindings/clock/qcom,sm8550-tcsr.h | 18 +++++++
> 2 files changed, 71 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
> create mode 100644 include/dt-bindings/clock/qcom,sm8550-tcsr.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
> new file mode 100644
> index 000000000000..15176b0457d1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
> @@ -0,0 +1,53 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm TCSR Clock Controller on SM8550
> +
> +maintainers:
> + - Bjorn Andersson <[email protected]>
> +
> +description: |
> + Qualcomm TCSR clock control module provides the clocks, resets and
> + power domains on SM8550
> +
> + See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h
> +
> +properties:
> + compatible:
> + const: qcom,sm8550-tcsr
> +
> + clocks:
> + items:
> + - description: Board XO source
This sounds like the crystal feeding the PMIC, but the clock here should
be the signal that arrives at the CXO pin of the SoC.
Other than that, this looks good now.
Thanks,
Bjorn
> +
> + reg:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> + '#reset-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - clocks
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,rpmh.h>
> +
> + clock-controller@1fc0000 {
> + compatible = "qcom,sm8550-tcsr";
> + reg = <0x1fc0000 0x30000>;
> + clocks = <&rpmhcc RPMH_CXO_PAD_CLK>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> +...
> diff --git a/include/dt-bindings/clock/qcom,sm8550-tcsr.h b/include/dt-bindings/clock/qcom,sm8550-tcsr.h
> new file mode 100644
> index 000000000000..091cb76f953a
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,sm8550-tcsr.h
> @@ -0,0 +1,18 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2022, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2022, Linaro Limited
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8550_H
> +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8550_H
> +
> +/* TCSR CC clocks */
> +#define TCSR_PCIE_0_CLKREF_EN 0
> +#define TCSR_PCIE_1_CLKREF_EN 1
> +#define TCSR_UFS_CLKREF_EN 2
> +#define TCSR_UFS_PAD_CLKREF_EN 3
> +#define TCSR_USB2_CLKREF_EN 4
> +#define TCSR_USB3_CLKREF_EN 5
> +
> +#endif
> --
> 2.34.1
>
On Tue, 06 Dec 2022 14:56:31 +0200, Abel Vesa wrote:
> Add bindings documentation for clock TCSR driver on SM8550.
>
> Signed-off-by: Abel Vesa <[email protected]>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../bindings/clock/qcom,sm8550-tcsr.yaml | 53 +++++++++++++++++++
> include/dt-bindings/clock/qcom,sm8550-tcsr.h | 18 +++++++
> 2 files changed, 71 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
> create mode 100644 include/dt-bindings/clock/qcom,sm8550-tcsr.h
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Error: Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.example.dts:23.29-30 syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:406: Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1492: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
On 22-12-06 16:35:16, Krzysztof Kozlowski wrote:
> On 06/12/2022 13:56, Abel Vesa wrote:
> > Add bindings documentation for clock TCSR driver on SM8550.
> >
> > Signed-off-by: Abel Vesa <[email protected]>
> > Reviewed-by: Krzysztof Kozlowski <[email protected]>
> > ---
> > .../bindings/clock/qcom,sm8550-tcsr.yaml | 53 +++++++++++++++++++
> > include/dt-bindings/clock/qcom,sm8550-tcsr.h | 18 +++++++
> > 2 files changed, 71 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
> > create mode 100644 include/dt-bindings/clock/qcom,sm8550-tcsr.h
> >
> > diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
> > new file mode 100644
> > index 000000000000..15176b0457d1
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
> > @@ -0,0 +1,53 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm TCSR Clock Controller on SM8550
> > +
> > +maintainers:
> > + - Bjorn Andersson <[email protected]>
> > +
> > +description: |
> > + Qualcomm TCSR clock control module provides the clocks, resets and
> > + power domains on SM8550
> > +
> > + See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h
> > +
> > +properties:
> > + compatible:
> > + const: qcom,sm8550-tcsr
>
> This still misses syscon. Did you send it before we talk on IRC?
Oups, I forgot to squash that part in.
Will send a new version.
>
> Best regards,
> Krzysztof
>
On 22-12-06 12:23:32, Bjorn Andersson wrote:
> On Tue, Dec 06, 2022 at 02:56:31PM +0200, Abel Vesa wrote:
> > Add bindings documentation for clock TCSR driver on SM8550.
> >
> > Signed-off-by: Abel Vesa <[email protected]>
> > Reviewed-by: Krzysztof Kozlowski <[email protected]>
> > ---
> > .../bindings/clock/qcom,sm8550-tcsr.yaml | 53 +++++++++++++++++++
> > include/dt-bindings/clock/qcom,sm8550-tcsr.h | 18 +++++++
> > 2 files changed, 71 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
> > create mode 100644 include/dt-bindings/clock/qcom,sm8550-tcsr.h
> >
> > diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
> > new file mode 100644
> > index 000000000000..15176b0457d1
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
> > @@ -0,0 +1,53 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm TCSR Clock Controller on SM8550
> > +
> > +maintainers:
> > + - Bjorn Andersson <[email protected]>
> > +
> > +description: |
> > + Qualcomm TCSR clock control module provides the clocks, resets and
> > + power domains on SM8550
> > +
> > + See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h
> > +
> > +properties:
> > + compatible:
> > + const: qcom,sm8550-tcsr
> > +
> > + clocks:
> > + items:
> > + - description: Board XO source
>
> This sounds like the crystal feeding the PMIC, but the clock here should
> be the signal that arrives at the CXO pin of the SoC.
Oh, I guess this should be:
- description: TCXO pad clock
Will send a new version.
>
> Other than that, this looks good now.
>
> Thanks,
> Bjorn
>
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + '#clock-cells':
> > + const: 1
> > +
> > + '#reset-cells':
> > + const: 1
> > +
> > +required:
> > + - compatible
> > + - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/qcom,rpmh.h>
> > +
> > + clock-controller@1fc0000 {
> > + compatible = "qcom,sm8550-tcsr";
> > + reg = <0x1fc0000 0x30000>;
> > + clocks = <&rpmhcc RPMH_CXO_PAD_CLK>;
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > +...
> > diff --git a/include/dt-bindings/clock/qcom,sm8550-tcsr.h b/include/dt-bindings/clock/qcom,sm8550-tcsr.h
> > new file mode 100644
> > index 000000000000..091cb76f953a
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/qcom,sm8550-tcsr.h
> > @@ -0,0 +1,18 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> > +/*
> > + * Copyright (c) 2022, The Linux Foundation. All rights reserved.
> > + * Copyright (c) 2022, Linaro Limited
> > + */
> > +
> > +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8550_H
> > +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SM8550_H
> > +
> > +/* TCSR CC clocks */
> > +#define TCSR_PCIE_0_CLKREF_EN 0
> > +#define TCSR_PCIE_1_CLKREF_EN 1
> > +#define TCSR_UFS_CLKREF_EN 2
> > +#define TCSR_UFS_PAD_CLKREF_EN 3
> > +#define TCSR_USB2_CLKREF_EN 4
> > +#define TCSR_USB3_CLKREF_EN 5
> > +
> > +#endif
> > --
> > 2.34.1
> >