From: Quentin Schulz <[email protected]>
clk_cifout is derived from clk_cifout_src through an integer divider
limited to 32. clk_cifout_src is a child of either cpll, gpll or npll
without any possibility of a divider of any sort. The default clock
parent is cpll.
Let's allow clk_cifout to ask its parent clk_cifout_src to reparent in
order to find the real closest possible rate for clk_cifout and not one
derived from cpll only.
Cc: [email protected] # 4.10+
Fixes: fd8bc829336a ("clk: rockchip: fix the rk3399 cifout clock")
Signed-off-by: Quentin Schulz <[email protected]>
---
clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent
This used to be correct before v4.10 but commit fd8bc829336a ("clk: rockchip:
fix the rk3399 cifout clock") incorrectly removed this ability while reworking
it.
Note: this has been tested on top of v6.0.2 only but no changes were made to
this driver since. As for older stable releases, the git context seems identical
and there does not seem to have been any logical change introduced since v4.10
so it should be pretty safe to apply.
To: Michael Turquette <[email protected]>
To: Stephen Boyd <[email protected]>
To: Heiko Stuebner <[email protected]>
To: Xing Zheng <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
drivers/clk/rockchip/clk-rk3399.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 306910a3a0d38..9ebd6c451b3db 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -1263,7 +1263,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKSEL_CON(56), 6, 2, MFLAGS,
RK3399_CLKGATE_CON(10), 7, GFLAGS),
- COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0,
+ COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS),
/* gic */
---
base-commit: cc675d22e422442f6d230654a55a5fc5682ea018
change-id: 20221117-rk3399-cifout-set-rate-parent-1fbf0173ef2d
Best regards,
--
Quentin Schulz <[email protected]>
Hi all,
Gently pinging as it hasn't received any review and I couldn't find the
patch in a branch in the linux-clk tree.
Cheers,
Quentin
On 11/17/22 13:04, Quentin Schulz wrote:
> From: Quentin Schulz <[email protected]>
>
> clk_cifout is derived from clk_cifout_src through an integer divider
> limited to 32. clk_cifout_src is a child of either cpll, gpll or npll
> without any possibility of a divider of any sort. The default clock
> parent is cpll.
>
> Let's allow clk_cifout to ask its parent clk_cifout_src to reparent in
> order to find the real closest possible rate for clk_cifout and not one
> derived from cpll only.
>
> Cc: [email protected] # 4.10+
> Fixes: fd8bc829336a ("clk: rockchip: fix the rk3399 cifout clock")
> Signed-off-by: Quentin Schulz <[email protected]>
> ---
> clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent
>
> This used to be correct before v4.10 but commit fd8bc829336a ("clk: rockchip:
> fix the rk3399 cifout clock") incorrectly removed this ability while reworking
> it.
>
> Note: this has been tested on top of v6.0.2 only but no changes were made to
> this driver since. As for older stable releases, the git context seems identical
> and there does not seem to have been any logical change introduced since v4.10
> so it should be pretty safe to apply.
>
> To: Michael Turquette <[email protected]>
> To: Stephen Boyd <[email protected]>
> To: Heiko Stuebner <[email protected]>
> To: Xing Zheng <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> ---
> drivers/clk/rockchip/clk-rk3399.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
> index 306910a3a0d38..9ebd6c451b3db 100644
> --- a/drivers/clk/rockchip/clk-rk3399.c
> +++ b/drivers/clk/rockchip/clk-rk3399.c
> @@ -1263,7 +1263,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
> RK3399_CLKSEL_CON(56), 6, 2, MFLAGS,
> RK3399_CLKGATE_CON(10), 7, GFLAGS),
>
> - COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0,
> + COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, CLK_SET_RATE_PARENT,
> RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS),
>
> /* gic */
>
> ---
> base-commit: cc675d22e422442f6d230654a55a5fc5682ea018
> change-id: 20221117-rk3399-cifout-set-rate-parent-1fbf0173ef2d
>
> Best regards,
On Thu, 17 Nov 2022 13:04:31 +0100, Quentin Schulz wrote:
> From: Quentin Schulz <[email protected]>
>
> clk_cifout is derived from clk_cifout_src through an integer divider
> limited to 32. clk_cifout_src is a child of either cpll, gpll or npll
> without any possibility of a divider of any sort. The default clock
> parent is cpll.
>
> [...]
Applied, thanks!
[1/1] clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent
commit: 3ad07d73ae650057fe64b2d85721c644a30428c1
Best regards,
--
Heiko Stuebner <[email protected]>