-Add 'xlnx,axi-iic-2.1' new IP version support.
-Add dynamic SCL frequency configuration support.
Raviteja Narayanam (3):
dt-bindings: i2c: xiic: Add 'xlnx,axi-iic-2.1' to compatible
i2c: xiic: Update compatible with new IP version
i2c: xiic: Add SCL frequency configuration support
---
Changes for v6:
Add enum for clock-frequency in xlnx,xps-iic-2.00.a.yaml
Changes for v5:
Update description and add default value details for clock-frequency
in xlnx,xps-iic-2.00.a.yaml
Changes since v4:
First 6 patches of "Added Standard mode and SMBus support" series applied
to for-next
https://lore.kernel.org/linux-arm-kernel/[email protected]/
.../bindings/i2c/xlnx,xps-iic-2.00.a.yaml | 11 +-
drivers/i2c/busses/i2c-xiic.c | 149 ++++++++++++++++++
2 files changed, 159 insertions(+), 1 deletion(-)
--
2.25.1
From: Raviteja Narayanam <[email protected]>
Add xilinx I2C new version 'xlnx,axi-iic-2.1' string to compatible.
Add clock-frequency as optional property.
Signed-off-by: Raviteja Narayanam <[email protected]>
Signed-off-by: Manikanta Guntupalli <[email protected]>
Acked-by: Michal Simek <[email protected]>
---
Changes for v6:
Add enum for clock-frequency in xlnx,xps-iic-2.00.a.yaml
Changes for v5:
Update description and add default value details for clock-frequency
in xlnx,xps-iic-2.00.a.yaml
Changes for v4:
Add description for clock-frequency in xlnx,xps-iic-2.00.a.yaml
Changes since v3: none
---
.../devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml b/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml
index 8d241a703d85..1b598638d457 100644
--- a/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml
+++ b/Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml
@@ -14,7 +14,9 @@ allOf:
properties:
compatible:
- const: xlnx,xps-iic-2.00.a
+ enum:
+ - xlnx,axi-iic-2.1
+ - xlnx,xps-iic-2.00.a
reg:
maxItems: 1
@@ -30,6 +32,13 @@ properties:
description: |
Input clock name.
+ clock-frequency:
+ description:
+ Optional I2C SCL clock frequency. If not specified, do not configure
+ in software, rely only on hardware design value.
+ default: 100000
+ enum: [ 100000, 400000, 1000000 ]
+
required:
- compatible
- reg
--
2.25.1
From: Raviteja Narayanam <[email protected]>
Xilinx AXI I2C IP is updated with a bug fix for dynamic mode reads.
Older IPs are handled with a workaround in which they are using
xiic standard mode for all these effected use cases.
Add the new IP version to compatible.
Signed-off-by: Raviteja Narayanam <[email protected]>
Signed-off-by: Manikanta Guntupalli <[email protected]>
Acked-by: Michal Simek <[email protected]>
---
Changes since v1: none
---
drivers/i2c/busses/i2c-xiic.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c
index 8503b5016aaf..682b3567e83e 100644
--- a/drivers/i2c/busses/i2c-xiic.c
+++ b/drivers/i2c/busses/i2c-xiic.c
@@ -1074,6 +1074,7 @@ static const struct xiic_version_data xiic_2_00 = {
#if defined(CONFIG_OF)
static const struct of_device_id xiic_of_match[] = {
{ .compatible = "xlnx,xps-iic-2.00.a", .data = &xiic_2_00 },
+ { .compatible = "xlnx,axi-iic-2.1", },
{},
};
MODULE_DEVICE_TABLE(of, xiic_of_match);
--
2.25.1
From: Raviteja Narayanam <[email protected]>
From 'clock-frequency' device tree property, configure I2C SCL
frequency by calculating the timing register values according to
input clock.
After soft reset in reinit function, the timing registers are set
to default values (configured in design tool). So, setting SCL
frequency is done inside reinit function after the soft reset.
This allows configuration of SCL frequency exclusively through
software via device tree property, overriding the design.
If the clock-frequency parameter is not specified in DT, driver
doesn't configure frequency, making it backward compatible.
Signed-off-by: Raviteja Narayanam <[email protected]>
Signed-off-by: Manikanta Guntupalli <[email protected]>
Acked-by: Michal Simek <[email protected]>
---
Changes since v1: none
---
drivers/i2c/busses/i2c-xiic.c | 148 ++++++++++++++++++++++++++++++++++
1 file changed, 148 insertions(+)
diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c
index 682b3567e83e..1e89e8270749 100644
--- a/drivers/i2c/busses/i2c-xiic.c
+++ b/drivers/i2c/busses/i2c-xiic.c
@@ -46,6 +46,12 @@ enum xiic_endian {
BIG
};
+enum i2c_scl_freq {
+ REG_VALUES_100KHZ = 0,
+ REG_VALUES_400KHZ = 1,
+ REG_VALUES_1MHZ = 2
+};
+
/**
* struct xiic_i2c - Internal representation of the XIIC I2C bus
* @dev: Pointer to device structure
@@ -66,6 +72,8 @@ enum xiic_endian {
* @prev_msg_tx: Previous message is Tx
* @quirks: To hold platform specific bug info
* @smbus_block_read: Flag to handle block read
+ * @input_clk: Input clock to I2C controller
+ * @i2c_clk: I2C SCL frequency
*/
struct xiic_i2c {
struct device *dev;
@@ -86,12 +94,37 @@ struct xiic_i2c {
bool prev_msg_tx;
u32 quirks;
bool smbus_block_read;
+ unsigned long input_clk;
+ unsigned int i2c_clk;
};
struct xiic_version_data {
u32 quirks;
};
+/**
+ * struct timing_regs - AXI I2C timing registers that depend on I2C spec
+ * @tsusta: setup time for a repeated START condition
+ * @tsusto: setup time for a STOP condition
+ * @thdsta: hold time for a repeated START condition
+ * @tsudat: setup time for data
+ * @tbuf: bus free time between STOP and START
+ */
+struct timing_regs {
+ unsigned int tsusta;
+ unsigned int tsusto;
+ unsigned int thdsta;
+ unsigned int tsudat;
+ unsigned int tbuf;
+};
+
+/* Reg values in ns derived from I2C spec and AXI I2C PG for different frequencies */
+static const struct timing_regs timing_reg_values[] = {
+ { 5700, 5000, 4300, 550, 5000 }, /* Reg values for 100KHz */
+ { 900, 900, 900, 400, 1600 }, /* Reg values for 400KHz */
+ { 380, 380, 380, 170, 620 }, /* Reg values for 1MHz */
+};
+
#define XIIC_MSB_OFFSET 0
#define XIIC_REG_OFFSET (0x100 + XIIC_MSB_OFFSET)
@@ -110,6 +143,19 @@ struct xiic_version_data {
#define XIIC_RFD_REG_OFFSET (0x20 + XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
#define XIIC_GPO_REG_OFFSET (0x24 + XIIC_REG_OFFSET) /* Output Register */
+/*
+ * Timing register offsets from RegisterBase. These are used only for
+ * setting i2c clock frequency for the line.
+ */
+#define XIIC_TSUSTA_REG_OFFSET (0x28 + XIIC_REG_OFFSET) /* TSUSTA Register */
+#define XIIC_TSUSTO_REG_OFFSET (0x2C + XIIC_REG_OFFSET) /* TSUSTO Register */
+#define XIIC_THDSTA_REG_OFFSET (0x30 + XIIC_REG_OFFSET) /* THDSTA Register */
+#define XIIC_TSUDAT_REG_OFFSET (0x34 + XIIC_REG_OFFSET) /* TSUDAT Register */
+#define XIIC_TBUF_REG_OFFSET (0x38 + XIIC_REG_OFFSET) /* TBUF Register */
+#define XIIC_THIGH_REG_OFFSET (0x3C + XIIC_REG_OFFSET) /* THIGH Register */
+#define XIIC_TLOW_REG_OFFSET (0x40 + XIIC_REG_OFFSET) /* TLOW Register */
+#define XIIC_THDDAT_REG_OFFSET (0x44 + XIIC_REG_OFFSET) /* THDDAT Register */
+
/* Control Register masks */
#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
@@ -310,12 +356,102 @@ static int xiic_wait_tx_empty(struct xiic_i2c *i2c)
return 0;
}
+/**
+ * xiic_setclk - Sets the configured clock rate
+ * @i2c: Pointer to the xiic device structure
+ *
+ * The timing register values are calculated according to the input clock
+ * frequency and configured scl frequency. For details, please refer the
+ * AXI I2C PG and NXP I2C Spec.
+ * Supported frequencies are 100KHz, 400KHz and 1MHz.
+ *
+ * Return: 0 on success (Supported frequency selected or not configurable in SW)
+ * -EINVAL on failure (scl frequency not supported or THIGH is 0)
+ */
+static int xiic_setclk(struct xiic_i2c *i2c)
+{
+ unsigned int clk_in_mhz;
+ unsigned int index = 0;
+ u32 reg_val;
+
+ dev_dbg(i2c->adap.dev.parent,
+ "%s entry, i2c->input_clk: %ld, i2c->i2c_clk: %d\n",
+ __func__, i2c->input_clk, i2c->i2c_clk);
+
+ /* If not specified in DT, do not configure in SW. Rely only on Vivado design */
+ if (!i2c->i2c_clk || !i2c->input_clk)
+ return 0;
+
+ clk_in_mhz = DIV_ROUND_UP(i2c->input_clk, 1000000);
+
+ switch (i2c->i2c_clk) {
+ case I2C_MAX_FAST_MODE_PLUS_FREQ:
+ index = REG_VALUES_1MHZ;
+ break;
+ case I2C_MAX_FAST_MODE_FREQ:
+ index = REG_VALUES_400KHZ;
+ break;
+ case I2C_MAX_STANDARD_MODE_FREQ:
+ index = REG_VALUES_100KHZ;
+ break;
+ default:
+ dev_warn(i2c->adap.dev.parent, "Unsupported scl frequency\n");
+ return -EINVAL;
+ }
+
+ /*
+ * Value to be stored in a register is the number of clock cycles required
+ * for the time duration. So the time is divided by the input clock time
+ * period to get the number of clock cycles required. Refer Xilinx AXI I2C
+ * PG document and I2C specification for further details.
+ */
+
+ /* THIGH - Depends on SCL clock frequency(i2c_clk) as below */
+ reg_val = (DIV_ROUND_UP(i2c->input_clk, 2 * i2c->i2c_clk)) - 7;
+ if (reg_val == 0)
+ return -EINVAL;
+
+ xiic_setreg32(i2c, XIIC_THIGH_REG_OFFSET, reg_val - 1);
+
+ /* TLOW - Value same as THIGH */
+ xiic_setreg32(i2c, XIIC_TLOW_REG_OFFSET, reg_val - 1);
+
+ /* TSUSTA */
+ reg_val = (timing_reg_values[index].tsusta * clk_in_mhz) / 1000;
+ xiic_setreg32(i2c, XIIC_TSUSTA_REG_OFFSET, reg_val - 1);
+
+ /* TSUSTO */
+ reg_val = (timing_reg_values[index].tsusto * clk_in_mhz) / 1000;
+ xiic_setreg32(i2c, XIIC_TSUSTO_REG_OFFSET, reg_val - 1);
+
+ /* THDSTA */
+ reg_val = (timing_reg_values[index].thdsta * clk_in_mhz) / 1000;
+ xiic_setreg32(i2c, XIIC_THDSTA_REG_OFFSET, reg_val - 1);
+
+ /* TSUDAT */
+ reg_val = (timing_reg_values[index].tsudat * clk_in_mhz) / 1000;
+ xiic_setreg32(i2c, XIIC_TSUDAT_REG_OFFSET, reg_val - 1);
+
+ /* TBUF */
+ reg_val = (timing_reg_values[index].tbuf * clk_in_mhz) / 1000;
+ xiic_setreg32(i2c, XIIC_TBUF_REG_OFFSET, reg_val - 1);
+
+ /* THDDAT */
+ xiic_setreg32(i2c, XIIC_THDDAT_REG_OFFSET, 1);
+
+ return 0;
+}
+
static int xiic_reinit(struct xiic_i2c *i2c)
{
int ret;
xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
+ ret = xiic_setclk(i2c);
+ if (ret)
+ return ret;
+
/* Set receive Fifo depth to maximum (zero based). */
xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
@@ -1138,6 +1274,15 @@ static int xiic_i2c_probe(struct platform_device *pdev)
pm_runtime_use_autosuspend(i2c->dev);
pm_runtime_set_active(i2c->dev);
pm_runtime_enable(i2c->dev);
+
+ /* SCL frequency configuration */
+ i2c->input_clk = clk_get_rate(i2c->clk);
+ ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
+ &i2c->i2c_clk);
+ /* If clock-frequency not specified in DT, do not configure in SW */
+ if (ret || i2c->i2c_clk > I2C_MAX_FAST_MODE_PLUS_FREQ)
+ i2c->i2c_clk = 0;
+
ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
xiic_process, IRQF_ONESHOT,
pdev->name, i2c);
@@ -1181,6 +1326,9 @@ static int xiic_i2c_probe(struct platform_device *pdev)
i2c_new_client_device(&i2c->adap, pdata->devices + i);
}
+ dev_dbg(&pdev->dev, "mmio %08lx irq %d scl clock frequency %d\n",
+ (unsigned long)res->start, irq, i2c->i2c_clk);
+
return 0;
err_clk_dis:
--
2.25.1
On 15/02/2023 14:32, Manikanta Guntupalli wrote:
> From: Raviteja Narayanam <[email protected]>
>
> Add xilinx I2C new version 'xlnx,axi-iic-2.1' string to compatible.
> Add clock-frequency as optional property.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Wed, Feb 15, 2023 at 07:02:22PM +0530, Manikanta Guntupalli wrote:
> From: Raviteja Narayanam <[email protected]>
>
> Add xilinx I2C new version 'xlnx,axi-iic-2.1' string to compatible.
> Add clock-frequency as optional property.
>
> Signed-off-by: Raviteja Narayanam <[email protected]>
> Signed-off-by: Manikanta Guntupalli <[email protected]>
> Acked-by: Michal Simek <[email protected]>
Applied to for-next, thanks!
On Wed, Feb 15, 2023 at 07:02:23PM +0530, Manikanta Guntupalli wrote:
> From: Raviteja Narayanam <[email protected]>
>
> Xilinx AXI I2C IP is updated with a bug fix for dynamic mode reads.
> Older IPs are handled with a workaround in which they are using
> xiic standard mode for all these effected use cases.
> Add the new IP version to compatible.
>
> Signed-off-by: Raviteja Narayanam <[email protected]>
> Signed-off-by: Manikanta Guntupalli <[email protected]>
> Acked-by: Michal Simek <[email protected]>
Applied to for-next, thanks!
On Wed, Feb 15, 2023 at 07:02:24PM +0530, Manikanta Guntupalli wrote:
> From: Raviteja Narayanam <[email protected]>
>
> From 'clock-frequency' device tree property, configure I2C SCL
> frequency by calculating the timing register values according to
> input clock.
>
> After soft reset in reinit function, the timing registers are set
> to default values (configured in design tool). So, setting SCL
> frequency is done inside reinit function after the soft reset.
> This allows configuration of SCL frequency exclusively through
> software via device tree property, overriding the design.
> If the clock-frequency parameter is not specified in DT, driver
> doesn't configure frequency, making it backward compatible.
>
> Signed-off-by: Raviteja Narayanam <[email protected]>
> Signed-off-by: Manikanta Guntupalli <[email protected]>
> Acked-by: Michal Simek <[email protected]>
Applied to for-next, thanks!