Bring in bindings and the dt part for SM6115 GPU SMMU
Depends on:
https://lore.kernel.org/linux-arm-msm/[email protected]/
[2/2] only addresses 6115, 6125 will be sent separately after some dt cleanups there
WARNING:
[1/2] WILL apply without the dependency, HOWEVER it will not make much sense
Signed-off-by: Konrad Dybcio <[email protected]>
---
Konrad Dybcio (2):
dt-bindings: arm-smmu: Document SM61[12]5 GPU SMMU
arm64: dts: qcom: sm6115: Add GPUCC and Adreno SMMU
.../devicetree/bindings/iommu/arm,smmu.yaml | 28 ++++++++++++++--
arch/arm64/boot/dts/qcom/sm6115.dtsi | 38 ++++++++++++++++++++++
2 files changed, 64 insertions(+), 2 deletions(-)
---
base-commit: 062337f0f153c686835cefdb4f937b63fa03edb6
change-id: 20230315-topic-kamorta_adrsmmu-e4e09e01e0da
Best regards,
--
Konrad Dybcio <[email protected]>
Both of these SoCs have a Qualcomm MMU500 implementation of SMMU
in front of their GPUs that expect 3 clocks. Both of them also have
an APPS SMMU that expects no clocks. Remove qcom,sm61[12]5-smmu-500
from the "no clocks" list (intentionally 'breaking' the schema checks
of APPS SMMU, as now it *can* accept clocks - with the current
structure of this file it would have taken a wastefully-long time to
sort this out properly..) and add necessary yaml to describe the
clocks required by the GPU SMMUs.
Signed-off-by: Konrad Dybcio <[email protected]>
---
.../devicetree/bindings/iommu/arm,smmu.yaml | 28 ++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index a6224b7e5310..62c7a5ff148e 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -79,6 +79,8 @@ properties:
items:
- enum:
- qcom,sc7280-smmu-500
+ - qcom,sm6115-smmu-500
+ - qcom,sm6125-smmu-500
- qcom,sm8150-smmu-500
- qcom,sm8250-smmu-500
- qcom,sm8350-smmu-500
@@ -375,6 +377,30 @@ allOf:
- description: interface clock required to access smmu's registers
through the TCU's programming interface.
+ - if:
+ properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,sm6115-smmu-500
+ - qcom,sm6125-smmu-500
+ - const: qcom,adreno-smmu
+ - const: qcom,smmu-500
+ - const: arm,mmu-500
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: mem
+ - const: hlos
+ - const: iface
+
+ clocks:
+ items:
+ - description: GPU memory bus clock
+ - description: Voter clock required for HLOS SMMU access
+ - description: Interface clock required for register access
+
# Disallow clocks for all other platforms with specific compatibles
- if:
properties:
@@ -394,8 +420,6 @@ allOf:
- qcom,sdm845-smmu-500
- qcom,sdx55-smmu-500
- qcom,sdx65-smmu-500
- - qcom,sm6115-smmu-500
- - qcom,sm6125-smmu-500
- qcom,sm6350-smmu-500
- qcom,sm6375-smmu-500
- qcom,sm8350-smmu-500
--
2.39.2
Add GPUCC and Adreno SMMU nodes in preparation for adding the GPU
itself.
Signed-off-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 38 ++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index c56738633431..c1844abc4d9f 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
#include <dt-bindings/clock/qcom,sm6115-dispcc.h>
+#include <dt-bindings/clock/qcom,sm6115-gpucc.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h>
@@ -1135,6 +1136,43 @@ usb_1_dwc3: usb@4e00000 {
};
};
+ gpucc: clock-controller@5990000 {
+ compatible = "qcom,sm6115-gpucc";
+ reg = <0x0 0x05990000 0x0 0x9000>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ adreno_smmu: iommu@59a0000 {
+ compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu",
+ "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x059a0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
+ clock-names = "mem",
+ "hlos",
+ "iface";
+ power-domains = <&gpucc GPU_CX_GDSC>;
+
+ #global-interrupts = <1>;
+ #iommu-cells = <2>;
+ };
+
mdss: display-subsystem@5e00000 {
compatible = "qcom,sm6115-mdss";
reg = <0x0 0x05e00000 0x0 0x1000>;
--
2.39.2
On 15/03/2023 11:52, Konrad Dybcio wrote:
> Both of these SoCs have a Qualcomm MMU500 implementation of SMMU
> in front of their GPUs that expect 3 clocks. Both of them also have
> an APPS SMMU that expects no clocks. Remove qcom,sm61[12]5-smmu-500
> from the "no clocks" list (intentionally 'breaking' the schema checks
> of APPS SMMU, as now it *can* accept clocks - with the current
> structure of this file it would have taken a wastefully-long time to
> sort this out properly..) and add necessary yaml to describe the
> clocks required by the GPU SMMUs.
> + properties:
> + compatible:
> + items:
> + - enum:
> + - qcom,sm6115-smmu-500
> + - qcom,sm6125-smmu-500
> + - const: qcom,adreno-smmu
> + - const: qcom,smmu-500
> + - const: arm,mmu-500
If you drop the hunk later (from allOf:if), then what clocks do you
expect for non-GPU SMMU?
> + then:
> + properties:
> + clock-names:
> + items:
> + - const: mem
> + - const: hlos
> + - const: iface
> +
> + clocks:
> + items:
> + - description: GPU memory bus clock
> + - description: Voter clock required for HLOS SMMU access
> + - description: Interface clock required for register access
> +
> # Disallow clocks for all other platforms with specific compatibles
> - if:
> properties:
> @@ -394,8 +420,6 @@ allOf:
> - qcom,sdm845-smmu-500
> - qcom,sdx55-smmu-500
> - qcom,sdx65-smmu-500
> - - qcom,sm6115-smmu-500
> - - qcom,sm6125-smmu-500
> - qcom,sm6350-smmu-500
> - qcom,sm6375-smmu-500
> - qcom,sm8350-smmu-500
>
Best regards,
Krzysztof
On 16.03.2023 20:29, Krzysztof Kozlowski wrote:
> On 15/03/2023 11:52, Konrad Dybcio wrote:
>> Both of these SoCs have a Qualcomm MMU500 implementation of SMMU
>> in front of their GPUs that expect 3 clocks. Both of them also have
>> an APPS SMMU that expects no clocks. Remove qcom,sm61[12]5-smmu-500
>> from the "no clocks" list (intentionally 'breaking' the schema checks
>> of APPS SMMU, as now it *can* accept clocks - with the current
>> structure of this file it would have taken a wastefully-long time to
>> sort this out properly..) and add necessary yaml to describe the
>> clocks required by the GPU SMMUs.
>
>
>> + properties:
>> + compatible:
>> + items:
>> + - enum:
>> + - qcom,sm6115-smmu-500
>> + - qcom,sm6125-smmu-500
>> + - const: qcom,adreno-smmu
>> + - const: qcom,smmu-500
>> + - const: arm,mmu-500
>
> If you drop the hunk later (from allOf:if), then what clocks do you
> expect for non-GPU SMMU?
Both 6115 and 6125 require no clocks under the APPS (non-GPU) SMMU.
However, the list below uses a `contains:` which means I'd have
to add a whole another hunk like
- items:
- enum:
- qcom,sm6115-smmu-500
- qcom,sm6125-smmu-500
- const: qcom,smmu-500
- const: arm,mmu-500
and add another level of indentation to the previous one
I figured skipping that was less messy (I think we discussed this
once as well), but if you prefer to keep it strict, I can.
Konrad
>
>> + then:
>> + properties:
>> + clock-names:
>> + items:
>> + - const: mem
>> + - const: hlos
>> + - const: iface
>> +
>> + clocks:
>> + items:
>> + - description: GPU memory bus clock
>> + - description: Voter clock required for HLOS SMMU access
>> + - description: Interface clock required for register access
>> +
>> # Disallow clocks for all other platforms with specific compatibles
>> - if:
>> properties:
>> @@ -394,8 +420,6 @@ allOf:
>> - qcom,sdm845-smmu-500
>> - qcom,sdx55-smmu-500
>> - qcom,sdx65-smmu-500
>> - - qcom,sm6115-smmu-500
>> - - qcom,sm6125-smmu-500
>> - qcom,sm6350-smmu-500
>> - qcom,sm6375-smmu-500
>> - qcom,sm8350-smmu-500
>>
>
> Best regards,
> Krzysztof
>
On 16/03/2023 22:59, Konrad Dybcio wrote:
>
>
> On 16.03.2023 20:29, Krzysztof Kozlowski wrote:
>> On 15/03/2023 11:52, Konrad Dybcio wrote:
>>> Both of these SoCs have a Qualcomm MMU500 implementation of SMMU
>>> in front of their GPUs that expect 3 clocks. Both of them also have
>>> an APPS SMMU that expects no clocks. Remove qcom,sm61[12]5-smmu-500
>>> from the "no clocks" list (intentionally 'breaking' the schema checks
>>> of APPS SMMU, as now it *can* accept clocks - with the current
>>> structure of this file it would have taken a wastefully-long time to
>>> sort this out properly..) and add necessary yaml to describe the
>>> clocks required by the GPU SMMUs.
>>
>>
>>> + properties:
>>> + compatible:
>>> + items:
>>> + - enum:
>>> + - qcom,sm6115-smmu-500
>>> + - qcom,sm6125-smmu-500
>>> + - const: qcom,adreno-smmu
>>> + - const: qcom,smmu-500
>>> + - const: arm,mmu-500
>>
>> If you drop the hunk later (from allOf:if), then what clocks do you
>> expect for non-GPU SMMU?
> Both 6115 and 6125 require no clocks under the APPS (non-GPU) SMMU.
> However, the list below uses a `contains:` which means I'd have
> to add a whole another hunk like
>
> - items:
> - enum:
> - qcom,sm6115-smmu-500
> - qcom,sm6125-smmu-500
> - const: qcom,smmu-500
> - const: arm,mmu-500
>
> and add another level of indentation to the previous one
>
> I figured skipping that was less messy (I think we discussed this
> once as well), but if you prefer to keep it strict, I can.
Nah, ok, it's fine.
Best regards,
Krzysztof
On 15/03/2023 11:52, Konrad Dybcio wrote:
> Both of these SoCs have a Qualcomm MMU500 implementation of SMMU
> in front of their GPUs that expect 3 clocks. Both of them also have
> an APPS SMMU that expects no clocks. Remove qcom,sm61[12]5-smmu-500
> from the "no clocks" list (intentionally 'breaking' the schema checks
> of APPS SMMU, as now it *can* accept clocks - with the current
> structure of this file it would have taken a wastefully-long time to
> sort this out properly..) and add necessary yaml to describe the
> clocks required by the GPU SMMUs.
>
> Signed-off-by: Konrad Dybcio <[email protected]>
> ---
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Wed, 15 Mar 2023 11:52:07 +0100, Konrad Dybcio wrote:
> Bring in bindings and the dt part for SM6115 GPU SMMU
>
> Depends on:
> https://lore.kernel.org/linux-arm-msm/[email protected]/
>
> [2/2] only addresses 6115, 6125 will be sent separately after some dt cleanups there
>
> [...]
Applied bindings change to will (for-joerg/arm-smmu/bindings), thanks!
[1/2] dt-bindings: arm-smmu: Document SM61[12]5 GPU SMMU
https://git.kernel.org/will/c/3ad6585509dc
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
On Wed, 15 Mar 2023 11:52:07 +0100, Konrad Dybcio wrote:
> Bring in bindings and the dt part for SM6115 GPU SMMU
>
> Depends on:
> https://lore.kernel.org/linux-arm-msm/[email protected]/
>
> [2/2] only addresses 6115, 6125 will be sent separately after some dt cleanups there
>
> [...]
Applied, thanks!
[2/2] arm64: dts: qcom: sm6115: Add GPUCC and Adreno SMMU
commit: fc7c39d61cf8cd03e197ac492241fa5a007dd2c0
Best regards,
--
Bjorn Andersson <[email protected]>