Changes since v6:
* Rebased on top of Besar's updated patch
[PATCH v6] perf: arm_cspmu: Separate Arm and vendor module
https://lore.kernel.org/all/[email protected]/
* Changed Ampere specific module to use ida/ida_alloc() instead of idr/idr_alloc()
Changes since v5:
* Implemented the needed parts for vendor registration API
* Rebased on top of Besar's patch
[PATCH v5] perf: arm_cspmu: Separate Arm and vendor module
https://lore.kernel.org/all/[email protected]/
* v5: https://lore.kernel.org/all/[email protected]/
Changes since v4:
* "Support implementation specific filters" patch:
- Added comment about filter and impdef registers and reference
to the Coresight PMU specification to the commit message
* "Add support for Ampere SoC PMU" patch:
- Fixed the documentation and added more comments
- Changed the incrementing PMU index number to idr_alloc()
(Needs a impdef release hook patch to release unused index)
- Fixed style in init_ops() to more reasonable
- Moved bank parameter to config1
Changes since v3:
* use_64b_counter_reg => has_atomic_dword (patch 1/4)
* Removed the unnecessary hook for group validation (patch 3/4)
* Added group config validation to ampere_cspmu_validate_event() (patch 4/4)
* Rebased the patchset
Changes since v2:
* Changed to use supports_64bits_atomics() and replaced the split writes
with lo_hi_writeq()
* Added implementation specific group validation to patch 3
* Dropped shared interrupt patch
* Removed unnecessary filter_enable parameter from ampere module
* Added group validation to ampere module
Changes since v1:
* Rather than creating a completely new driver, implemented as a submodule
of Arm CoreSight PMU driver
* Fixed shared filter handling
Ilkka Koskinen (4):
perf: arm_cspmu: Split 64-bit write to 32-bit writes
perf: arm_cspmu: Support implementation specific filters
perf: arm_cspmu: Support implementation specific validation
perf: arm_cspmu: ampere_cspmu: Add support for Ampere SoC PMU
.../admin-guide/perf/ampere_cspmu.rst | 29 ++
drivers/perf/arm_cspmu/Kconfig | 10 +
drivers/perf/arm_cspmu/Makefile | 2 +
drivers/perf/arm_cspmu/ampere_cspmu.c | 271 ++++++++++++++++++
drivers/perf/arm_cspmu/arm_cspmu.c | 33 ++-
drivers/perf/arm_cspmu/arm_cspmu.h | 7 +
6 files changed, 346 insertions(+), 6 deletions(-)
create mode 100644 Documentation/admin-guide/perf/ampere_cspmu.rst
create mode 100644 drivers/perf/arm_cspmu/ampere_cspmu.c
--
2.40.1
Split the 64-bit register accesses if 64-bit access is not supported
by the PMU.
Signed-off-by: Ilkka Koskinen <[email protected]>
Reviewed-by: Besar Wicaksono <[email protected]>
Reviewed-by: Suzuki K Poulose <[email protected]>
---
drivers/perf/arm_cspmu/arm_cspmu.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/arm_cspmu.c
index c59f1e5a35a3..5f4f04135a22 100644
--- a/drivers/perf/arm_cspmu/arm_cspmu.c
+++ b/drivers/perf/arm_cspmu/arm_cspmu.c
@@ -719,7 +719,10 @@ static void arm_cspmu_write_counter(struct perf_event *event, u64 val)
if (use_64b_counter_reg(cspmu)) {
offset = counter_offset(sizeof(u64), event->hw.idx);
- writeq(val, cspmu->base1 + offset);
+ if (cspmu->has_atomic_dword)
+ writeq(val, cspmu->base1 + offset);
+ else
+ lo_hi_writeq(val, cspmu->base1 + offset);
} else {
offset = counter_offset(sizeof(u32), event->hw.idx);
--
2.40.1
Some platforms may use e.g. different filtering mechanism and, thus,
may need different way to validate the events and group.
Signed-off-by: Ilkka Koskinen <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Suzuki K Poulose <[email protected]>
---
drivers/perf/arm_cspmu/arm_cspmu.c | 8 +++++++-
drivers/perf/arm_cspmu/arm_cspmu.h | 3 +++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/arm_cspmu.c
index 2ecbf8d7714b..1ba00d640352 100644
--- a/drivers/perf/arm_cspmu/arm_cspmu.c
+++ b/drivers/perf/arm_cspmu/arm_cspmu.c
@@ -576,7 +576,7 @@ static void arm_cspmu_disable(struct pmu *pmu)
static int arm_cspmu_get_event_idx(struct arm_cspmu_hw_events *hw_events,
struct perf_event *event)
{
- int idx;
+ int idx, ret;
struct arm_cspmu *cspmu = to_arm_cspmu(event->pmu);
if (supports_cycle_counter(cspmu)) {
@@ -610,6 +610,12 @@ static int arm_cspmu_get_event_idx(struct arm_cspmu_hw_events *hw_events,
if (idx >= cspmu->num_logical_ctrs)
return -EAGAIN;
+ if (cspmu->impl.ops.validate_event) {
+ ret = cspmu->impl.ops.validate_event(cspmu, event);
+ if (ret)
+ return ret;
+ }
+
set_bit(idx, hw_events->used_ctrs);
return idx;
diff --git a/drivers/perf/arm_cspmu/arm_cspmu.h b/drivers/perf/arm_cspmu/arm_cspmu.h
index e0cca5b4aab9..a30c8372214c 100644
--- a/drivers/perf/arm_cspmu/arm_cspmu.h
+++ b/drivers/perf/arm_cspmu/arm_cspmu.h
@@ -107,6 +107,9 @@ struct arm_cspmu_impl_ops {
/* Set event filter */
void (*set_ev_filter)(struct arm_cspmu *cspmu,
struct hw_perf_event *hwc, u32 filter);
+ /* Implementation specific event validation */
+ int (*validate_event)(struct arm_cspmu *cspmu,
+ struct perf_event *event);
/* Hide/show unsupported events */
umode_t (*event_attr_is_visible)(struct kobject *kobj,
struct attribute *attr, int unused);
--
2.40.1
On Wed, 13 Sep 2023 16:39:37 -0700, Ilkka Koskinen wrote:
> Changes since v6:
> * Rebased on top of Besar's updated patch
>
> [PATCH v6] perf: arm_cspmu: Separate Arm and vendor module
> https://lore.kernel.org/all/[email protected]/
>
> * Changed Ampere specific module to use ida/ida_alloc() instead of idr/idr_alloc()
>
> [...]
Applied to will (for-next/perf), thanks!
[1/4] perf: arm_cspmu: Split 64-bit write to 32-bit writes
https://git.kernel.org/will/c/8c282414ca62
[2/4] perf: arm_cspmu: Support implementation specific filters
https://git.kernel.org/will/c/0a7603ab242e
[3/4] perf: arm_cspmu: Support implementation specific validation
https://git.kernel.org/will/c/647d5c5a9e76
[4/4] perf: arm_cspmu: ampere_cspmu: Add support for Ampere SoC PMU
https://git.kernel.org/will/c/290a9c0e55f8
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev