From: Elad Nachman <[email protected]>
Add support for CN9130 and CN9131 COM Express Type 7 CPU
module boards by Marvell.
Define these COM Express CPU modules as dtsi, and
provide a dtsi file for a carrier board (Marvell AC5X RD
COM Express type 7 carrier board).
This Carrier board only utilizes the PCIe link, hence no
special device / driver support is provided by this dtsi file.
Finally, add dts file for the combined carrier and CPU module.
v4:
1) reorder patches - dt bindings before dts/dtsi files
2) correct description in dt bindings
3) separate dt bindings for CPU module, carrier and combination
4) make carrier board dts into dtsi, make dts for combination of
carrier and CPU module
5) correct compatibility strings and file names to use dashes
instead of underscores
v3:
1) Remove acronym which creates warnings for checkpatch.pl
2) Correct compatibility string for ac5x rd board
3) Add above compatibility string to dt bindings
4) update MAINTAINERS file with ac5 series dts files
5) remove memory property from carrier dts
6) add comment explaining that OOB RGMII ethernet port
connector and PHY are both on CPU module
v2:
1) add compatibility string for the board
2) remove unneeded hard-coded PHY LED blinking mode initialization
3) Split the CPU portion of the carrier board to
dtsi files, and define a dts file for the AC5X RD
carrier board.
Elad Nachman (3):
MAINTAINERS: add ac5 to list of maintained Marvell dts files
dt-bindings: arm64: dts: add dt-bindings for Marvell COM Express
boards
arm64: dts: cn913x: add device trees for COM Express boards
.../bindings/arm/marvell/armada-7k-8k.yaml | 15 +++
.../bindings/arm/marvell/marvell,ac5.yaml | 14 +++
MAINTAINERS | 1 +
arch/arm64/boot/dts/marvell/Makefile | 1 +
.../marvell/ac5x-rd-carrier-with-cn9131.dts | 19 +++
.../boot/dts/marvell/ac5x-rd-carrier.dtsi | 18 +++
.../dts/marvell/cn9130-db-comexpress.dtsi | 101 ++++++++++++++++
.../dts/marvell/cn9131-db-comexpress.dtsi | 113 ++++++++++++++++++
8 files changed, 282 insertions(+)
create mode 100644 arch/arm64/boot/dts/marvell/ac5x-rd-carrier-with-cn9131.dts
create mode 100644 arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi
--
2.25.1
From: Elad Nachman <[email protected]>
Add ac5 dts files to the list of maintained Marvell Armada dts files
Signed-off-by: Elad Nachman <[email protected]>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index bdc4638b2df5..199225588567 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2323,6 +2323,7 @@ F: arch/arm/boot/dts/marvell/armada*
F: arch/arm/boot/dts/marvell/kirkwood*
F: arch/arm/configs/mvebu_*_defconfig
F: arch/arm/mach-mvebu/
+F: arch/arm64/boot/dts/marvell/ac5*
F: arch/arm64/boot/dts/marvell/armada*
F: arch/arm64/boot/dts/marvell/cn913*
F: drivers/clk/mvebu/
--
2.25.1
From: Elad Nachman <[email protected]>
Add support for CN9130 and CN9131 COM Express Type 7 CPU
module boards by Marvell.
Define these COM Express CPU modules as dtsi and
provide a dtsi file for a carrier board (Marvell AC5X RD
COM Express type 7 carrier board).
This Carrier board only utilizes the PCIe link, hence no
special device / driver support is provided by this dtsi file.
Finally, provide a dts file for the com express carrier and
CPU module combination.
These COM Express boards differ from the existing CN913x DB
boards by the type of ethernet connection (RGMII),
the type of voltage regulators (not i2c expander based)
and the USB phy (not UTMI based).
Note - PHY + RGMII connector is OOB on CPU module.
CN9131 COM Express board is basically CN9130 COM Express board
with an additional CP115 I/O co-processor, which in this case
provides an additional USB host controller on the board.
Signed-off-by: Elad Nachman <[email protected]>
---
arch/arm64/boot/dts/marvell/Makefile | 1 +
.../marvell/ac5x-rd-carrier-with-cn9131.dts | 20 ++++
.../boot/dts/marvell/ac5x-rd-carrier.dtsi | 15 +++
.../dts/marvell/cn9130-db-comexpress.dtsi | 101 ++++++++++++++++
.../dts/marvell/cn9131-db-comexpress.dtsi | 113 ++++++++++++++++++
5 files changed, 250 insertions(+)
create mode 100644 arch/arm64/boot/dts/marvell/ac5x-rd-carrier-with-cn9131.dts
create mode 100644 arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi
diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
index 79ac09b58a89..88c0f357a778 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -26,4 +26,5 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += ac5x-rd-carrier-with-cn9131.dtb
dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb
diff --git a/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-with-cn9131.dts b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-with-cn9131.dts
new file mode 100644
index 000000000000..9ca2725184e2
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-with-cn9131.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 Marvell International Ltd.
+ *
+ * Device tree for the AC5X RD Type 7 Com Express carrier board,
+ * Utilizing the CN913x COM Express CPU module board.
+ * This specific board only maintains a PCIe link with the CPU CPU module
+ * module, which does not require any special DTS definitions.
+ */
+
+#include "cn9131-db-comexpress.dtsi"
+#include "ac5x-rd-carrier.dtsi"
+
+/ {
+ model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board with CN9131 CPU module";
+ compatible = "marvell,rd-ac5x-carrier-with-cn9131", "marvell,rd-ac5x-carrier",
+ "marvell,cn9131", "marvell,cn9130",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+};
diff --git a/arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi
new file mode 100644
index 000000000000..6d976d268deb
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 Marvell International Ltd.
+ *
+ * Device tree for the AC5X RD Type 7 Com Express carrier board,
+ * This specific board only maintains a PCIe link with the CPU CPU module
+ * module, which does not require any special DTS definitions.
+ */
+
+/ {
+ model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board";
+ compatible = "marvell,rd-ac5x-carrier", "marvell,cn9131", "marvell,cn9130",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+};
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
new file mode 100644
index 000000000000..1180066a3cf2
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 Marvell International Ltd.
+ *
+ * Device tree for the CN9130-DB Com Express CPU module board.
+ */
+
+#include "cn9130-db.dtsi"
+
+/ {
+ model = "Marvell Armada CN9130-DB COM EXPRESS type 7 CPU module board";
+ compatible = "marvell,cn9130-cpu-module", "marvell,cn9130",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x2 0x00000000>;
+ };
+
+};
+
+&ap0_reg_sd_vccq {
+ regulator-max-microvolt = <1800000>;
+ states = <1800000 0x1 1800000 0x0>;
+ /delete-property/ gpios;
+};
+
+&cp0_reg_usb3_vbus0 {
+ /delete-property/ gpio;
+};
+
+&cp0_reg_usb3_vbus1 {
+ /delete-property/ gpio;
+};
+
+&cp0_reg_sd_vcc {
+ status = "disabled";
+};
+
+&cp0_reg_sd_vccq {
+ status = "disabled";
+};
+
+&cp0_sdhci0 {
+ status = "disabled";
+};
+
+&cp0_eth0 {
+ status = "disabled";
+};
+
+&cp0_eth1 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
+&cp0_eth2 {
+ status = "disabled";
+};
+
+&cp0_mdio {
+ status = "okay";
+ pinctrl-0 = <&cp0_ge_mdio_pins>;
+ phy0: ethernet-phy@0 {
+ status = "okay";
+ };
+};
+
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp0_ge_mdio_pins: ge-mdio-pins {
+ marvell,pins = "mpp40", "mpp41";
+ marvell,function = "ge";
+ };
+ };
+};
+
+&cp0_sdhci0 {
+ status = "disabled";
+};
+
+&cp0_spi1 {
+ status = "okay";
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy0>;
+ phy-names = "usb";
+ /delete-property/ phys;
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy1>;
+ phy-names = "usb";
+ /delete-property/ phys;
+};
diff --git a/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi
new file mode 100644
index 000000000000..0d2d2a119253
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2023 Marvell International Ltd.
+ *
+ * Device tree for the CN9131-DB Com Express CPU module board.
+ */
+
+#include "cn9131-db.dtsi"
+
+/ {
+ model = "Marvell Armada CN9131-DB COM EXPRESS type 7 CPU module board";
+ compatible = "marvell,cn9131-cpu-module", "marvell,cn9131", "marvell,cn9130",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x2 0x00000000>;
+ };
+
+};
+
+&ap0_reg_sd_vccq {
+ regulator-max-microvolt = <1800000>;
+ states = <1800000 0x1 1800000 0x0>;
+ /delete-property/ gpios;
+};
+
+&cp0_reg_usb3_vbus0 {
+ /delete-property/ gpio;
+};
+
+&cp0_reg_usb3_vbus1 {
+ /delete-property/ gpio;
+};
+
+&cp1_reg_usb3_vbus0 {
+ /delete-property/ gpio;
+};
+
+&cp0_reg_sd_vcc {
+ status = "disabled";
+};
+
+&cp0_reg_sd_vccq {
+ status = "disabled";
+};
+
+&cp0_sdhci0 {
+ status = "disabled";
+};
+
+&cp0_eth0 {
+ status = "disabled";
+};
+
+&cp0_eth1 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
+&cp0_eth2 {
+ status = "disabled";
+};
+
+&cp0_mdio {
+ status = "okay";
+ pinctrl-0 = <&cp0_ge_mdio_pins>;
+ phy0: ethernet-phy@0 {
+ status = "okay";
+ };
+};
+
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp0_ge_mdio_pins: ge-mdio-pins {
+ marvell,pins = "mpp40", "mpp41";
+ marvell,function = "ge";
+ };
+ };
+};
+
+&cp0_sdhci0 {
+ status = "disabled";
+};
+
+&cp0_spi1 {
+ status = "okay";
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy0>;
+ phy-names = "usb";
+ /delete-property/ phys;
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy1>;
+ phy-names = "usb";
+ /delete-property/ phys;
+};
+
+&cp1_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp1_usb3_0_phy0>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy3 1>;
+ phy-names = "usb";
+};
--
2.25.1
From: Elad Nachman <[email protected]>
Add dt bindings for:
CN9130 COM Express CPU module
CN9131 COM Express CPU module
AC5X RD COM Express Type 7 carrier board.
AC5X RD COM Express board with a CN9131 COM Express Type 7 CPU module.
Signed-off-by: Elad Nachman <[email protected]>
---
.../bindings/arm/marvell/armada-7k-8k.yaml | 15 +++++++++++++++
.../bindings/arm/marvell/marvell,ac5.yaml | 14 ++++++++++++++
2 files changed, 29 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml
index 52d78521e412..7e0ac5110eef 100644
--- a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml
+++ b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml
@@ -60,4 +60,19 @@ properties:
- const: marvell,armada-ap807-quad
- const: marvell,armada-ap807
+ - description: Armada CN9130 SoC without external CP as COM Express CPU module
+ items:
+ - const: marvell,cn9130-cpu-module
+ - const: marvell,cn9130
+ - const: marvell,armada-ap807-quad
+ - const: marvell,armada-ap807
+
+ - description: Armada CN9131 SoC with one external CP as COM Express CPU module
+ items:
+ - const: marvell,cn9131-cpu-module
+ - const: marvell,cn9131
+ - const: marvell,cn9130
+ - const: marvell,armada-ap807-quad
+ - const: marvell,armada-ap807
+
additionalProperties: true
diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml b/Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml
index 8960fb8b2b2f..734e1716a3e9 100644
--- a/Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml
+++ b/Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml
@@ -27,6 +27,20 @@ properties:
- const: marvell,ac5x
- const: marvell,ac5
+ - description: Alleycat5X (98DX35xx) Reference Design as COM Express Carrier
+ items:
+ - enum:
+ - marvell,rd-ac5x-carrier
+ - const: marvell,ac5x
+
+ - description:
+ Alleycat5X (98DX35xx) Reference Design as COM Express Carrier plus
+ Armada CN9131 COM Express CPU module
+ items:
+ - enum:
+ - marvell,rd-ac5x-carrier-with-cn9131
+ - const: marvell,ac5x
+
additionalProperties: true
...
--
2.25.1
On Sun, Oct 29, 2023 at 07:48:12PM +0200, Elad Nachman wrote:
> From: Elad Nachman <[email protected]>
>
> Add ac5 dts files to the list of maintained Marvell Armada dts files
>
> Signed-off-by: Elad Nachman <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Andrew
> +++ b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi
> @@ -0,0 +1,15 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2023 Marvell International Ltd.
> + *
> + * Device tree for the AC5X RD Type 7 Com Express carrier board,
> + * This specific board only maintains a PCIe link with the CPU CPU module
> + * module, which does not require any special DTS definitions.
> + */
> +
> +/ {
> + model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board";
> + compatible = "marvell,rd-ac5x-carrier", "marvell,cn9131", "marvell,cn9130",
> + "marvell,armada-ap807-quad", "marvell,armada-ap807";
This sees wrong to me. Say i mount a congatec Module in it. Its then
is not compatible with marvell,cn9131 etc. I think you should just
list the carrier compatible here.
> +#include "cn9130-db.dtsi"
> +
> +/ {
> + model = "Marvell Armada CN9130-DB COM EXPRESS type 7 CPU module board";
> + compatible = "marvell,cn9130-cpu-module", "marvell,cn9130",
> + "marvell,armada-ap807-quad", "marvell,armada-ap807";
> +
> + memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x0 0x2 0x00000000>;
Is the memory soldered down, or socketed?
Andrew
On Sun, 29 Oct 2023 19:48:13 +0200, Elad Nachman wrote:
> From: Elad Nachman <[email protected]>
>
> Add dt bindings for:
> CN9130 COM Express CPU module
> CN9131 COM Express CPU module
> AC5X RD COM Express Type 7 carrier board.
> AC5X RD COM Express board with a CN9131 COM Express Type 7 CPU module.
>
> Signed-off-by: Elad Nachman <[email protected]>
> ---
> .../bindings/arm/marvell/armada-7k-8k.yaml | 15 +++++++++++++++
> .../bindings/arm/marvell/marvell,ac5.yaml | 14 ++++++++++++++
> 2 files changed, 29 insertions(+)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
./Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml:37:12: [warning] wrong indentation: expected 10 but found 11 (indentation)
dtschema/dtc warnings/errors:
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
On Sun, Oct 29, 2023 at 07:48:13PM +0200, Elad Nachman wrote:
> From: Elad Nachman <[email protected]>
Drop 'dts:' from the subject. This is not a .dts file.
Also drop the 2nd 'dt-bindings'. Subject line space is precious.
>
> Add dt bindings for:
> CN9130 COM Express CPU module
> CN9131 COM Express CPU module
> AC5X RD COM Express Type 7 carrier board.
> AC5X RD COM Express board with a CN9131 COM Express Type 7 CPU module.
>
> Signed-off-by: Elad Nachman <[email protected]>
> ---
> .../bindings/arm/marvell/armada-7k-8k.yaml | 15 +++++++++++++++
> .../bindings/arm/marvell/marvell,ac5.yaml | 14 ++++++++++++++
> 2 files changed, 29 insertions(+)
On 29/10/2023 18:48, Elad Nachman wrote:
> From: Elad Nachman <[email protected]>
>
A nit, subject: drop second/last, redundant "dt-bindings for". The
"dt-bindings" prefix is already stating that these are bindings.
> Add dt bindings for:
> CN9130 COM Express CPU module
> CN9131 COM Express CPU module
> AC5X RD COM Express Type 7 carrier board.
> AC5X RD COM Express board with a CN9131 COM Express Type 7 CPU module.
>
> Signed-off-by: Elad Nachman <[email protected]>
> ---
> .../bindings/arm/marvell/armada-7k-8k.yaml | 15 +++++++++++++++
> .../bindings/arm/marvell/marvell,ac5.yaml | 14 ++++++++++++++
> 2 files changed, 29 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml
> index 52d78521e412..7e0ac5110eef 100644
> --- a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml
> +++ b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.yaml
> @@ -60,4 +60,19 @@ properties:
> - const: marvell,armada-ap807-quad
> - const: marvell,armada-ap807
>
> + - description: Armada CN9130 SoC without external CP as COM Express CPU module
> + items:
> + - const: marvell,cn9130-cpu-module
How CPU module can be used alone?
> + - const: marvell,cn9130
> + - const: marvell,armada-ap807-quad
> + - const: marvell,armada-ap807
> +
> + - description: Armada CN9131 SoC with one external CP as COM Express CPU module
> + items:
> + - const: marvell,cn9131-cpu-module
> + - const: marvell,cn9131
> + - const: marvell,cn9130
> + - const: marvell,armada-ap807-quad
> + - const: marvell,armada-ap807
> +
> additionalProperties: true
> diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml b/Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml
> index 8960fb8b2b2f..734e1716a3e9 100644
> --- a/Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml
> +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml
> @@ -27,6 +27,20 @@ properties:
> - const: marvell,ac5x
> - const: marvell,ac5
>
> + - description: Alleycat5X (98DX35xx) Reference Design as COM Express Carrier
> + items:
> + - enum:
> + - marvell,rd-ac5x-carrier
> + - const: marvell,ac5x
> +
> + - description:
> + Alleycat5X (98DX35xx) Reference Design as COM Express Carrier plus
> + Armada CN9131 COM Express CPU module
> + items:
> + - enum:
> + - marvell,rd-ac5x-carrier-with-cn9131
> + - const: marvell,ac5x
You never responded to me concerns, so I still do not know what's this.
This claims it has CN9131, but compatibles are missing.
Can anyone help us understand why AC5 has CN9130 but these are in
different files?
Best regards,
Krzysztof
On 29/10/2023 18:48, Elad Nachman wrote:
> From: Elad Nachman <[email protected]>
>
> Add support for CN9130 and CN9131 COM Express Type 7 CPU
> module boards by Marvell.
> Define these COM Express CPU modules as dtsi and
> provide a dtsi file for a carrier board (Marvell AC5X RD
> COM Express type 7 carrier board).
> This Carrier board only utilizes the PCIe link, hence no
> special device / driver support is provided by this dtsi file.
> Finally, provide a dts file for the com express carrier and
> CPU module combination.
>
> These COM Express boards differ from the existing CN913x DB
> boards by the type of ethernet connection (RGMII),
> the type of voltage regulators (not i2c expander based)
> and the USB phy (not UTMI based).
> Note - PHY + RGMII connector is OOB on CPU module.
> CN9131 COM Express board is basically CN9130 COM Express board
> with an additional CP115 I/O co-processor, which in this case
> provides an additional USB host controller on the board.
>
> Signed-off-by: Elad Nachman <[email protected]>
> ---
> arch/arm64/boot/dts/marvell/Makefile | 1 +
> .../marvell/ac5x-rd-carrier-with-cn9131.dts | 20 ++++
> .../boot/dts/marvell/ac5x-rd-carrier.dtsi | 15 +++
> .../dts/marvell/cn9130-db-comexpress.dtsi | 101 ++++++++++++++++
> .../dts/marvell/cn9131-db-comexpress.dtsi | 113 ++++++++++++++++++
> 5 files changed, 250 insertions(+)
> create mode 100644 arch/arm64/boot/dts/marvell/ac5x-rd-carrier-with-cn9131.dts
> create mode 100644 arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi
> create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
> create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi
>
> diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
> index 79ac09b58a89..88c0f357a778 100644
> --- a/arch/arm64/boot/dts/marvell/Makefile
> +++ b/arch/arm64/boot/dts/marvell/Makefile
> @@ -26,4 +26,5 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb
> dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb
> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb
> +dtb-$(CONFIG_ARCH_MVEBU) += ac5x-rd-carrier-with-cn9131.dtb
> dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb
> diff --git a/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-with-cn9131.dts b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-with-cn9131.dts
> new file mode 100644
> index 000000000000..9ca2725184e2
> --- /dev/null
> +++ b/arch/arm64/boot/dts/marvell/ac5x-rd-carrier-with-cn9131.dts
> @@ -0,0 +1,20 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2023 Marvell International Ltd.
> + *
> + * Device tree for the AC5X RD Type 7 Com Express carrier board,
> + * Utilizing the CN913x COM Express CPU module board.
> + * This specific board only maintains a PCIe link with the CPU CPU module
> + * module, which does not require any special DTS definitions.
> + */
> +
> +#include "cn9131-db-comexpress.dtsi"
> +#include "ac5x-rd-carrier.dtsi"
> +
> +/ {
> + model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board with CN9131 CPU module";
> + compatible = "marvell,rd-ac5x-carrier-with-cn9131", "marvell,rd-ac5x-carrier",
> + "marvell,cn9131", "marvell,cn9130",
> + "marvell,armada-ap807-quad", "marvell,armada-ap807";
So you clearly did not test what you wrote.
This is v4, so at this point testing should be obvious. You must test
your bindings and you must test your DTS against bindings.
Successful test means: ZERO warnings.
Standard disclaimer:
It does not look like you tested the DTS against bindings. Please run
`make dtbs_check W=1` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).
It does not look like you tested the bindings, at least after quick
look. Please run `make dt_binding_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).
Maybe you need to update your dtschema and yamllint.
Best regards,
Krzysztof