From: Atul Dhudase <[email protected]>
Commit c14e64b46944 ("soc: qcom: llcc: Support chipsets that can
write to llcc") add the support for chipset where capacity based
allocation and retention through power collapse can be programmed
based on content of SCT table mentioned in the llcc driver where
the target like sdm845 where the entire programming related to it
is controlled in firmware. However, the commit introduces a bug
where capacity/retention register get overwritten each time it
gets programmed for each slice and that results in misconfiguration
of the register based on SCT table and that is not expected
behaviour instead it should be read modify write to retain the
configuration of other slices.
This issue is totally caught from code review and programming test
and not through any power/perf numbers so, it is not known what
impact this could make if we don't have this change however,
this feature are for these targets and they should have been
programmed accordingly as per their configuration mentioned in
SCT table like others bits information.
This change brings one difference where it keeps capacity/retention
bits of the slices that are not mentioned in SCT table in unknown
state where as earlier it was initialized to zero.
Fixes: c14e64b46944 ("soc: qcom: llcc: Support chipsets that can write to llcc")
Signed-off-by: Atul Dhudase <[email protected]>
Signed-off-by: Mukesh Ojha <[email protected]>
---
Changes in v2: https://lore.kernel.org/lkml/[email protected]/
- Rewritten the commit text based on feedback in v1
- Aligned the lines in the code.
drivers/soc/qcom/llcc-qcom.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index fb4085b7cb19..57d47dcf11b9 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -941,15 +941,15 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config,
u32 disable_cap_alloc, retain_pc;
disable_cap_alloc = config->dis_cap_alloc << config->slice_id;
- ret = regmap_write(drv_data->bcast_regmap,
- LLCC_TRP_SCID_DIS_CAP_ALLOC, disable_cap_alloc);
+ ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_SCID_DIS_CAP_ALLOC,
+ BIT(config->slice_id), disable_cap_alloc);
if (ret)
return ret;
if (drv_data->version < LLCC_VERSION_4_1_0_0) {
retain_pc = config->retain_on_pc << config->slice_id;
- ret = regmap_write(drv_data->bcast_regmap,
- LLCC_TRP_PCB_ACT, retain_pc);
+ ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_PCB_ACT,
+ BIT(config->slice_id), retain_pc);
if (ret)
return ret;
}
--
2.7.4
Hi,
On Wed, Dec 6, 2023 at 7:33 AM Mukesh Ojha <[email protected]> wrote:
>
> From: Atul Dhudase <[email protected]>
>
> Commit c14e64b46944 ("soc: qcom: llcc: Support chipsets that can
> write to llcc") add the support for chipset where capacity based
> allocation and retention through power collapse can be programmed
> based on content of SCT table mentioned in the llcc driver where
> the target like sdm845 where the entire programming related to it
> is controlled in firmware. However, the commit introduces a bug
> where capacity/retention register get overwritten each time it
> gets programmed for each slice and that results in misconfiguration
> of the register based on SCT table and that is not expected
> behaviour instead it should be read modify write to retain the
> configuration of other slices.
>
> This issue is totally caught from code review and programming test
> and not through any power/perf numbers so, it is not known what
> impact this could make if we don't have this change however,
> this feature are for these targets and they should have been
> programmed accordingly as per their configuration mentioned in
> SCT table like others bits information.
>
> This change brings one difference where it keeps capacity/retention
> bits of the slices that are not mentioned in SCT table in unknown
> state where as earlier it was initialized to zero.
>
> Fixes: c14e64b46944 ("soc: qcom: llcc: Support chipsets that can write to llcc")
> Signed-off-by: Atul Dhudase <[email protected]>
> Signed-off-by: Mukesh Ojha <[email protected]>
> ---
> Changes in v2: https://lore.kernel.org/lkml/[email protected]/
> - Rewritten the commit text based on feedback in v1
> - Aligned the lines in the code.
>
> drivers/soc/qcom/llcc-qcom.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
The commit message is much more clear now, though I wish we actually
had more real details about what was in the other bits in the register
that aren't being cleared now and also if this has any effect on
power/performance. In any case, this still seems worthwhile to me to
land.
Reviewed-by: Douglas Anderson <[email protected]>
On Wed, 06 Dec 2023 21:02:51 +0530, Mukesh Ojha wrote:
> Commit c14e64b46944 ("soc: qcom: llcc: Support chipsets that can
> write to llcc") add the support for chipset where capacity based
> allocation and retention through power collapse can be programmed
> based on content of SCT table mentioned in the llcc driver where
> the target like sdm845 where the entire programming related to it
> is controlled in firmware. However, the commit introduces a bug
> where capacity/retention register get overwritten each time it
> gets programmed for each slice and that results in misconfiguration
> of the register based on SCT table and that is not expected
> behaviour instead it should be read modify write to retain the
> configuration of other slices.
>
> [...]
Applied, thanks!
[1/1] soc: qcom: llcc: Fix dis_cap_alloc and retain_on_pc configuration
commit: eed6e57e9f3e2beac37563eb6a0129549daa330e
Best regards,
--
Bjorn Andersson <[email protected]>