Some spi flash memories have an interrupt signal which can be used for
signalling on-chip events such as busy status or ecc errors to the host.
Add binding for "interrupts" property so that boards wiring this signal
may describe the connection.
Signed-off-by: Josua Mayer <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
Changes in v7:
- split out of original patchset because it should go via mtd tree
- collected acked-by Rob Herring from v6
- Link to v6: https://lore.kernel.org/r/[email protected]
---
Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
index 58f0cea160ef..6e3afb42926e 100644
--- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
+++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
@@ -52,6 +52,9 @@ properties:
minItems: 1
maxItems: 2
+ interrupts:
+ maxItems: 1
+
m25p,fast-read:
type: boolean
description:
---
base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d
change-id: 20240219-mtd-flash-interrupt-binding-647f78d123cb
Best regards,
--
Josua Mayer <[email protected]>
On Mon, Feb 19 2024, Josua Mayer wrote:
> Some spi flash memories have an interrupt signal which can be used for
> signalling on-chip events such as busy status or ecc errors to the host.
>
> Add binding for "interrupts" property so that boards wiring this signal
> may describe the connection.
>
> Signed-off-by: Josua Mayer <[email protected]>
> Acked-by: Rob Herring <[email protected]>
Acked-by: Pratyush Yadav <[email protected]>
BTW, I don't see any support in SPI NOR for handling these interrupts.
Do you plan to add them in a later patchset? If not, what do you get by
describing them?
> ---
> Changes in v7:
> - split out of original patchset because it should go via mtd tree
> - collected acked-by Rob Herring from v6
> - Link to v6: https://lore.kernel.org/r/[email protected]
> ---
> Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> index 58f0cea160ef..6e3afb42926e 100644
> --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
> @@ -52,6 +52,9 @@ properties:
> minItems: 1
> maxItems: 2
>
> + interrupts:
> + maxItems: 1
> +
> m25p,fast-read:
> type: boolean
> description:
>
--
Regards,
Pratyush Yadav
Am 20.02.24 um 13:19 schrieb Pratyush Yadav:
> On Mon, Feb 19 2024, Josua Mayer wrote:
>
>> Some spi flash memories have an interrupt signal which can be used for
>> signalling on-chip events such as busy status or ecc errors to the host.
>>
>> Add binding for "interrupts" property so that boards wiring this signal
>> may describe the connection.
>>
>> Signed-off-by: Josua Mayer <[email protected]>
>> Acked-by: Rob Herring <[email protected]>
> Acked-by: Pratyush Yadav <[email protected]>
>
> BTW, I don't see any support in SPI NOR for handling these interrupts.
> Do you plan to add them in a later patchset?
No current plans, I have little knowledge how spi-nor works in the kernel.
> If not, what do you get by
> describing them?
Foremost I get to submit a correct device-tree (describes hardware)
to the kernel, without maintainers getting all over me for introducing
new dtbs_check errors.
And I really do prefer submitting a complete device-tree so that all
knowledge I have gained reading private schematics is readily
available the next time someone works on it.
>
>> ---
>> Changes in v7:
>> - split out of original patchset because it should go via mtd tree
>> - collected acked-by Rob Herring from v6
>> - Link to v6: https://lore.kernel.org/r/[email protected]
>> ---
>> Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
>> index 58f0cea160ef..6e3afb42926e 100644
>> --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
>> +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
>> @@ -52,6 +52,9 @@ properties:
>> minItems: 1
>> maxItems: 2
>>
>> + interrupts:
>> + maxItems: 1
>> +
>> m25p,fast-read:
>> type: boolean
>> description:
>>
On Tue, Feb 20 2024, Josua Mayer wrote:
> Am 20.02.24 um 13:19 schrieb Pratyush Yadav:
>> On Mon, Feb 19 2024, Josua Mayer wrote:
>>
>>> Some spi flash memories have an interrupt signal which can be used for
>>> signalling on-chip events such as busy status or ecc errors to the host.
>>>
>>> Add binding for "interrupts" property so that boards wiring this signal
>>> may describe the connection.
>>>
>>> Signed-off-by: Josua Mayer <[email protected]>
>>> Acked-by: Rob Herring <[email protected]>
>> Acked-by: Pratyush Yadav <[email protected]>
>>
>> BTW, I don't see any support in SPI NOR for handling these interrupts.
>> Do you plan to add them in a later patchset?
> No current plans, I have little knowledge how spi-nor works in the kernel.
>> If not, what do you get by
>> describing them?
> Foremost I get to submit a correct device-tree (describes hardware)
> to the kernel, without maintainers getting all over me for introducing
> new dtbs_check errors.
>
> And I really do prefer submitting a complete device-tree so that all
> knowledge I have gained reading private schematics is readily
> available the next time someone works on it.
Fair enough. I guessed as much but thanks for the confirmation!
[...]
--
Regards,
Pratyush Yadav
Hi,
On Mon Feb 19, 2024 at 3:41 PM CET, Josua Mayer wrote:
> Some spi flash memories have an interrupt signal which can be used for
> signalling on-chip events such as busy status or ecc errors to the host.
Do you have an example? Maybe one with a public datasheet?
-michael
Hi,
Am 21.02.24 um 09:27 schrieb Michael Walle:
> Hi,
>
> On Mon Feb 19, 2024 at 3:41 PM CET, Josua Mayer wrote:
>> Some spi flash memories have an interrupt signal which can be used for
>> signalling on-chip events such as busy status or ecc errors to the host.
> Do you have an example? Maybe one with a public datasheet?
My example is Infineon S28HS512T, however datasheet download requires
user account.
S26HS512T has interrupt line, too, and datasheet is downloadable without
registration:
https://www.infineon.com/cms/en/product/memories/nor-flash/semper-nor-flash-family/semper-nor-flash/#!documents
>
> -michael
[+ Takahiro]
Hi,
On Wed Feb 21, 2024 at 10:13 AM CET, Josua Mayer wrote:
> Hi,
>
> Am 21.02.24 um 09:27 schrieb Michael Walle:
> > Hi,
> >
> > On Mon Feb 19, 2024 at 3:41 PM CET, Josua Mayer wrote:
> >> Some spi flash memories have an interrupt signal which can be used for
> >> signalling on-chip events such as busy status or ecc errors to the host.
> > Do you have an example? Maybe one with a public datasheet?
>
> My example is Infineon S28HS512T, however datasheet download requires
> user account.
>
> S26HS512T has interrupt line, too, and datasheet is downloadable without
> registration:
> https://www.infineon.com/cms/en/product/memories/nor-flash/semper-nor-flash-family/semper-nor-flash/#!documents
Thanks, as far as I can see, both are hyperbus flashes. I'm asking
because I'm not aware of any SPI NOR flash with an interrupt line.
-michael
On Wed, Feb 21 2024, Michael Walle wrote:
> [+ Takahiro]
>
> Hi,
>
> On Wed Feb 21, 2024 at 10:13 AM CET, Josua Mayer wrote:
>> Hi,
>>
>> Am 21.02.24 um 09:27 schrieb Michael Walle:
>> > Hi,
>> >
>> > On Mon Feb 19, 2024 at 3:41 PM CET, Josua Mayer wrote:
>> >> Some spi flash memories have an interrupt signal which can be used for
>> >> signalling on-chip events such as busy status or ecc errors to the host.
>> > Do you have an example? Maybe one with a public datasheet?
>>
>> My example is Infineon S28HS512T, however datasheet download requires
>> user account.
>>
>> S26HS512T has interrupt line, too, and datasheet is downloadable without
>> registration:
>> https://www.infineon.com/cms/en/product/memories/nor-flash/semper-nor-flash-family/semper-nor-flash/#!documents
>
> Thanks, as far as I can see, both are hyperbus flashes. I'm asking
> because I'm not aware of any SPI NOR flash with an interrupt line.
I found this datasheet [0] for S28H flash family from Infineon on
Google. These are SPI NOR flashes. In pinout you can see there is an
INT# signal. The signal description says: "System Interrupt (INT#). When
LOW, the device is indicating that an internal event has occurred."
Further in section 4.1.1.5 "INT# Output" it says:
HL-T/HS-T supports INT# output pin to indicate to the host system
that an event has occurred within the flash device. The user can
configure the INT# output pin to transition to the active (LOW)
state when:
- 2-bit ECC error is detected
- 1-bit ECC error is detected
- Transitioning from the Busy to the Ready state
[0] https://www.infineon.com/dgdl/Infineon-S28HS256T_S28HS512T_S28HS01GT_S28HL256T_S28HL512T_S28HL01GT_256-Mb_(32-MB)_512-Mb_(64-MB)_1-Gb_(128-MB)_HS-T_(1.8-V)_HL-T_(3.0-V)_Semper_Flash_with_Octal_Interface-DataSheet-v03_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ee6bca96f97&da=t
--
Regards,
Pratyush Yadav
On Wed Feb 21, 2024 at 11:48 AM CET, Pratyush Yadav wrote:
> On Wed, Feb 21 2024, Michael Walle wrote:
>
> > [+ Takahiro]
> >
> > Hi,
> >
> > On Wed Feb 21, 2024 at 10:13 AM CET, Josua Mayer wrote:
> >> Hi,
> >>
> >> Am 21.02.24 um 09:27 schrieb Michael Walle:
> >> > Hi,
> >> >
> >> > On Mon Feb 19, 2024 at 3:41 PM CET, Josua Mayer wrote:
> >> >> Some spi flash memories have an interrupt signal which can be used for
> >> >> signalling on-chip events such as busy status or ecc errors to the host.
> >> > Do you have an example? Maybe one with a public datasheet?
> >>
> >> My example is Infineon S28HS512T, however datasheet download requires
> >> user account.
> >>
> >> S26HS512T has interrupt line, too, and datasheet is downloadable without
> >> registration:
> >> https://www.infineon.com/cms/en/product/memories/nor-flash/semper-nor-flash-family/semper-nor-flash/#!documents
> >
> > Thanks, as far as I can see, both are hyperbus flashes. I'm asking
> > because I'm not aware of any SPI NOR flash with an interrupt line.
>
> I found this datasheet [0] for S28H flash family from Infineon on
> Google. These are SPI NOR flashes. In pinout you can see there is an
> INT# signal. The signal description says: "System Interrupt (INT#). When
> LOW, the device is indicating that an internal event has occurred."
> Further in section 4.1.1.5 "INT# Output" it says:
>
> HL-T/HS-T supports INT# output pin to indicate to the host system
> that an event has occurred within the flash device. The user can
> configure the INT# output pin to transition to the active (LOW)
> state when:
>
> - 2-bit ECC error is detected
> - 1-bit ECC error is detected
> - Transitioning from the Busy to the Ready state
>
> [0] https://www.infineon.com/dgdl/Infineon-S28HS256T_S28HS512T_S28HS01GT_S28HL256T_S28HL512T_S28HL01GT_256-Mb_(32-MB)_512-Mb_(64-MB)_1-Gb_(128-MB)_HS-T_(1.8-V)_HL-T_(3.0-V)_Semper_Flash_with_Octal_Interface-DataSheet-v03_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ee6bca96f97&da=t
Okay then,
Acked-by: Michael Walle <[email protected]>
-michael
On Mon, 19 Feb 2024 15:41:19 +0100, Josua Mayer wrote:
> Some spi flash memories have an interrupt signal which can be used for
> signalling on-chip events such as busy status or ecc errors to the host.
>
> Add binding for "interrupts" property so that boards wiring this signal
> may describe the connection.
>
>
> [...]
Applied to git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git,
spi-nor/next branch. Thanks!
[1/1] dt-bindings: mtd: spi-nor: add optional interrupts property
(no commit info)
Cheers,
--
Tudor Ambarus <[email protected]>