LinuxLists.cc - [PATCH 00/17] HSI2, UFS & UFS phy support for Tensor GS101

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Subject: [PATCH 01/17] dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit

Add dt schema documentation and clock IDs for the High Speed Interface
2 (HSI2) clock management unit. This CMU feeds high speed interfaces
such as PCIe and UFS.

Signed-off-by: Peter Griffin <[email protected]>
---
.../bindings/clock/google,gs101-clock.yaml | 30 +++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
index 1d2bcea41c85..a202fd5d1ead 100644
--- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
@@ -32,14 +32,15 @@ properties:
- google,gs101-cmu-misc
- google,gs101-cmu-peric0
- google,gs101-cmu-peric1
+ - google,gs101-cmu-hsi2

clocks:
minItems: 1
- maxItems: 3
+ maxItems: 5

clock-names:
minItems: 1
- maxItems: 3
+ maxItems: 5

"#clock-cells":
const: 1
@@ -112,6 +113,31 @@ allOf:
- const: bus
- const: ip

+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - google,gs101-cmu-hsi2
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24.576 MHz)
+ - description: High Speed Interface bus clock (from CMU_TOP)
+ - description: High Speed Interface pcie clock (from CMU_TOP)
+ - description: High Speed Interface ufs clock (from CMU_TOP)
+ - description: High Speed Interface mmc clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: bus
+ - const: pcie
+ - const: ufs_embd
+ - const: mmc_card
+
additionalProperties: false

examples:
--
2.44.0.478.gd926399ef9-goog

2024-04-04 12:29:45

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Subject: [PATCH 03/17] dt-bindings: ufs: exynos-ufs: Add gs101 compatible

Add dedicated google,gs101-ufs compatible for Google Tensor gs101
SoC.

Signed-off-by: Peter Griffin <[email protected]>
---
.../bindings/ufs/samsung,exynos-ufs.yaml | 51 +++++++++++++++----
1 file changed, 42 insertions(+), 9 deletions(-)

diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
index b2b509b3944d..898da6c0e94f 100644
--- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
@@ -12,12 +12,10 @@ maintainers:
description: |
Each Samsung UFS host controller instance should have its own node.

-allOf:
- - $ref: ufs-common.yaml
-
properties:
compatible:
enum:
+ - google,gs101-ufs
- samsung,exynos7-ufs
- samsung,exynosautov9-ufs
- samsung,exynosautov9-ufs-vh
@@ -38,14 +36,12 @@ properties:
- const: ufsp

clocks:
- items:
- - description: ufs link core clock
- - description: unipro main clock
+ minItems: 2
+ maxItems: 5

clock-names:
- items:
- - const: core_clk
- - const: sclk_unipro_main
+ minItems: 2
+ maxItems: 5

phys:
maxItems: 1
@@ -72,6 +68,43 @@ required:
- clocks
- clock-names

+allOf:
+ - $ref: ufs-common.yaml
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: google,gs101-ufs
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: ufs link core clock
+ - description: unipro main clock
+ - description: fmp clock
+ - description: ufs aclk clock
+ - description: ufs pclk clock
+
+ clock-names:
+ items:
+ - const: core_clk
+ - const: sclk_unipro_main
+ - const: fmp
+ - const: ufs_aclk
+ - const: ufs_pclk
+ else:
+ properties:
+ clocks:
+ items:
+ - description: ufs link core clock
+ - description: unipro main clock
+
+ clock-names:
+ items:
+ - const: core_clk
+ - const: sclk_unipro_main
+
unevaluatedProperties: false

examples:
--
2.44.0.478.gd926399ef9-goog

2024-04-04 12:30:26

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Subject: [PATCH 05/17] arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller

Enable the cmu_hsi2 clock management unit. It feeds some of
the high speed interfaces such as PCIe and UFS.

Signed-off-by: Peter Griffin <[email protected]>
---
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index eddb6b326fde..38ac4fb1397e 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -1253,6 +1253,18 @@ pinctrl_hsi1: pinctrl@11840000 {
interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
};

+ cmu_hsi2: clock-controller@14400000 {
+ compatible = "google,gs101-cmu-hsi2";
+ reg = <0x14400000 0x4000>;
+ #clock-cells = <1>;
+ clocks = <&ext_24_5m>,
+ <&cmu_top CLK_DOUT_CMU_HSI2_BUS>,
+ <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>,
+ <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>,
+ <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>;
+ clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card";
+ };
+
pinctrl_hsi2: pinctrl@14440000 {
compatible = "google,gs101-pinctrl";
reg = <0x14440000 0x00001000>;
--
2.44.0.478.gd926399ef9-goog

2024-04-04 12:31:08

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Subject: [PATCH 07/17] arm64: dts: exynos: gs101: Add ufs, ufs-phy and ufs regulator dt nodes

Enable the ufs controller, ufs phy and ufs regulator in device tree.

Signed-off-by: Peter Griffin <[email protected]>
---
.../boot/dts/exynos/google/gs101-oriole.dts | 17 +++++++++
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 35 +++++++++++++++++++
2 files changed, 52 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
index 6be15e990b65..986eb5c9898a 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
+++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
@@ -53,6 +53,14 @@ button-power {
wakeup-source;
};
};
+
+ ufs_0_fixed_vcc_reg: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "ufs-vcc";
+ gpio = <&gpp0 1 0>;
+ regulator-boot-on;
+ enable-active-high;
+ };
};

&ext_24_5m {
@@ -106,6 +114,15 @@ &serial_0 {
status = "okay";
};

+&ufs_0 {
+ status = "okay";
+ vcc-supply = <&ufs_0_fixed_vcc_reg>;
+};
+
+&ufs_0_phy {
+ status = "okay";
+};
+
&usi_uart {
samsung,clkreq-on; /* needed for UART mode */
status = "okay";
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index 608369cec47b..9c94829bf14c 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -1277,6 +1277,41 @@ pinctrl_hsi2: pinctrl@14440000 {
interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
};

+ ufs_0_phy: phy@17e04000 {
+ compatible = "google,gs101-ufs-phy";
+ reg = <0x14704000 0x3000>;
+ reg-names = "phy-pma";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ clocks = <&ext_24_5m>;
+ clock-names = "ref_clk";
+ status = "disabled";
+ };
+
+ ufs_0: ufs@14700000 {
+ compatible = "google,gs101-ufs";
+
+ reg = <0x14700000 0x200>,
+ <0x14701100 0x200>,
+ <0x14780000 0xa000>,
+ <0x14600000 0x100>;
+ reg-names = "hci", "vs_hci", "unipro", "ufsp";
+ interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>,
+ <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>,
+ <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>,
+ <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>,
+ <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>;
+ clock-names = "core_clk", "sclk_unipro_main", "fmp", "ufs_aclk", "ufs_pclk";
+ freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
+ phys = <&ufs_0_phy>;
+ phy-names = "ufs-phy";
+ samsung,sysreg = <&sysreg_hsi2 0x710>;
+ status = "disabled";
+ };
+
cmu_apm: clock-controller@17400000 {
compatible = "google,gs101-cmu-apm";
reg = <0x17400000 0x8000>;
--
2.44.0.478.gd926399ef9-goog

2024-04-04 12:33:13

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Subject: [PATCH 11/17] phy: samsung-ufs: ufs: Add support for gs101 UFS phy tuning

Add the m-phy tuning values for gs101 UFS phy and SoC callbacks
gs101_phy_wait_for_calibration() and gs101_phy_wait_for_cdr_lock().

Signed-off-by: Peter Griffin <[email protected]>
---
drivers/phy/samsung/Makefile | 1 +
drivers/phy/samsung/phy-gs101-ufs.c | 182 ++++++++++++++++++++++++++
drivers/phy/samsung/phy-samsung-ufs.c | 3 +
drivers/phy/samsung/phy-samsung-ufs.h | 1 +
4 files changed, 187 insertions(+)
create mode 100644 drivers/phy/samsung/phy-gs101-ufs.c

diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
index afb34a153e34..fea1f96d0e43 100644
--- a/drivers/phy/samsung/Makefile
+++ b/drivers/phy/samsung/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o
obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-exynos-ufs.o
+phy-exynos-ufs-y += phy-gs101-ufs.o
phy-exynos-ufs-y += phy-samsung-ufs.o
phy-exynos-ufs-y += phy-exynos7-ufs.o
phy-exynos-ufs-y += phy-exynosautov9-ufs.o
diff --git a/drivers/phy/samsung/phy-gs101-ufs.c b/drivers/phy/samsung/phy-gs101-ufs.c
new file mode 100644
index 000000000000..17b798da5b57
--- /dev/null
+++ b/drivers/phy/samsung/phy-gs101-ufs.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * UFS PHY driver data for Google Tensor gs101 SoC
+ *
+ * Copyright (C) 2024 Linaro Ltd
+ * Author: Peter Griffin <[email protected]>
+ */
+
+#include "phy-samsung-ufs.h"
+
+#define TENSOR_GS101_PHY_CTRL 0x3ec8
+#define TENSOR_GS101_PHY_CTRL_MASK 0x1
+#define TENSOR_GS101_PHY_CTRL_EN BIT(0)
+#define PHY_GS101_LANE_OFFSET 0x200
+#define TRSV_REG338 0x338
+#define LN0_MON_RX_CAL_DONE BIT(3)
+#define TRSV_REG339 0x339
+#define LN0_MON_RX_CDR_FLD_CK_MODE_DONE BIT(3)
+#define TRSV_REG222 0x222
+#define LN0_OVRD_RX_CDR_EN BIT(4)
+#define LN0_RX_CDR_EN BIT(3)
+
+#define PHY_PMA_TRSV_ADDR(reg, lane) (PHY_APB_ADDR((reg) + \
+ ((lane) * PHY_GS101_LANE_OFFSET)))
+
+#define PHY_TRSV_REG_CFG_GS101(o, v, d) \
+ PHY_TRSV_REG_CFG_OFFSET(o, v, d, PHY_GS101_LANE_OFFSET)
+
+/* Calibration for phy initialization */
+static const struct samsung_ufs_phy_cfg tensor_gs101_pre_init_cfg[] = {
+ PHY_COMN_REG_CFG(0x43, 0x10, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x3C, 0x14, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x46, 0x48, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x200, 0x00, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x201, 0x06, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x202, 0x06, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x203, 0x0a, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x204, 0x00, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x205, 0x11, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x207, 0x0c, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2E1, 0xc0, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x22D, 0xb8, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x234, 0x60, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x238, 0x13, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x239, 0x48, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x23A, 0x01, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x23B, 0x25, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x23C, 0x2a, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x23D, 0x01, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x23E, 0x13, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x23F, 0x13, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x240, 0x4a, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x243, 0x40, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x244, 0x02, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x25D, 0x00, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x25E, 0x3f, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x25F, 0xff, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x273, 0x33, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x274, 0x50, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x284, 0x02, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x285, 0x02, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2A2, 0x04, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x25D, 0x01, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2FA, 0x01, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x286, 0x03, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x287, 0x03, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x288, 0x03, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x289, 0x03, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2B3, 0x04, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2B6, 0x0b, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2B7, 0x0b, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2B8, 0x0b, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2B9, 0x0b, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2BA, 0x0b, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2BB, 0x06, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2BC, 0x06, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2BD, 0x06, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x29E, 0x06, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2E4, 0x1a, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2ED, 0x25, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x269, 0x1a, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x2F4, 0x2f, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x34B, 0x01, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x34C, 0x23, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x34D, 0x23, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x34E, 0x45, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x34F, 0x00, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x350, 0x31, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x351, 0x00, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x352, 0x02, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x353, 0x00, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x354, 0x01, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x43, 0x18, PWR_MODE_ANY),
+ PHY_COMN_REG_CFG(0x43, 0x00, PWR_MODE_ANY),
+ END_UFS_PHY_CFG,
+};
+
+static const struct samsung_ufs_phy_cfg tensor_gs101_pre_pwr_hs_config[] = {
+ PHY_TRSV_REG_CFG_GS101(0x369, 0x11, PWR_MODE_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x246, 0x03, PWR_MODE_ANY),
+};
+
+/* Calibration for HS mode series A/B */
+static const struct samsung_ufs_phy_cfg tensor_gs101_post_pwr_hs_config[] = {
+ PHY_COMN_REG_CFG(0x8, 0x60, PWR_MODE_PWM_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x222, 0x08, PWR_MODE_PWM_ANY),
+ PHY_TRSV_REG_CFG_GS101(0x246, 0x01, PWR_MODE_ANY),
+ END_UFS_PHY_CFG,
+};
+
+static const struct samsung_ufs_phy_cfg *tensor_gs101_ufs_phy_cfgs[CFG_TAG_MAX] = {
+ [CFG_PRE_INIT] = tensor_gs101_pre_init_cfg,
+ [CFG_PRE_PWR_HS] = tensor_gs101_pre_pwr_hs_config,
+ [CFG_POST_PWR_HS] = tensor_gs101_post_pwr_hs_config,
+};
+
+static const char * const tensor_gs101_ufs_phy_clks[] = {
+ "ref_clk",
+};
+
+static int gs101_phy_wait_for_calibration(struct phy *phy, u8 lane)
+{
+ struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
+ const unsigned int timeout_us = 40000;
+ const unsigned int sleep_us = 40;
+ u32 val;
+ u32 off;
+ int err;
+
+ off = PHY_PMA_TRSV_ADDR(TRSV_REG338, lane);
+
+ err = readl_poll_timeout(ufs_phy->reg_pma + off,
+ val, (val & LN0_MON_RX_CAL_DONE),
+ sleep_us, timeout_us);
+
+ if (err) {
+ dev_err(ufs_phy->dev,
+ "failed to get phy cal done %d\n", err);
+ }
+
+ return err;
+}
+
+#define DELAY_IN_US 40
+#define RETRY_CNT 100
+static int gs101_phy_wait_for_cdr_lock(struct phy *phy, u8 lane)
+{
+ struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
+ u32 val;
+ int i;
+
+ for (i = 0; i < RETRY_CNT; i++) {
+ udelay(DELAY_IN_US);
+ val = readl(ufs_phy->reg_pma +
+ PHY_PMA_TRSV_ADDR(TRSV_REG339, lane));
+
+ if (val & LN0_MON_RX_CDR_FLD_CK_MODE_DONE)
+ return 0;
+
+ udelay(DELAY_IN_US);
+ /* Override and enable clock data recovery */
+ writel(LN0_OVRD_RX_CDR_EN, ufs_phy->reg_pma +
+ PHY_PMA_TRSV_ADDR(TRSV_REG222, lane));
+ writel(LN0_OVRD_RX_CDR_EN | LN0_RX_CDR_EN,
+ ufs_phy->reg_pma + PHY_PMA_TRSV_ADDR(TRSV_REG222, lane));
+ }
+ dev_err(ufs_phy->dev, "failed to get cdr lock\n");
+ return -ETIMEDOUT;
+}
+
+const struct samsung_ufs_phy_drvdata tensor_gs101_ufs_phy = {
+ .cfgs = tensor_gs101_ufs_phy_cfgs,
+ .isol = {
+ .offset = TENSOR_GS101_PHY_CTRL,
+ .mask = TENSOR_GS101_PHY_CTRL_MASK,
+ .en = TENSOR_GS101_PHY_CTRL_EN,
+ },
+ .clk_list = tensor_gs101_ufs_phy_clks,
+ .num_clks = ARRAY_SIZE(tensor_gs101_ufs_phy_clks),
+ .wait_for_cal = gs101_phy_wait_for_calibration,
+ .wait_for_cdr = gs101_phy_wait_for_cdr_lock,
+};
diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
index f57a2f2a415d..813bce47121d 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.c
+++ b/drivers/phy/samsung/phy-samsung-ufs.c
@@ -310,6 +310,9 @@ static int samsung_ufs_phy_probe(struct platform_device *pdev)

static const struct of_device_id samsung_ufs_phy_match[] = {
{
+ .compatible = "google,gs101-ufs-phy",
+ .data = &tensor_gs101_ufs_phy,
+ }, {
.compatible = "samsung,exynos7-ufs-phy",
.data = &exynos7_ufs_phy,
}, {
diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
index 7de6b574b94d..9b7deef6e10f 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.h
+++ b/drivers/phy/samsung/phy-samsung-ufs.h
@@ -147,5 +147,6 @@ int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy, u8 lane);
extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy;
extern const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy;
extern const struct samsung_ufs_phy_drvdata fsd_ufs_phy;
+extern const struct samsung_ufs_phy_drvdata tensor_gs101_ufs_phy;

#endif /* _PHY_SAMSUNG_UFS_ */
--
2.44.0.478.gd926399ef9-goog

2024-04-04 12:34:02

[permalink] [raw]

Subject: [PATCH 15/17] scsi: ufs: host: ufs-exynos: add some pa_dbg_ register offsets into drvdata

This allows these registers to be at different offsets or not
exist at all on some SoCs variants.

Signed-off-by: Peter Griffin <[email protected]>
---
drivers/ufs/host/ufs-exynos.c | 38 ++++++++++++++++++++++++-----------
drivers/ufs/host/ufs-exynos.h | 6 +++++-
2 files changed, 31 insertions(+), 13 deletions(-)

diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index 1bfda9c75703..065258203836 100644
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -308,8 +308,9 @@ static int exynosauto_ufs_post_pwr_change(struct exynos_ufs *ufs,

static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
{
+ struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
+ u32 val = attr->pa_dbg_opt_suite1_val;
struct ufs_hba *hba = ufs->hba;
- u32 val = ufs->drv_data->uic_attr->pa_dbg_option_suite;
int i;

exynos_ufs_enable_ov_tm(hba);
@@ -326,12 +327,13 @@ static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0);
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1);
udelay(1);
- ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val | (1 << 12));
+ ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off),
+ val | (1 << 12));
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1);
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1);
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1);
udelay(1600);
- ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off), val);

return 0;
}
@@ -923,14 +925,19 @@ static int exynos_ufs_phy_init(struct exynos_ufs *ufs)

static void exynos_ufs_config_unipro(struct exynos_ufs *ufs)
{
+ struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
struct ufs_hba *hba = ufs->hba;

- ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD),
- DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
+ if (attr->pa_dbg_clk_period_off)
+ ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off),
+ DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
+
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTRAILINGCLOCKS),
ufs->drv_data->uic_attr->tx_trailingclks);
- ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE),
- ufs->drv_data->uic_attr->pa_dbg_option_suite);
+
+ if (attr->pa_dbg_opt_suite1_off)
+ ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off),
+ attr->pa_dbg_opt_suite1_val);
}

static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 index)
@@ -1486,10 +1493,11 @@ static int exynosauto_ufs_vh_init(struct ufs_hba *hba)

static int fsd_ufs_pre_link(struct exynos_ufs *ufs)
{
- int i;
+ struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
struct ufs_hba *hba = ufs->hba;
+ int i;

- ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD),
+ ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_clk_period_off),
DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12);
ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
@@ -1513,7 +1521,9 @@ static int fsd_ufs_pre_link(struct exynos_ufs *ufs)

ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_AUTOMODE_THLD), 0x4E20);
- ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), 0x2e820183);
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off),
+ 0x2e820183);
ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0);

exynos_ufs_establish_connt(ufs);
@@ -1655,7 +1665,9 @@ static struct exynos_ufs_uic_attr exynos7_uic_attr = {
.rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf),
.rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf),
.rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf),
- .pa_dbg_option_suite = 0x30103,
+ .pa_dbg_clk_period_off = PA_DBG_CLK_PERIOD,
+ .pa_dbg_opt_suite1_val = 0x30103,
+ .pa_dbg_opt_suite1_off = PA_DBG_OPTION_SUITE,
};

static const struct exynos_ufs_drv_data exynosauto_ufs_drvs = {
@@ -1729,7 +1741,9 @@ static struct exynos_ufs_uic_attr fsd_uic_attr = {
.rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf),
.rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf),
.rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf),
- .pa_dbg_option_suite = 0x2E820183,
+ .pa_dbg_clk_period_off = PA_DBG_CLK_PERIOD,
+ .pa_dbg_opt_suite1_val = 0x2E820183,
+ .pa_dbg_opt_suite1_off = PA_DBG_OPTION_SUITE,
};

static const struct exynos_ufs_drv_data fsd_ufs_drvs = {
diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h
index 7acc13914100..f30423223474 100644
--- a/drivers/ufs/host/ufs-exynos.h
+++ b/drivers/ufs/host/ufs-exynos.h
@@ -145,7 +145,11 @@ struct exynos_ufs_uic_attr {
/* Common Attributes */
unsigned int cmn_pwm_clk_ctrl;
/* Internal Attributes */
- unsigned int pa_dbg_option_suite;
+ unsigned int pa_dbg_clk_period_off;
+ unsigned int pa_dbg_opt_suite1_val;
+ unsigned int pa_dbg_opt_suite1_off;
+ unsigned int pa_dbg_opt_suite2_val;
+ unsigned int pa_dbg_opt_suite2_off;
/* Changeable Attributes */
unsigned int rx_adv_fine_gran_sup_en;
unsigned int rx_adv_fine_gran_step;
--
2.44.0.478.gd926399ef9-goog

2024-04-04 12:36:54

[permalink] [raw]

Subject: [PATCH 04/17] dt-bindings: phy: samsung,ufs-phy: Add dedicated gs101-ufs-phy compatible

Update dt schema to include the gs101 ufs phy compatible.

Signed-off-by: Peter Griffin <[email protected]>
---
Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
index 782f975b43ae..f402e31bf58d 100644
--- a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml
@@ -15,6 +15,7 @@ properties:

compatible:
enum:
+ - google,gs101-ufs-phy
- samsung,exynos7-ufs-phy
- samsung,exynosautov9-ufs-phy
- tesla,fsd-ufs-phy
--
2.44.0.478.gd926399ef9-goog

2024-04-04 12:37:50

[permalink] [raw]

Subject: [PATCH 08/17] clk: samsung: gs101: add support for cmu_hsi2

CMU_HSI2 is the clock management unit used for the hsi2 block.
HSI stands for High Speed Interface and as such it generates
clocks for PCIe, UFS and MMC card.

This patch adds support for the muxes, dividers, and gates in
cmu_hsi2.

CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK is marked as CLK_IS_CRITICAL
as disabling it leads to an immediate system hang.

CLK_GOUT_HSI2_SYSREG_HSI2_PCLK is also marked CLK_IS_CRITICAL.
A hang is not observed with fine grained clock control, but
UFS IP does not function with syscon controlling this clock
just around hsi2_sysreg register accesses.

CLK_GOUT_HSI2_GPIO_HSI2_PCLK is marked CLK_IGNORE_UNUSED until
the exynos pinctrl clock patches land then it can be removed.

Some clocks in this unit have very long names. To help with this
the clock name mangling strategy was updated to include removing
the following sub-strings.
- G4X2_DWC_PCIE_CTL_
- G4X1_DWC_PCIE_CTL_
- PCIE_SUB_CTRL_
- INST_0_
- LN05LPE_
- TM_WRAPPER_
- SF_

Signed-off-by: Peter Griffin <[email protected]>

---
Updated regex for clock name mangling
sed \
-e 's|^PLL_LOCKTIME_PLL_$[^_]\+$|fout_\L\1_pll|' \
\
-e 's|^PLL_CON0_MUX_CLKCMU_$[^_]\+$_$.*$|mout_\L\1_\2|' \
-e 's|^PLL_CON0_PLL_$.*$|mout_pll_\L\1|' \
-e 's|^CLK_CON_MUX_MUX_CLK_$.*$|mout_\L\1|' \
-e '/^PLL_CON[1-4]_[^_]\+_/d' \
-e '/^[^_]\+_CMU_[^_]\+_CONTROLLER_OPTION/d' \
-e '/^CLKOUT_CON_BLK_[^_]\+_CMU_[^_]\+_CLKOUT0/d' \
\
-e 's|_IPCLKPORT||' \
-e 's|_RSTNSYNC||' \
-e 's|_G4X2_DWC_PCIE_CTL||' \
-e 's|_G4X1_DWC_PCIE_CTL||' \
-e 's|_PCIE_SUB_CTRL||' \
-e 's|_INST_0||g' \
-e 's|_LN05LPE||' \
-e 's|_TM_WRAPPER||' \
-e 's|_SF||' \
\
-e 's|^CLK_CON_DIV_DIV_CLK_$[^_]\+$_$.*$|dout_\L\1_\2|' \
\
-e 's|^CLK_CON_BUF_CLKBUF_$[^_]\+$_$.*$|gout_\L\1_\2|' \
-e 's|^CLK_CON_GAT_CLK_BLK_$[^_]\+$_UID_$.*$|gout_\L\1_\2|' \
-e 's|^gout_[^_]\+_[^_]\+_cmu_$[^_]\+$_pclk$|gout_\1_\1_pclk|' \
-e 's|^CLK_CON_GAT_GOUT_BLK_$[^_]\+$_UID_$.*$|gout_\L\1_\2|' \
-e 's|^CLK_CON_GAT_CLK_$[^_]\+$_$.*$|gout_\L\1_clk_\L\1_\2|' \
\
-e '/^$DMYQCH\|PCH\|QCH\|QUEUE$_/d'
---
drivers/clk/samsung/clk-gs101.c | 558 +++++++++++++++++++++++
include/dt-bindings/clock/google,gs101.h | 63 +++
2 files changed, 621 insertions(+)

diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
index d065e343a85d..b9f84c7d5c22 100644
--- a/drivers/clk/samsung/clk-gs101.c
+++ b/drivers/clk/samsung/clk-gs101.c
@@ -22,6 +22,7 @@
#define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)
#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1)
+#define CLKS_NR_HSI2 (CLK_GOUT_HSI2_XIU_P_HSI2_ACLK + 1)

/* ---- CMU_TOP ------------------------------------------------------------- */

@@ -3409,6 +3410,560 @@ static const struct samsung_cmu_info peric1_cmu_info __initconst = {
.clk_name = "bus",
};

+/* ---- CMU_HSI2 ---------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_HSI2 (0x14400000) */
+#define PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER 0x0600
+#define PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER 0x0604
+#define PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0610
+#define PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0614
+#define PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER 0x0620
+#define PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER 0x0624
+#define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0630
+#define PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0634
+#define HSI2_CMU_HSI2_CONTROLLER_OPTION 0x0800
+#define CLKOUT_CON_BLK_HSI2_CMU_HSI2_CLKOUT0 0x0810
+#define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2000
+#define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2004
+#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK 0x2008
+#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK 0x200c
+#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK 0x2010
+#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK 0x2014
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK 0x201c
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK 0x2020
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK 0x2024
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK 0x2028
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK 0x202c
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK 0x2030
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2034
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x2038
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x203c
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2040
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2044
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2048
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x204c
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2050
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2054
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2058
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK 0x205c
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK 0x2060
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK 0x2064
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK 0x2068
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK 0x206c
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK 0x2070
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK 0x2074
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK 0x2078
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK 0x207c
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK 0x2080
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK 0x2084
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK 0x2088
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK 0x208c
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK 0x2090
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK 0x2094
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK 0x2098
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK 0x209c
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK 0x20a0
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK 0x20a4
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2 0x20a8
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK 0x20ac
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK 0x20b0
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK 0x20b4
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK 0x20b8
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK 0x20bc
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK 0x20c0
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK 0x20c4
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK 0x20c8
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK 0x20cc
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK 0x20d0
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO 0x20d4
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK 0x20d8
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK 0x20dc
+#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK 0x20e0
+#define DMYQCH_CON_PCIE_GEN4_1_QCH_SCLK_1 0x3000
+#define PCH_CON_LHM_AXI_P_HSI2_PCH 0x3008
+#define PCH_CON_LHS_ACEL_D_HSI2_PCH 0x300c
+#define QCH_CON_D_TZPC_HSI2_QCH 0x3010
+#define QCH_CON_GPC_HSI2_QCH 0x3014
+#define QCH_CON_GPIO_HSI2_QCH 0x3018
+#define QCH_CON_HSI2_CMU_HSI2_QCH 0x301c
+#define QCH_CON_LHM_AXI_P_HSI2_QCH 0x3020
+#define QCH_CON_LHS_ACEL_D_HSI2_QCH 0x3024
+#define QCH_CON_MMC_CARD_QCH 0x3028
+#define QCH_CON_PCIE_GEN4_1_QCH_APB_1 0x302c
+#define QCH_CON_PCIE_GEN4_1_QCH_APB_2 0x3030
+#define QCH_CON_PCIE_GEN4_1_QCH_AXI_1 0x3034
+#define QCH_CON_PCIE_GEN4_1_QCH_AXI_2 0x3038
+#define QCH_CON_PCIE_GEN4_1_QCH_DBG_1 0x303c
+#define QCH_CON_PCIE_GEN4_1_QCH_DBG_2 0x3040
+#define QCH_CON_PCIE_GEN4_1_QCH_PCS_APB 0x3044
+#define QCH_CON_PCIE_GEN4_1_QCH_PMA_APB 0x3048
+#define QCH_CON_PCIE_GEN4_1_QCH_UDBG 0x304c
+#define QCH_CON_PCIE_IA_GEN4A_1_QCH 0x3050
+#define QCH_CON_PCIE_IA_GEN4B_1_QCH 0x3054
+#define QCH_CON_PPMU_HSI2_QCH 0x3058
+#define QCH_CON_QE_MMC_CARD_HSI2_QCH 0x305c
+#define QCH_CON_QE_PCIE_GEN4A_HSI2_QCH 0x3060
+#define QCH_CON_QE_PCIE_GEN4B_HSI2_QCH 0x3064
+#define QCH_CON_QE_UFS_EMBD_HSI2_QCH 0x3068
+#define QCH_CON_SSMT_HSI2_QCH 0x306c
+#define QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH 0x3070
+#define QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH 0x3074
+#define QCH_CON_SYSMMU_HSI2_QCH 0x3078
+#define QCH_CON_SYSREG_HSI2_QCH 0x307c
+#define QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH 0x3080
+#define QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH 0x3084
+#define QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH 0x3088
+#define QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH 0x308c
+#define QCH_CON_UFS_EMBD_QCH 0x3090
+#define QCH_CON_UFS_EMBD_QCH_FMP 0x3094
+#define QUEUE_CTRL_REG_BLK_HSI2_CMU_HSI2 0x3c00
+
+static const unsigned long cmu_hsi2_clk_regs[] __initconst = {
+ PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER,
+ PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER,
+ PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER,
+ PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER,
+ PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER,
+ PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER,
+ PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
+ PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
+ HSI2_CMU_HSI2_CONTROLLER_OPTION,
+ CLKOUT_CON_BLK_HSI2_CMU_HSI2_CLKOUT0,
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK,
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK,
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK,
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK,
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK,
+ DMYQCH_CON_PCIE_GEN4_1_QCH_SCLK_1,
+ PCH_CON_LHM_AXI_P_HSI2_PCH,
+ PCH_CON_LHS_ACEL_D_HSI2_PCH,
+ QCH_CON_D_TZPC_HSI2_QCH,
+ QCH_CON_GPC_HSI2_QCH,
+ QCH_CON_GPIO_HSI2_QCH,
+ QCH_CON_HSI2_CMU_HSI2_QCH,
+ QCH_CON_LHM_AXI_P_HSI2_QCH,
+ QCH_CON_LHS_ACEL_D_HSI2_QCH,
+ QCH_CON_MMC_CARD_QCH,
+ QCH_CON_PCIE_GEN4_1_QCH_APB_1,
+ QCH_CON_PCIE_GEN4_1_QCH_APB_2,
+ QCH_CON_PCIE_GEN4_1_QCH_AXI_1,
+ QCH_CON_PCIE_GEN4_1_QCH_AXI_2,
+ QCH_CON_PCIE_GEN4_1_QCH_DBG_1,
+ QCH_CON_PCIE_GEN4_1_QCH_DBG_2,
+ QCH_CON_PCIE_GEN4_1_QCH_PCS_APB,
+ QCH_CON_PCIE_GEN4_1_QCH_PMA_APB,
+ QCH_CON_PCIE_GEN4_1_QCH_UDBG,
+ QCH_CON_PCIE_IA_GEN4A_1_QCH,
+ QCH_CON_PCIE_IA_GEN4B_1_QCH,
+ QCH_CON_PPMU_HSI2_QCH,
+ QCH_CON_QE_MMC_CARD_HSI2_QCH,
+ QCH_CON_QE_PCIE_GEN4A_HSI2_QCH,
+ QCH_CON_QE_PCIE_GEN4B_HSI2_QCH,
+ QCH_CON_QE_UFS_EMBD_HSI2_QCH,
+ QCH_CON_SSMT_HSI2_QCH,
+ QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH,
+ QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH,
+ QCH_CON_SYSMMU_HSI2_QCH,
+ QCH_CON_SYSREG_HSI2_QCH,
+ QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH,
+ QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH,
+ QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH,
+ QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH,
+ QCH_CON_UFS_EMBD_QCH,
+ QCH_CON_UFS_EMBD_QCH_FMP,
+ QUEUE_CTRL_REG_BLK_HSI2_CMU_HSI2,
+};
+
+PNAME(mout_hsi2_ufs_embd_p) = { "oscclk", "dout_cmu_shared0_div4",
+ "dout_cmu_shared2_div2", "fout_spare_pll" };
+
+PNAME(mout_hsi2_pcie_p) = { "oscclk", "dout_cmu_shared2_div2" };
+
+PNAME(mout_hsi2_bus_p) = { "dout_cmu_shared0_div4",
+ "dout_cmu_shared1_div4",
+ "dout_cmu_shared2_div2",
+ "dout_cmu_shared3_div2",
+ "fout_spare_pll", "oscclk", "oscclk",
+ "oscclk" };
+
+PNAME(mout_hsi2_mmc_card_p) = { "fout_shared2_pll", "fout_shared3_pll",
+ "dout_cmu_shared0_div4", "fout_spare_pll" };
+
+PNAME(mout_hsi2_bus_user_p) = { "oscclk", "dout_cmu_hsi2_bus" };
+PNAME(mout_hsi2_pcie_user_p) = { "oscclk", "dout_cmu_hsi2_pcie" };
+PNAME(mout_hsi2_ufs_embd_user_p) = { "oscclk", "dout_cmu_hsi2_ufs_embd" };
+PNAME(mout_hsi2_mmc_card_user_p) = { "oscclk", "dout_cmu_hsi2_mmc_card" };
+
+static const struct samsung_mux_clock hsi2_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_HSI2_BUS_USER, "mout_hsi2_bus_user", mout_hsi2_bus_user_p,
+ PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER, 4, 1),
+ MUX(CLK_MOUT_HSI2_MMC_CARD_USER, "mout_hsi2_mmc_card_user",
+ mout_hsi2_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER,
+ 4, 1),
+ MUX(CLK_MOUT_HSI2_PCIE_USER, "mout_hsi2_pcie_user",
+ mout_hsi2_pcie_user_p, PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER,
+ 4, 1),
+ MUX(CLK_MOUT_HSI2_UFS_EMBD_USER, "mout_hsi2_ufs_embd_user",
+ mout_hsi2_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
+ 4, 1),
+};
+
+static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = {
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_PHY_REFCLK_IN,
+ "gout_hsi2_pcie_gen4_1_pcie_003_phy_refclk_in",
+ "mout_hsi2_pcie_user",
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_PHY_REFCLK_IN,
+ "gout_hsi2_pcie_gen4_1_pcie_004_phy_refclk_in",
+ "mout_hsi2_pcie_user",
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_ACLK,
+ "gout_hsi2_ssmt_pcie_ia_gen4a_1_aclk",
+ "mout_hsi2_bus_user",
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_PCLK,
+ "gout_hsi2_ssmt_pcie_ia_gen4a_1_pclk",
+ "mout_hsi2_bus_user",
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_ACLK,
+ "gout_hsi2_ssmt_pcie_ia_gen4b_1_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_PCLK,
+ "gout_hsi2_ssmt_pcie_ia_gen4b_1_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_D_TZPC_HSI2_PCLK,
+ "gout_hsi2_d_tzpc_hsi2_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_GPC_HSI2_PCLK,
+ "gout_hsi2_gpc_hsi2_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK, 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_GPIO_HSI2_PCLK,
+ "gout_hsi2_gpio_hsi2_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+
+ /* Disabling this clock makes the system hang. Mark the clock as critical. */
+ GATE(CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK,
+ "gout_hsi2_hsi2_cmu_hsi2_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK,
+ 21, CLK_IS_CRITICAL, 0),
+
+ GATE(CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK,
+ "gout_hsi2_lhm_axi_p_hsi2_i_clk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK,
+ "gout_hsi2_lhs_acel_d_hsi2_i_clk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_MMC_CARD_I_ACLK,
+ "gout_hsi2_mmc_card_i_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_MMC_CARD_SDCLKIN,
+ "gout_hsi2_mmc_card_sdclkin", "mout_hsi2_mmc_card_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_DBI_ACLK_UG,
+ "gout_hsi2_pcie_gen4_1_pcie_003_dbi_aclk_ug", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_MSTR_ACLK_UG,
+ "gout_hsi2_pcie_gen4_1_pcie_003_mstr_aclk_ug",
+ "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_SLV_ACLK_UG,
+ "gout_hsi2_pcie_gen4_1_pcie_003_slv_aclk_ug", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_I_DRIVER_APB_CLK,
+ "gout_hsi2_pcie_gen4_1_pcie_003_i_driver_apb_clk",
+ "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_DBI_ACLK_UG,
+ "gout_hsi2_pcie_gen4_1_pcie_004_dbi_aclk_ug", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_MSTR_ACLK_UG,
+ "gout_hsi2_pcie_gen4_1_pcie_004_mstr_aclk_ug",
+ "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_SLV_ACLK_UG,
+ "gout_hsi2_pcie_gen4_1_pcie_004_slv_aclk_ug", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_I_DRIVER_APB_CLK,
+ "gout_hsi2_pcie_gen4_1_pcie_004_i_driver_apb_clk",
+ "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PHY_UDBG_I_APB_PCLK,
+ "gout_hsi2_pcie_gen4_1_pcs_pma_phy_udbg_i_apb_pclk",
+ "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PIPE_PAL_PCIE_I_APB_PCLK,
+ "gout_hsi2_pcie_gen4_1_pcs_pma_pipe_pal_pcie_i_apb_pclk",
+ "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PCIEPHY210X2_QCH_I_APB_PCLK,
+ "gout_hsi2_pcie_gen4_1_pcs_pma_pciephy210x2_qch_i_apb_pclk",
+ "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_IA_GEN4A_1_I_CLK,
+ "gout_hsi2_pcie_ia_gen4a_1_i_clk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PCIE_IA_GEN4B_1_I_CLK,
+ "gout_hsi2_pcie_ia_gen4b_1_i_clk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PPMU_HSI2_ACLK,
+ "gout_hsi2_ppmu_hsi2_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_PPMU_HSI2_PCLK,
+ "gout_hsi2_ppmu_hsi2_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_ACLK,
+ "gout_hsi2_qe_mmc_card_hsi2_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_PCLK,
+ "gout_hsi2_qe_mmc_card_hsi2_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_ACLK,
+ "gout_hsi2_qe_pcie_gen4a_hsi2_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_PCLK,
+ "gout_hsi2_qe_pcie_gen4a_hsi2_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_ACLK,
+ "gout_hsi2_qe_pcie_gen4b_hsi2_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_PCLK,
+ "gout_hsi2_qe_pcie_gen4b_hsi2_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK,
+ "gout_hsi2_qe_ufs_embd_hsi2_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK,
+ "gout_hsi2_qe_ufs_embd_hsi2_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK,
+ "gout_hsi2_clk_hsi2_bus_clk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_CLK_HSI2_OSCCLK_CLK,
+ "gout_hsi2_clk_hsi2_oscclk_clk", "oscclk",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_SSMT_HSI2_ACLK,
+ "gout_hsi2_ssmt_hsi2_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_SSMT_HSI2_PCLK,
+ "gout_hsi2_ssmt_hsi2_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2,
+ "gout_hsi2_sysmmu_hsi2_clk_s2", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_SYSREG_HSI2_PCLK,
+ "gout_hsi2_sysreg_hsi2_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK,
+ 21, CLK_IS_CRITICAL, 0),
+
+ GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK,
+ "gout_hsi2_uasc_pcie_gen4a_dbi_1_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_PCLK,
+ "gout_hsi2_uasc_pcie_gen4a_dbi_1_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_ACLK,
+ "gout_hsi2_uasc_pcie_gen4a_slv_1_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_PCLK,
+ "gout_hsi2_uasc_pcie_gen4a_slv_1_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_ACLK,
+ "gout_hsi2_uasc_pcie_gen4b_dbi_1_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_PCLK,
+ "gout_hsi2_uasc_pcie_gen4b_dbi_1_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_ACLK,
+ "gout_hsi2_uasc_pcie_gen4b_slv_1_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_PCLK,
+ "gout_hsi2_uasc_pcie_gen4b_slv_1_pclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_UFS_EMBD_I_ACLK,
+ "gout_hsi2_ufs_embd_i_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO,
+ "gout_hsi2_ufs_embd_i_clk_unipro", "mout_hsi2_ufs_embd_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK,
+ "gout_hsi2_ufs_embd_i_fmp_clk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_XIU_D_HSI2_ACLK,
+ "gout_hsi2_xiu_d_hsi2_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK,
+ 21, 0, 0),
+
+ GATE(CLK_GOUT_HSI2_XIU_P_HSI2_ACLK,
+ "gout_hsi2_xiu_p_hsi2_aclk", "mout_hsi2_bus_user",
+ CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK,
+ 21, 0, 0),
+};
+
+static const struct samsung_cmu_info hsi2_cmu_info __initconst = {
+ .mux_clks = hsi2_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(hsi2_mux_clks),
+ .gate_clks = hsi2_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(hsi2_gate_clks),
+ .nr_clk_ids = CLKS_NR_HSI2,
+ .clk_regs = cmu_hsi2_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cmu_hsi2_clk_regs),
+ .clk_name = "bus",
+};
+
/* ---- platform_driver ----------------------------------------------------- */

static int __init gs101_cmu_probe(struct platform_device *pdev)
@@ -3432,6 +3987,9 @@ static const struct of_device_id gs101_cmu_of_match[] = {
}, {
.compatible = "google,gs101-cmu-peric1",
.data = &peric1_cmu_info,
+ }, {
+ .compatible = "google,gs101-cmu-hsi2",
+ .data = &hsi2_cmu_info,
}, {
},
};
diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h
index 3dac3577788a..ac239ce6821b 100644
--- a/include/dt-bindings/clock/google,gs101.h
+++ b/include/dt-bindings/clock/google,gs101.h
@@ -518,4 +518,67 @@
#define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK 45
#define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 46

+/* CMU_HSI2 */
+
+#define CLK_MOUT_HSI2_BUS_USER 1
+#define CLK_MOUT_HSI2_MMC_CARD_USER 2
+#define CLK_MOUT_HSI2_PCIE_USER 3
+#define CLK_MOUT_HSI2_UFS_EMBD_USER 4
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_PHY_REFCLK_IN 5
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_PHY_REFCLK_IN 6
+#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_ACLK 7
+#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_PCLK 8
+#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_ACLK 9
+#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_PCLK 10
+#define CLK_GOUT_HSI2_D_TZPC_HSI2_PCLK 11
+#define CLK_GOUT_HSI2_GPC_HSI2_PCLK 12
+#define CLK_GOUT_HSI2_GPIO_HSI2_PCLK 13
+#define CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK 14
+#define CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK 15
+#define CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK 16
+#define CLK_GOUT_HSI2_MMC_CARD_I_ACLK 17
+#define CLK_GOUT_HSI2_MMC_CARD_SDCLKIN 18
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_DBI_ACLK_UG 19
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_MSTR_ACLK_UG 20
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_SLV_ACLK_UG 21
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_I_DRIVER_APB_CLK 22
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_DBI_ACLK_UG 23
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_MSTR_ACLK_UG 24
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_SLV_ACLK_UG 25
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_I_DRIVER_APB_CLK 26
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PHY_UDBG_I_APB_PCLK 27
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PIPE_PAL_PCIE_I_APB_PCLK 28
+#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PCIEPHY210X2_QCH_I_APB_PCLK 29
+#define CLK_GOUT_HSI2_PCIE_IA_GEN4A_1_I_CLK 30
+#define CLK_GOUT_HSI2_PCIE_IA_GEN4B_1_I_CLK 31
+#define CLK_GOUT_HSI2_PPMU_HSI2_ACLK 32
+#define CLK_GOUT_HSI2_PPMU_HSI2_PCLK 33
+#define CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_ACLK 34
+#define CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_PCLK 35
+#define CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_ACLK 36
+#define CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_PCLK 37
+#define CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_ACLK 38
+#define CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_PCLK 39
+#define CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK 40
+#define CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK 41
+#define CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK 42
+#define CLK_GOUT_HSI2_CLK_HSI2_OSCCLK_CLK 43
+#define CLK_GOUT_HSI2_SSMT_HSI2_ACLK 44
+#define CLK_GOUT_HSI2_SSMT_HSI2_PCLK 45
+#define CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2 46
+#define CLK_GOUT_HSI2_SYSREG_HSI2_PCLK 47
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK 48
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_PCLK 49
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_ACLK 50
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_PCLK 51
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_ACLK 52
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_PCLK 53
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_ACLK 54
+#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_PCLK 55
+#define CLK_GOUT_HSI2_UFS_EMBD_I_ACLK 56
+#define CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO 57
+#define CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK 58
+#define CLK_GOUT_HSI2_XIU_D_HSI2_ACLK 59
+#define CLK_GOUT_HSI2_XIU_P_HSI2_ACLK 60
+
#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
--
2.44.0.478.gd926399ef9-goog

2024-04-04 12:37:59

[permalink] [raw]

Subject: [PATCH 09/17] phy: samsung-ufs: use exynos_get_pmu_regmap_by_phandle() to obtain PMU regmap

This allows us to obtain a PMU regmap that is created by the exynos-pmu
driver. Platforms such as gs101 require exynos-pmu created regmap to
issue SMC calls for PMU register accesses. Existing platforms still get
a MMIO regmap as before.

Signed-off-by: Peter Griffin <[email protected]>
---
drivers/phy/samsung/phy-samsung-ufs.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
index 183c88e3d1ec..c567efafc30f 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.c
+++ b/drivers/phy/samsung/phy-samsung-ufs.c
@@ -18,6 +18,7 @@
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include <linux/soc/samsung/exynos-pmu.h>

#include "phy-samsung-ufs.h"

@@ -255,8 +256,8 @@ static int samsung_ufs_phy_probe(struct platform_device *pdev)
goto out;
}

- phy->reg_pmu = syscon_regmap_lookup_by_phandle(
- dev->of_node, "samsung,pmu-syscon");
+ phy->reg_pmu = exynos_get_pmu_regmap_by_phandle(dev->of_node,
+ "samsung,pmu-syscon");
if (IS_ERR(phy->reg_pmu)) {
err = PTR_ERR(phy->reg_pmu);
dev_err(dev, "failed syscon remap for pmu\n");
--
2.44.0.478.gd926399ef9-goog

2024-04-04 12:39:09

[permalink] [raw]

Subject: [PATCH 13/17] scsi: ufs: host: ufs-exynos: add EXYNOS_UFS_OPT_TIMER_TICK_SELECT option

This option is intended to be set for SoCs that have HCI_V2P1_CTRL
register and can select their tick source via IA_TICK_SEL bit.

Source clock selection for timer tick
0x0 = Bus clock (aclk)
0x1 = Function clock (mclk)

Signed-off-by: Peter Griffin <[email protected]>
---
drivers/ufs/host/ufs-exynos.c | 9 +++++++++
drivers/ufs/host/ufs-exynos.h | 1 +
2 files changed, 10 insertions(+)

diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index 7b68229f6264..1bfda9c75703 100644
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -50,6 +50,8 @@
#define HCI_ERR_EN_N_LAYER 0x80
#define HCI_ERR_EN_T_LAYER 0x84
#define HCI_ERR_EN_DME_LAYER 0x88
+#define HCI_V2P1_CTRL 0x8C
+#define IA_TICK_SEL BIT(16)
#define HCI_CLKSTOP_CTRL 0xB0
#define REFCLKOUT_STOP BIT(4)
#define MPHY_APBCLK_STOP BIT(3)
@@ -1005,6 +1007,13 @@ static void exynos_ufs_fit_aggr_timeout(struct exynos_ufs *ufs)
{
u32 val;

+ /* Select function clock (mclk) for timer tick */
+ if (ufs->opts & EXYNOS_UFS_OPT_TIMER_TICK_SELECT) {
+ val = hci_readl(ufs, HCI_V2P1_CTRL);
+ val |= IA_TICK_SEL;
+ hci_writel(ufs, val, HCI_V2P1_CTRL);
+ }
+
val = exynos_ufs_calc_time_cntr(ufs, IATOVAL_NSEC / CNTR_DIV_VAL);
hci_writel(ufs, val & CNT_VAL_1US_MASK, HCI_1US_TO_CNT_VAL);
}
diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h
index 0fc21b6bbfcd..acf07cc54684 100644
--- a/drivers/ufs/host/ufs-exynos.h
+++ b/drivers/ufs/host/ufs-exynos.h
@@ -222,6 +222,7 @@ struct exynos_ufs {
#define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER BIT(4)
#define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR BIT(5)
#define EXYNOS_UFS_OPT_UFSPR_SECURE BIT(6)
+#define EXYNOS_UFS_OPT_TIMER_TICK_SELECT BIT(7)
};

#define for_each_ufs_rx_lane(ufs, i) \
--
2.44.0.478.gd926399ef9-goog

2024-04-04 12:40:10

[permalink] [raw]

Subject: [PATCH 16/17] scsi: ufs: host: ufs-exynos: Add support for Tensor gs101 SoC

Add a dedicated compatible and drv_data with associated
hooks for gs101 SoC found on Pixel 6.

Note we make use of the previously added EXYNOS_UFS_OPT_UFSPR_SECURE
option, to skip initialisation of UFSPR registers as these are only
accessible via SMC call.

EXYNOS_UFS_OPT_TIMER_TICK_SELECT option is also set to select tick
source. This has been done so as not to effect any existing platforms.

DBG_OPTION_SUITE on gs101 has different address offsets to other SoCs
so these register offsets now come from uic_attr struct.

Signed-off-by: Peter Griffin <[email protected]>
---
drivers/ufs/host/ufs-exynos.c | 146 ++++++++++++++++++++++++++++++++++
drivers/ufs/host/ufs-exynos.h | 14 ++++
2 files changed, 160 insertions(+)

diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index 065258203836..f3f6219f0920 100644
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -61,6 +61,7 @@
#define CLK_STOP_MASK (REFCLKOUT_STOP | REFCLK_STOP |\
UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\
UNIPRO_PCLK_STOP)
+/* HCI_MISC is also known as HCI_FORCE_HCS */
#define HCI_MISC 0xB4
#define REFCLK_CTRL_EN BIT(7)
#define UNIPRO_PCLK_CTRL_EN BIT(6)
@@ -138,6 +139,9 @@ enum {
/*
* UNIPRO registers
*/
+#define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER0 0x7888
+#define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER1 0x788c
+#define UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER2 0x7890
#define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0 0x78B8
#define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1 0x78BC
#define UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2 0x78C0
@@ -938,6 +942,10 @@ static void exynos_ufs_config_unipro(struct exynos_ufs *ufs)
if (attr->pa_dbg_opt_suite1_off)
ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite1_off),
attr->pa_dbg_opt_suite1_val);
+
+ if (attr->pa_dbg_opt_suite2_off)
+ ufshcd_dme_set(hba, UIC_ARG_MIB(attr->pa_dbg_opt_suite2_off),
+ attr->pa_dbg_opt_suite2_val);
}

static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 index)
@@ -1592,6 +1600,96 @@ static int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs,
return 0;
}

+static inline u32 get_mclk_period_unipro_18(struct exynos_ufs *ufs)
+{
+ return (16 * 1000 * 1000000UL / ufs->mclk_rate);
+}
+
+static int gs101_ufs_pre_link(struct exynos_ufs *ufs)
+{
+ struct ufs_hba *hba = ufs->hba;
+ int i;
+ u32 tx_line_reset_period, rx_line_reset_period;
+
+ rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate)
+ / NSEC_PER_MSEC;
+ tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate)
+ / NSEC_PER_MSEC;
+
+ unipro_writel(ufs, get_mclk_period_unipro_18(ufs), COMP_CLK_PERIOD);
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
+
+ for_each_ufs_rx_lane(ufs, i) {
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i),
+ DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i),
+ (rx_line_reset_period >> 16) & 0xFF);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i),
+ (rx_line_reset_period >> 8) & 0xFF);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i),
+ (rx_line_reset_period) & 0xFF);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x69);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6);
+ }
+
+ for_each_ufs_tx_lane(ufs, i) {
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i),
+ DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i),
+ 0x02);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i),
+ (tx_line_reset_period >> 16) & 0xFF);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i),
+ (tx_line_reset_period >> 8) & 0xFF);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i),
+ (tx_line_reset_period) & 0xFF);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x7F, i), 0);
+ }
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), 0x0);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), 0x1);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(0xA006), 0x8000);
+
+ return 0;
+}
+
+static int gs101_ufs_post_link(struct exynos_ufs *ufs)
+{
+ struct ufs_hba *hba = ufs->hba;
+
+ exynos_ufs_enable_dbg_mode(hba);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0x3e8);
+ exynos_ufs_disable_dbg_mode(hba);
+
+ return 0;
+}
+
+static int gs101_ufs_pre_pwr_change(struct exynos_ufs *ufs,
+ struct ufs_pa_layer_attr *pwr)
+{
+ struct ufs_hba *hba = ufs->hba;
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000);
+ unipro_writel(ufs, 8064, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER0);
+ unipro_writel(ufs, 28224, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER1);
+ unipro_writel(ufs, 20160, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER2);
+ unipro_writel(ufs, 12000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0);
+ unipro_writel(ufs, 32000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1);
+ unipro_writel(ufs, 16000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2);
+
+ return 0;
+}
+
static const struct ufs_hba_variant_ops ufs_hba_exynos_ops = {
.name = "exynos_ufs",
.init = exynos_ufs_init,
@@ -1719,6 +1817,34 @@ static const struct exynos_ufs_drv_data exynos_ufs_drvs = {
.post_pwr_change = exynos7_ufs_post_pwr_change,
};

+static struct exynos_ufs_uic_attr gs101_uic_attr = {
+ .tx_trailingclks = 0xff,
+ .tx_dif_p_nsec = 3000000, /* unit: ns */
+ .tx_dif_n_nsec = 1000000, /* unit: ns */
+ .tx_high_z_cnt_nsec = 20000, /* unit: ns */
+ .tx_base_unit_nsec = 100000, /* unit: ns */
+ .tx_gran_unit_nsec = 4000, /* unit: ns */
+ .tx_sleep_cnt = 1000, /* unit: ns */
+ .tx_min_activatetime = 0xa,
+ .rx_filler_enable = 0x2,
+ .rx_dif_p_nsec = 1000000, /* unit: ns */
+ .rx_hibern8_wait_nsec = 4000000, /* unit: ns */
+ .rx_base_unit_nsec = 100000, /* unit: ns */
+ .rx_gran_unit_nsec = 4000, /* unit: ns */
+ .rx_sleep_cnt = 1280, /* unit: ns */
+ .rx_stall_cnt = 320, /* unit: ns */
+ .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf),
+ .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf),
+ .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf),
+ .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf),
+ .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf),
+ .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf),
+ .pa_dbg_opt_suite1_val = 0x90913C1C,
+ .pa_dbg_opt_suite1_off = PA_GS101_DBG_OPTION_SUITE1,
+ .pa_dbg_opt_suite2_val = 0xE01C115F,
+ .pa_dbg_opt_suite2_off = PA_GS101_DBG_OPTION_SUITE2,
+};
+
static struct exynos_ufs_uic_attr fsd_uic_attr = {
.tx_trailingclks = 0x10,
.tx_dif_p_nsec = 3000000, /* unit: ns */
@@ -1762,7 +1888,27 @@ static const struct exynos_ufs_drv_data fsd_ufs_drvs = {
.pre_pwr_change = fsd_ufs_pre_pwr_change,
};

+static const struct exynos_ufs_drv_data gs101_ufs_drvs = {
+ .uic_attr = &gs101_uic_attr,
+ .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
+ UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
+ UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
+ UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
+ UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL |
+ UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING,
+ .opts = EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
+ EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
+ EXYNOS_UFS_OPT_UFSPR_SECURE |
+ EXYNOS_UFS_OPT_TIMER_TICK_SELECT,
+ .drv_init = exynosauto_ufs_drv_init,
+ .pre_link = gs101_ufs_pre_link,
+ .post_link = gs101_ufs_post_link,
+ .pre_pwr_change = gs101_ufs_pre_pwr_change,
+};
+
static const struct of_device_id exynos_ufs_of_match[] = {
+ { .compatible = "google,gs101-ufs",
+ .data = &gs101_ufs_drvs },
{ .compatible = "samsung,exynos7-ufs",
.data = &exynos_ufs_drvs },
{ .compatible = "samsung,exynosautov9-ufs",
diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h
index f30423223474..1646c4a9bb08 100644
--- a/drivers/ufs/host/ufs-exynos.h
+++ b/drivers/ufs/host/ufs-exynos.h
@@ -9,6 +9,12 @@
#ifndef _UFS_EXYNOS_H_
#define _UFS_EXYNOS_H_

+/*
+ * Component registers
+ */
+
+#define COMP_CLK_PERIOD 0x44
+
/*
* UNIPRO registers
*/
@@ -29,6 +35,14 @@
#define PA_DBG_OPTION_SUITE 0x9564
#define PA_DBG_OPTION_SUITE_DYN 0x9565

+/*
+ * Note: GS101_DBG_OPTION offsets below differ from the TRM
+ * but match the downstream driver. Following the TRM
+ * results in non-functioning UFS.
+ */
+#define PA_GS101_DBG_OPTION_SUITE1 0x956a
+#define PA_GS101_DBG_OPTION_SUITE2 0x956d
+
/*
* MIBs for Transport Layer debug registers
*/
--
2.44.0.478.gd926399ef9-goog

2024-04-04 12:40:26

[permalink] [raw]

Subject: [PATCH 17/17] MAINTAINERS: Add phy-gs101-ufs file to Tensor GS101.

Add the newly created ufs phy for GS101 to MAINTAINERS.

Signed-off-by: Peter Griffin <[email protected]>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 491d48f7c2fa..48ac9bd64f22 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9256,6 +9256,7 @@ S: Maintained
F: Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
F: arch/arm64/boot/dts/exynos/google/
F: drivers/clk/samsung/clk-gs101.c
+F: drivers/phy/samsung/phy-gs101-ufs.c
F: include/dt-bindings/clock/google,gs101.h
K: [gG]oogle.?[tT]ensor

--
2.44.0.478.gd926399ef9-goog

2024-04-04 12:51:04

[permalink] [raw]

Subject: [PATCH 02/17] dt-bindings: soc: google: exynos-sysreg: add dedicated hsi2 sysreg compatible

Update dt schema to include the gs101 hsi2 sysreg compatible.

Signed-off-by: Peter Griffin <[email protected]>
---
.../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml | 2 ++
1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
index c0c6ce8fc786..3ca220582897 100644
--- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
+++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
@@ -15,6 +15,7 @@ properties:
- items:
- enum:
- google,gs101-apm-sysreg
+ - google,gs101-hsi2-sysreg
- google,gs101-peric0-sysreg
- google,gs101-peric1-sysreg
- samsung,exynos3-sysreg
@@ -72,6 +73,7 @@ allOf:
compatible:
contains:
enum:
+ - google,gs101-hsi2-sysreg
- google,gs101-peric0-sysreg
- google,gs101-peric1-sysreg
- samsung,exynos850-cmgp-sysreg
--
2.44.0.478.gd926399ef9-goog

2024-04-04 12:53:14

[permalink] [raw]

Subject: [PATCH 06/17] arm64: dts: exynos: gs101: Add the hsi2 sysreg node

This has some configuration bits such as sharability that
are required by UFS.

Signed-off-by: Peter Griffin <[email protected]>
---
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index 38ac4fb1397e..608369cec47b 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -1265,6 +1265,12 @@ cmu_hsi2: clock-controller@14400000 {
clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card";
};

+ sysreg_hsi2: syscon@14420000 {
+ compatible = "google,gs101-hsi2-sysreg", "syscon";
+ reg = <0x14420000 0x1000>;
+ clocks = <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>;
+ };
+
pinctrl_hsi2: pinctrl@14440000 {
compatible = "google,gs101-pinctrl";
reg = <0x14440000 0x00001000>;
--
2.44.0.478.gd926399ef9-goog

2024-04-04 12:58:40

[permalink] [raw]

Subject: [PATCH 10/17] phy: samsung-ufs: ufs: Add SoC callbacks for calibration and clk data recovery

Some SoCs like gs101 don't fit in well with the existing pll lock and
clock data recovery (CDR) callback used by existing exynos platforms.

Allow SoCs to specifify and implement their own calibration and CDR
functions that can be called by the generic samsung phy code.

Signed-off-by: Peter Griffin <[email protected]>
---
drivers/phy/samsung/phy-exynos7-ufs.c | 1 +
drivers/phy/samsung/phy-exynosautov9-ufs.c | 1 +
drivers/phy/samsung/phy-fsd-ufs.c | 1 +
drivers/phy/samsung/phy-samsung-ufs.c | 13 ++++++++++---
drivers/phy/samsung/phy-samsung-ufs.h | 5 +++++
5 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c b/drivers/phy/samsung/phy-exynos7-ufs.c
index a982e7c128c5..15eec1d9e0e0 100644
--- a/drivers/phy/samsung/phy-exynos7-ufs.c
+++ b/drivers/phy/samsung/phy-exynos7-ufs.c
@@ -82,4 +82,5 @@ const struct samsung_ufs_phy_drvdata exynos7_ufs_phy = {
.clk_list = exynos7_ufs_phy_clks,
.num_clks = ARRAY_SIZE(exynos7_ufs_phy_clks),
.cdr_lock_status_offset = EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
+ .wait_for_cdr = samsung_ufs_phy_wait_for_lock_acq,
};
diff --git a/drivers/phy/samsung/phy-exynosautov9-ufs.c b/drivers/phy/samsung/phy-exynosautov9-ufs.c
index 49e2bcbef0b4..9c3e030f07ba 100644
--- a/drivers/phy/samsung/phy-exynosautov9-ufs.c
+++ b/drivers/phy/samsung/phy-exynosautov9-ufs.c
@@ -71,4 +71,5 @@ const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy = {
.clk_list = exynosautov9_ufs_phy_clks,
.num_clks = ARRAY_SIZE(exynosautov9_ufs_phy_clks),
.cdr_lock_status_offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
+ .wait_for_cdr = samsung_ufs_phy_wait_for_lock_acq,
};
diff --git a/drivers/phy/samsung/phy-fsd-ufs.c b/drivers/phy/samsung/phy-fsd-ufs.c
index d36cabd53434..f2361746db0e 100644
--- a/drivers/phy/samsung/phy-fsd-ufs.c
+++ b/drivers/phy/samsung/phy-fsd-ufs.c
@@ -60,4 +60,5 @@ const struct samsung_ufs_phy_drvdata fsd_ufs_phy = {
.clk_list = fsd_ufs_phy_clks,
.num_clks = ARRAY_SIZE(fsd_ufs_phy_clks),
.cdr_lock_status_offset = FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
+ .wait_for_cdr = samsung_ufs_phy_wait_for_lock_acq,
};
diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
index c567efafc30f..f57a2f2a415d 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.c
+++ b/drivers/phy/samsung/phy-samsung-ufs.c
@@ -46,7 +46,7 @@ static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
}
}

-static int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy)
+int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy, u8 lane)
{
struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
const unsigned int timeout_us = 100000;
@@ -98,8 +98,15 @@ static int samsung_ufs_phy_calibrate(struct phy *phy)
}
}

- if (ufs_phy->ufs_phy_state == CFG_POST_PWR_HS)
- err = samsung_ufs_phy_wait_for_lock_acq(phy);
+ for_each_phy_lane(ufs_phy, i) {
+ if (ufs_phy->ufs_phy_state == CFG_PRE_INIT &&
+ ufs_phy->drvdata->wait_for_cal)
+ err = ufs_phy->drvdata->wait_for_cal(phy, i);
+
+ if (ufs_phy->ufs_phy_state == CFG_POST_PWR_HS &&
+ ufs_phy->drvdata->wait_for_cdr)
+ err = ufs_phy->drvdata->wait_for_cdr(phy, i);
+ }

/**
* In Samsung ufshci, PHY need to be calibrated at different
diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
index e122960cfee8..7de6b574b94d 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.h
+++ b/drivers/phy/samsung/phy-samsung-ufs.h
@@ -112,6 +112,9 @@ struct samsung_ufs_phy_drvdata {
const char * const *clk_list;
int num_clks;
u32 cdr_lock_status_offset;
+ /* SoC's specific operations */
+ int (*wait_for_cal)(struct phy *phy, u8 lane);
+ int (*wait_for_cdr)(struct phy *phy, u8 lane);
};

struct samsung_ufs_phy {
@@ -139,6 +142,8 @@ static inline void samsung_ufs_phy_ctrl_isol(
phy->isol.mask, isol ? 0 : phy->isol.en);
}

+int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy, u8 lane);
+
extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy;
extern const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy;
extern const struct samsung_ufs_phy_drvdata fsd_ufs_phy;
--
2.44.0.478.gd926399ef9-goog

2024-04-04 12:59:47

[permalink] [raw]

Subject: [PATCH 12/17] scsi: ufs: host: ufs-exynos: Add EXYNOS_UFS_OPT_UFSPR_SECURE option

This option is intended to be set on platforms whose ufspr
registers are only accessible via smc call (such as gs101).

Signed-off-by: Peter Griffin <[email protected]>
---
drivers/ufs/host/ufs-exynos.c | 4 +++-
drivers/ufs/host/ufs-exynos.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index 734d40f99e31..7b68229f6264 100644
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -1186,7 +1186,9 @@ static int exynos_ufs_init(struct ufs_hba *hba)
if (ret)
goto out;
exynos_ufs_specify_phy_time_attr(ufs);
- exynos_ufs_config_smu(ufs);
+
+ if (!(ufs->opts & EXYNOS_UFS_OPT_UFSPR_SECURE))
+ exynos_ufs_config_smu(ufs);
return 0;

out:
diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h
index a4bd6646d7f1..0fc21b6bbfcd 100644
--- a/drivers/ufs/host/ufs-exynos.h
+++ b/drivers/ufs/host/ufs-exynos.h
@@ -221,6 +221,7 @@ struct exynos_ufs {
#define EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX BIT(3)
#define EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER BIT(4)
#define EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR BIT(5)
+#define EXYNOS_UFS_OPT_UFSPR_SECURE BIT(6)
};

#define for_each_ufs_rx_lane(ufs, i) \
--
2.44.0.478.gd926399ef9-goog

2024-04-04 13:00:42

[permalink] [raw]

Subject: [PATCH 14/17] scsi: ufs: host: ufs-exynos: allow max frequencies up to 267Mhz

Platforms such as Tensor gs101 the pclk frequency is 267Mhz.
Increase PCLK_AVAIL_MAX so we don't fail the frequency check.

Signed-off-by: Peter Griffin <[email protected]>
---
drivers/ufs/host/ufs-exynos.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h
index acf07cc54684..7acc13914100 100644
--- a/drivers/ufs/host/ufs-exynos.h
+++ b/drivers/ufs/host/ufs-exynos.h
@@ -116,7 +116,7 @@ struct exynos_ufs;
#define PA_HIBERN8TIME_VAL 0x20

#define PCLK_AVAIL_MIN 70000000
-#define PCLK_AVAIL_MAX 167000000
+#define PCLK_AVAIL_MAX 267000000

struct exynos_ufs_uic_attr {
/* TX Attributes */
--
2.44.0.478.gd926399ef9-goog

2024-04-04 13:24:52

[permalink] [raw]

Subject: Re: [PATCH 08/17] clk: samsung: gs101: add support for cmu_hsi2

Hi Pete,

Thanks for this!

I haven't reviewed this, but one immediate comment...

On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> [...]
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> index d065e343a85d..b9f84c7d5c22 100644
> --- a/drivers/clk/samsung/clk-gs101.c
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -22,6 +22,7 @@
> #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
> #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)
> #define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1)
> +#define CLKS_NR_HSI2 (CLK_GOUT_HSI2_XIU_P_HSI2_ACLK + 1)

Can you please keep the #defines alphabetical (hsi before misc).

>
> /* ---- CMU_TOP ------------------------------------------------------------- */
>
> @@ -3409,6 +3410,560 @@ static const struct samsung_cmu_info peric1_cmu_info __initconst = {
> .clk_name = "bus",
> };
>
> +/* ---- CMU_HSI2 ---------------------------------------------------------- */

and this code block should be earlier in the file

> [..]

> static int __init gs101_cmu_probe(struct platform_device *pdev)
> @@ -3432,6 +3987,9 @@ static const struct of_device_id gs101_cmu_of_match[] = {
> }, {
> .compatible = "google,gs101-cmu-peric1",
> .data = &peric1_cmu_info,
> + }, {
> + .compatible = "google,gs101-cmu-hsi2",
> + .data = &hsi2_cmu_info,
> }, {

and this block should move up

> },
> };
> diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h
> index 3dac3577788a..ac239ce6821b 100644
> --- a/include/dt-bindings/clock/google,gs101.h
> +++ b/include/dt-bindings/clock/google,gs101.h
> @@ -518,4 +518,67 @@
> #define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK 45
> #define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 46
>
> +/* CMU_HSI2 */

and all these defines, too.

Cheers,
Andre'

2024-04-04 23:00:39

by kernel test robot

[permalink] [raw]

Subject: Re: [PATCH 08/17] clk: samsung: gs101: add support for cmu_hsi2

Hi Peter,

kernel test robot noticed the following build warnings:

[auto build test WARNING on krzk/for-next]
[also build test WARNING on robh/for-next clk/clk-next linus/master v6.9-rc2 next-20240404]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url: https://github.com/intel-lab-lkp/linux/commits/Peter-Griffin/dt-bindings-clock-google-gs101-clock-add-HSI2-clock-management-unit/20240404-205113
base: https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git for-next
patch link: https://lore.kernel.org/r/20240404122559.898930-9-peter.griffin%40linaro.org
patch subject: [PATCH 08/17] clk: samsung: gs101: add support for cmu_hsi2
config: arm64-defconfig (https://download.01.org/0day-ci/archive/20240405/[email protected]/config)
compiler: aarch64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240405/[email protected]/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/

All warnings (new ones prefixed by >>):

In file included from drivers/clk/samsung/clk-gs101.c:16:
>> drivers/clk/samsung/clk-gs101.c:3640:7: warning: 'mout_hsi2_mmc_card_p' defined but not used [-Wunused-const-variable=]
3640 | PNAME(mout_hsi2_mmc_card_p) = { "fout_shared2_pll", "fout_shared3_pll",
| ^~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk.h:229:44: note: in definition of macro 'PNAME'
229 | #define PNAME(x) static const char * const x[] __initconst
| ^
>> drivers/clk/samsung/clk-gs101.c:3633:7: warning: 'mout_hsi2_bus_p' defined but not used [-Wunused-const-variable=]
3633 | PNAME(mout_hsi2_bus_p) = { "dout_cmu_shared0_div4",
| ^~~~~~~~~~~~~~~
drivers/clk/samsung/clk.h:229:44: note: in definition of macro 'PNAME'
229 | #define PNAME(x) static const char * const x[] __initconst
| ^
>> drivers/clk/samsung/clk-gs101.c:3631:7: warning: 'mout_hsi2_pcie_p' defined but not used [-Wunused-const-variable=]
3631 | PNAME(mout_hsi2_pcie_p) = { "oscclk", "dout_cmu_shared2_div2" };
| ^~~~~~~~~~~~~~~~
drivers/clk/samsung/clk.h:229:44: note: in definition of macro 'PNAME'
229 | #define PNAME(x) static const char * const x[] __initconst
| ^
>> drivers/clk/samsung/clk-gs101.c:3628:7: warning: 'mout_hsi2_ufs_embd_p' defined but not used [-Wunused-const-variable=]
3628 | PNAME(mout_hsi2_ufs_embd_p) = { "oscclk", "dout_cmu_shared0_div4",
| ^~~~~~~~~~~~~~~~~~~~
drivers/clk/samsung/clk.h:229:44: note: in definition of macro 'PNAME'
229 | #define PNAME(x) static const char * const x[] __initconst
| ^

vim +/mout_hsi2_mmc_card_p +3640 drivers/clk/samsung/clk-gs101.c

3627
> 3628 PNAME(mout_hsi2_ufs_embd_p) = { "oscclk", "dout_cmu_shared0_div4",
3629 "dout_cmu_shared2_div2", "fout_spare_pll" };
3630
> 3631 PNAME(mout_hsi2_pcie_p) = { "oscclk", "dout_cmu_shared2_div2" };
3632
> 3633 PNAME(mout_hsi2_bus_p) = { "dout_cmu_shared0_div4",
3634 "dout_cmu_shared1_div4",
3635 "dout_cmu_shared2_div2",
3636 "dout_cmu_shared3_div2",
3637 "fout_spare_pll", "oscclk", "oscclk",
3638 "oscclk" };
3639
> 3640 PNAME(mout_hsi2_mmc_card_p) = { "fout_shared2_pll", "fout_shared3_pll",
3641 "dout_cmu_shared0_div4", "fout_spare_pll" };
3642

--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

2024-04-05 07:04:59

[permalink] [raw]

Subject: Re: [PATCH 09/17] phy: samsung-ufs: use exynos_get_pmu_regmap_by_phandle() to obtain PMU regmap

On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> This allows us to obtain a PMU regmap that is created by the exynos-pmu
> driver. Platforms such as gs101 require exynos-pmu created regmap to
> issue SMC calls for PMU register accesses. Existing platforms still get
> a MMIO regmap as before.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> drivers/phy/samsung/phy-samsung-ufs.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
> index 183c88e3d1ec..c567efafc30f 100644
> --- a/drivers/phy/samsung/phy-samsung-ufs.c
> +++ b/drivers/phy/samsung/phy-samsung-ufs.c
> @@ -18,6 +18,7 @@
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
> +#include <linux/soc/samsung/exynos-pmu.h>

You can now drop the include of linux/mfd/syscon.h

Once done, feel free to add

Reviewed-by: André Draszik <[email protected]>

>
> #include "phy-samsung-ufs.h"
>
> @@ -255,8 +256,8 @@ static int samsung_ufs_phy_probe(struct platform_device *pdev)
> goto out;
> }
>
> - phy->reg_pmu = syscon_regmap_lookup_by_phandle(
> - dev->of_node, "samsung,pmu-syscon");
> + phy->reg_pmu = exynos_get_pmu_regmap_by_phandle(dev->of_node,
> + "samsung,pmu-syscon");
> if (IS_ERR(phy->reg_pmu)) {
> err = PTR_ERR(phy->reg_pmu);
> dev_err(dev, "failed syscon remap for pmu\n");

2024-04-05 07:15:26

[permalink] [raw]

Subject: Re: [PATCH 01/17] dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit

Hi Pete,

On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> Add dt schema documentation and clock IDs for the High Speed Interface
> 2 (HSI2) clock management unit. This CMU feeds high speed interfaces
> such as PCIe and UFS.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> .../bindings/clock/google,gs101-clock.yaml    | 30 +++++++++++++++++--
> 1 file changed, 28 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-
> clock.yaml
> index 1d2bcea41c85..a202fd5d1ead 100644
> --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> @@ -32,14 +32,15 @@ properties:
>        - google,gs101-cmu-misc
>        - google,gs101-cmu-peric0
>        - google,gs101-cmu-peric1
> +      - google,gs101-cmu-hsi2

Can you keep this alphabetical and add hsi before misc please.
>
>    clocks:
>      minItems: 1
> -    maxItems: 3
> +    maxItems: 5
>
>    clock-names:
>      minItems: 1
> -    maxItems: 3
> +    maxItems: 5
>
>    "#clock-cells":
>      const: 1
> @@ -112,6 +113,31 @@ allOf:
>              - const: bus
>              - const: ip
>
> + - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - google,gs101-cmu-hsi2

this block should also come before misc please.

Once done, feel free to add

Reviewed-by: André Draszik <[email protected]>

> +
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: External reference clock (24.576 MHz)
> +            - description: High Speed Interface bus clock (from CMU_TOP)
> +            - description: High Speed Interface pcie clock (from CMU_TOP)
> +            - description: High Speed Interface ufs clock (from CMU_TOP)
> +            - description: High Speed Interface mmc clock (from CMU_TOP)
> +
> +        clock-names:
> +          items:
> +            - const: oscclk
> +            - const: bus
> +            - const: pcie
> +            - const: ufs_embd
> +            - const: mmc_card
> +
> additionalProperties: false
>
> examples:

2024-04-05 07:19:51

[permalink] [raw]

Subject: Re: [PATCH 02/17] dt-bindings: soc: google: exynos-sysreg: add dedicated hsi2 sysreg compatible

On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> Update dt schema to include the gs101 hsi2 sysreg compatible.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> .../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml | 2 ++
> 1 file changed, 2 insertions(+)

Reviewed-by: André Draszik <[email protected]>

2024-04-05 07:23:49

[permalink] [raw]

Subject: Re: [PATCH 08/17] clk: samsung: gs101: add support for cmu_hsi2

Hi Pete,

On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h
> index 3dac3577788a..ac239ce6821b 100644
> --- a/include/dt-bindings/clock/google,gs101.h
> +++ b/include/dt-bindings/clock/google,gs101.h
> @@ -518,4 +518,67 @@
> #define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK 45
> #define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 46
>
> +/* CMU_HSI2 */

You need to add these defines as part of the patch that is updating the
binding (patch 1 this series).

Cheers,
Andre'

2024-04-05 07:34:08

[permalink] [raw]

Subject: Re: [PATCH 06/17] arm64: dts: exynos: gs101: Add the hsi2 sysreg node

Hi Pete,

On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> This has some configuration bits such as sharability that
> are required by UFS.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index 38ac4fb1397e..608369cec47b 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -1265,6 +1265,12 @@ cmu_hsi2: clock-controller@14400000 {
> clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card";
> };
>
> + sysreg_hsi2: syscon@14420000 {
> + compatible = "google,gs101-hsi2-sysreg", "syscon";
> + reg = <0x14420000 0x1000>;

Should the length not be 0x10000?

Cheers,
Andre'

2024-04-05 07:40:32

[permalink] [raw]

Subject: Re: [PATCH 05/17] arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller

On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> Enable the cmu_hsi2 clock management unit. It feeds some of
> the high speed interfaces such as PCIe and UFS.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index eddb6b326fde..38ac4fb1397e 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -1253,6 +1253,18 @@ pinctrl_hsi1: pinctrl@11840000 {
> interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
> };
>
> + cmu_hsi2: clock-controller@14400000 {
> + compatible = "google,gs101-cmu-hsi2";
> + reg = <0x14400000 0x4000>;
> + #clock-cells = <1>;
> + clocks = <&ext_24_5m>,
> + <&cmu_top CLK_DOUT_CMU_HSI2_BUS>,
> + <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>,
> + <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>,
> + <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>;
> + clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card";
> + };

This doesn't build because you didn't add the clock ids in the binding patch.

Other than that,

Reviewed-by: André Draszik <[email protected]>

> +
> pinctrl_hsi2: pinctrl@14440000 {
> compatible = "google,gs101-pinctrl";
> reg = <0x14440000 0x00001000>;

2024-04-05 07:47:15

[permalink] [raw]

Subject: Re: [PATCH 01/17] dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit

On 05/04/2024 09:15, André Draszik wrote:
> Hi Pete,
>
> On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
>> Add dt schema documentation and clock IDs for the High Speed Interface
>> 2 (HSI2) clock management unit. This CMU feeds high speed interfaces
>> such as PCIe and UFS.
>>
>> Signed-off-by: Peter Griffin <[email protected]>
>> ---
>> .../bindings/clock/google,gs101-clock.yaml    | 30 +++++++++++++++++--
>> 1 file changed, 28 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-
>> clock.yaml
>> index 1d2bcea41c85..a202fd5d1ead 100644
>> --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
>> +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
>> @@ -32,14 +32,15 @@ properties:
>>        - google,gs101-cmu-misc
>>        - google,gs101-cmu-peric0
>>        - google,gs101-cmu-peric1
>> +      - google,gs101-cmu-hsi2
>
> Can you keep this alphabetical and add hsi before misc please.
>>
>>    clocks:
>>      minItems: 1
>> -    maxItems: 3
>> +    maxItems: 5
>>
>>    clock-names:
>>      minItems: 1
>> -    maxItems: 3
>> +    maxItems: 5
>>
>>    "#clock-cells":
>>      const: 1
>> @@ -112,6 +113,31 @@ allOf:
>>              - const: bus
>>              - const: ip
>>
>> + - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            enum:
>> +              - google,gs101-cmu-hsi2
>
> this block should also come before misc please.
>
> Once done, feel free to add

Yes, please, ack for both.

Best regards,
Krzysztof

2024-04-05 07:49:44

[permalink] [raw]

Subject: Re: [PATCH 03/17] dt-bindings: ufs: exynos-ufs: Add gs101 compatible

On 04/04/2024 14:25, Peter Griffin wrote:
> Add dedicated google,gs101-ufs compatible for Google Tensor gs101
> SoC.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> .../bindings/ufs/samsung,exynos-ufs.yaml | 51 +++++++++++++++----
> 1 file changed, 42 insertions(+), 9 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
> index b2b509b3944d..898da6c0e94f 100644
> --- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
> +++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
> @@ -12,12 +12,10 @@ maintainers:
> description: |
> Each Samsung UFS host controller instance should have its own node.
>
> -allOf:
> - - $ref: ufs-common.yaml
> -
> properties:
> compatible:
> enum:
> + - google,gs101-ufs
> - samsung,exynos7-ufs
> - samsung,exynosautov9-ufs
> - samsung,exynosautov9-ufs-vh
> @@ -38,14 +36,12 @@ properties:
> - const: ufsp
>
> clocks:
> - items:
> - - description: ufs link core clock
> - - description: unipro main clock
> + minItems: 2
> + maxItems: 5

Keep here minItems and:

+ - description: ufs link core clock
+ - description: unipro main clock
+ - description: fmp clock
+ - description: ufs aclk clock
+ - description: ufs pclk clock

>
> clock-names:
> - items:
> - - const: core_clk
> - - const: sclk_unipro_main
> + minItems: 2
> + maxItems: 5

Similarly here

>
> phys:
> maxItems: 1
> @@ -72,6 +68,43 @@ required:
> - clocks
> - clock-names
>
> +allOf:
> + - $ref: ufs-common.yaml
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: google,gs101-ufs
> +
> + then:
> + properties:
> + clocks:

Enough is:
minItems: 5

> + items:

and drop the items since they are defined in top-level.

Your original code is correct, but with my approach we keep the list
synced between variants, at least part of the list. If another variant
appears, then maybe it will go back to your approach, but maybe we can
still have the same clocks and their order.

> + - description: ufs link core clock
> + - description: unipro main clock
> + - description: fmp clock
> + - description: ufs aclk clock
> + - description: ufs pclk clock
> +
> + clock-names:

minItems: 5

> + items:
> + - const: core_clk
> + - const: sclk_unipro_main
> + - const: fmp
> + - const: ufs_aclk
> + - const: ufs_pclk
> + else:
> + properties:
> + clocks:

maxItems: 2

> + items:
> + - description: ufs link core clock
> + - description: unipro main clock
> +
> + clock-names:

maxItems: 2

> + items:
> + - const: core_clk
> + - const: sclk_unipro_main
> +
> unevaluatedProperties: false
>
> examples:

Best regards,
Krzysztof

2024-04-05 07:51:07

[permalink] [raw]

Subject: Re: [PATCH 04/17] dt-bindings: phy: samsung,ufs-phy: Add dedicated gs101-ufs-phy compatible

On 04/04/2024 14:25, Peter Griffin wrote:
> Update dt schema to include the gs101 ufs phy compatible.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml | 1 +
> 1 file changed, 1 insertion(+)

This should go via phy tree. DTS should not depend on other subsystems.

If, after resending as separate series, phy does not take patches for
longer time, feel free to ping me, but first let's try to go via phy/UFS.

Reviewed-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

2024-04-05 07:51:45

[permalink] [raw]

Subject: Re: [PATCH 05/17] arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller

On 04/04/2024 14:25, Peter Griffin wrote:
> Enable the cmu_hsi2 clock management unit. It feeds some of
> the high speed interfaces such as PCIe and UFS.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>

Was it really compiled?

Best regards,
Krzysztof

2024-04-05 07:52:03

[permalink] [raw]

Subject: Re: [PATCH 00/17] HSI2, UFS & UFS phy support for Tensor GS101

On 04/04/2024 14:25, Peter Griffin wrote:
> Hi folks,
>
> This series adds support for the High Speed Interface (HSI) 2 clock
> management unit, UFS controller and UFS phy calibration/tuning for GS101.
>
> With this series applied, UFS is now functional! The SKhynix HN8T05BZGKX015
> can be enumerated, partitions mounted etc. This then allows us to move away
> from the initramfs rootfs we have been using for development so far.
>
> The intention is this series will be merged via Krzysztofs Samsung Exynos
> tree(s). This series is rebased on next-20240404.
>
> The series is broadly split into the following parts:
> 1) dt-bindings documentation updates
> 2) gs101 device tree updates
> 3) Prepatory patches for samsung-ufs driver
> 4) GS101 ufs-phy support
> 5) Prepatory patches for ufs-exynos driver
> 6) GS101 ufs-exynos support

UFS phy and host should go through their trees. What is the
reason/need/requirement to put it into this patchset and merge via
Samsung SoC tree?

Best regards,
Krzysztof

2024-04-05 07:56:13

[permalink] [raw]

Subject: Re: [PATCH 08/17] clk: samsung: gs101: add support for cmu_hsi2

On 04/04/2024 14:25, Peter Griffin wrote:
> CMU_HSI2 is the clock management unit used for the hsi2 block.
> HSI stands for High Speed Interface and as such it generates
> clocks for PCIe, UFS and MMC card.
>
> This patch adds support for the muxes, dividers, and gates in
> cmu_hsi2.
>
> CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK is marked as CLK_IS_CRITICAL
> as disabling it leads to an immediate system hang.
>
> CLK_GOUT_HSI2_SYSREG_HSI2_PCLK is also marked CLK_IS_CRITICAL.
> A hang is not observed with fine grained clock control, but
> UFS IP does not function with syscon controlling this clock
> just around hsi2_sysreg register accesses.
>
> CLK_GOUT_HSI2_GPIO_HSI2_PCLK is marked CLK_IGNORE_UNUSED until
> the exynos pinctrl clock patches land then it can be removed.
>
> Some clocks in this unit have very long names. To help with this
> the clock name mangling strategy was updated to include removing
> the following sub-strings.
> - G4X2_DWC_PCIE_CTL_
> - G4X1_DWC_PCIE_CTL_
> - PCIE_SUB_CTRL_
> - INST_0_
> - LN05LPE_
> - TM_WRAPPER_
> - SF_
>
> Signed-off-by: Peter Griffin <[email protected]>
>
> ---
> Updated regex for clock name mangling
> sed \
> -e 's|^PLL_LOCKTIME_PLL_$[^_]\+$|fout_\L\1_pll|' \
> \
> -e 's|^PLL_CON0_MUX_CLKCMU_$[^_]\+$_$.*$|mout_\L\1_\2|' \
> -e 's|^PLL_CON0_PLL_$.*$|mout_pll_\L\1|' \
> -e 's|^CLK_CON_MUX_MUX_CLK_$.*$|mout_\L\1|' \
> -e '/^PLL_CON[1-4]_[^_]\+_/d' \
> -e '/^[^_]\+_CMU_[^_]\+_CONTROLLER_OPTION/d' \
> -e '/^CLKOUT_CON_BLK_[^_]\+_CMU_[^_]\+_CLKOUT0/d' \
> \
> -e 's|_IPCLKPORT||' \
> -e 's|_RSTNSYNC||' \
> -e 's|_G4X2_DWC_PCIE_CTL||' \
> -e 's|_G4X1_DWC_PCIE_CTL||' \
> -e 's|_PCIE_SUB_CTRL||' \
> -e 's|_INST_0||g' \
> -e 's|_LN05LPE||' \
> -e 's|_TM_WRAPPER||' \
> -e 's|_SF||' \
> \
> -e 's|^CLK_CON_DIV_DIV_CLK_$[^_]\+$_$.*$|dout_\L\1_\2|' \
> \
> -e 's|^CLK_CON_BUF_CLKBUF_$[^_]\+$_$.*$|gout_\L\1_\2|' \
> -e 's|^CLK_CON_GAT_CLK_BLK_$[^_]\+$_UID_$.*$|gout_\L\1_\2|' \
> -e 's|^gout_[^_]\+_[^_]\+_cmu_$[^_]\+$_pclk$|gout_\1_\1_pclk|' \
> -e 's|^CLK_CON_GAT_GOUT_BLK_$[^_]\+$_UID_$.*$|gout_\L\1_\2|' \
> -e 's|^CLK_CON_GAT_CLK_$[^_]\+$_$.*$|gout_\L\1_clk_\L\1_\2|' \
> \
> -e '/^$DMYQCH\|PCH\|QCH\|QUEUE$_/d'
> ---
> drivers/clk/samsung/clk-gs101.c | 558 +++++++++++++++++++++++
> include/dt-bindings/clock/google,gs101.h | 63 +++

Bindings are separate patches.

> 2 files changed, 621 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> index d065e343a85d..b9f84c7d5c22 100644
> --- a/drivers/clk/samsung/clk-gs101.c
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -22,6 +22,7 @@
> #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
> #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)
> #define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1)
> +#define CLKS_NR_HSI2 (CLK_GOUT_HSI2_XIU_P_HSI2_ACLK + 1)
>
> /* ---- CMU_TOP ------------------------------------------------------------- */
>
> @@ -3409,6 +3410,560 @@ static const struct samsung_cmu_info peric1_cmu_info __initconst = {
> .clk_name = "bus",
> };
>
> +/* ---- CMU_HSI2 ---------------------------------------------------------- */
> +
> +/* Register Offset definitions for CMU_HSI2 (0x14400000) */
> +#define PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER 0x0600
> +#define PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER 0x0604
> +#define PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0610
> +#define PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0614
> +#define PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER 0x0620
> +#define PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER 0x0624
> +#define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0630
> +#define PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0634
> +#define HSI2_CMU_HSI2_CONTROLLER_OPTION 0x0800
> +#define CLKOUT_CON_BLK_HSI2_CMU_HSI2_CLKOUT0 0x0810
> +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2000
> +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2004
> +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK 0x2008
> +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK 0x200c
> +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK 0x2010
> +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK 0x2014
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK 0x201c
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK 0x2020
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK 0x2024
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK 0x2028
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK 0x202c
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK 0x2030
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2034
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x2038
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x203c
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2040
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2044
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2048
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x204c
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2050
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2054
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2058
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK 0x205c
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK 0x2060
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK 0x2064

Is it doable to use shorter register names while still keeping them
close to datasheet/manual? This one is a bit too much... actually most
of them are quite too much. :)

..

> +
> /* ---- platform_driver ----------------------------------------------------- */
>
> static int __init gs101_cmu_probe(struct platform_device *pdev)
> @@ -3432,6 +3987,9 @@ static const struct of_device_id gs101_cmu_of_match[] = {
> }, {
> .compatible = "google,gs101-cmu-peric1",
> .data = &peric1_cmu_info,
> + }, {
> + .compatible = "google,gs101-cmu-hsi2",
> + .data = &hsi2_cmu_info,

Keep these also alphabetically ordered by compatible.

Best regards,
Krzysztof

2024-04-05 07:57:35

[permalink] [raw]

Subject: Re: [PATCH 10/17] phy: samsung-ufs: ufs: Add SoC callbacks for calibration and clk data recovery

On 04/04/2024 14:25, Peter Griffin wrote:
> Some SoCs like gs101 don't fit in well with the existing pll lock and
> clock data recovery (CDR) callback used by existing exynos platforms.
>
> Allow SoCs to specifify and implement their own calibration and CDR
> functions that can be called by the generic samsung phy code.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---

Acked-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

2024-04-05 07:57:53

[permalink] [raw]

Subject: Re: [PATCH 11/17] phy: samsung-ufs: ufs: Add support for gs101 UFS phy tuning

On 04/04/2024 14:25, Peter Griffin wrote:
> Add the m-phy tuning values for gs101 UFS phy and SoC callbacks
> gs101_phy_wait_for_calibration() and gs101_phy_wait_for_cdr_lock().
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---

Acked-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

2024-04-05 07:58:59

[permalink] [raw]

Subject: Re: [PATCH 12/17] scsi: ufs: host: ufs-exynos: Add EXYNOS_UFS_OPT_UFSPR_SECURE option

On 04/04/2024 14:25, Peter Griffin wrote:
> This option is intended to be set on platforms whose ufspr
> registers are only accessible via smc call (such as gs101).
>
> Signed-off-by: Peter Griffin <[email protected]>

Acked-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

2024-04-05 07:59:27

[permalink] [raw]

Subject: Re: [PATCH 13/17] scsi: ufs: host: ufs-exynos: add EXYNOS_UFS_OPT_TIMER_TICK_SELECT option

On 04/04/2024 14:25, Peter Griffin wrote:
> This option is intended to be set for SoCs that have HCI_V2P1_CTRL
> register and can select their tick source via IA_TICK_SEL bit.
>
> Source clock selection for timer tick
> 0x0 = Bus clock (aclk)
> 0x1 = Function clock (mclk)
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---

Acked-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

2024-04-05 07:59:43

[permalink] [raw]

Subject: Re: [PATCH 14/17] scsi: ufs: host: ufs-exynos: allow max frequencies up to 267Mhz

On 04/04/2024 14:25, Peter Griffin wrote:
> Platforms such as Tensor gs101 the pclk frequency is 267Mhz.
> Increase PCLK_AVAIL_MAX so we don't fail the frequency check.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---

Acked-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

2024-04-05 08:00:05

[permalink] [raw]

Subject: Re: [PATCH 15/17] scsi: ufs: host: ufs-exynos: add some pa_dbg_ register offsets into drvdata

On 04/04/2024 14:25, Peter Griffin wrote:
> This allows these registers to be at different offsets or not
> exist at all on some SoCs variants.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> drivers/ufs/host/ufs-exynos.c | 38 ++++++++++++++++++++++++-----------
> drivers/ufs/host/ufs-exynos.h | 6 +++++-
> 2 files changed, 31 insertions(+), 13 deletions(-)

Acked-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

2024-04-05 08:00:19

[permalink] [raw]

Subject: Re: [PATCH 07/17] arm64: dts: exynos: gs101: Add ufs, ufs-phy and ufs regulator dt nodes

On 04/04/2024 14:25, Peter Griffin wrote:
> Enable the ufs controller, ufs phy and ufs regulator in device tree.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> .../boot/dts/exynos/google/gs101-oriole.dts | 17 +++++++++
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 35 +++++++++++++++++++

If you wish you can split DTSI and DTS into separate patches. Up to you.

> 2 files changed, 52 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
> index 6be15e990b65..986eb5c9898a 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
> +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
> @@ -53,6 +53,14 @@ button-power {
> wakeup-source;
> };
> };
> +
> + ufs_0_fixed_vcc_reg: regulator-0 {
> + compatible = "regulator-fixed";
> + regulator-name = "ufs-vcc";
> + gpio = <&gpp0 1 0>;

Use defines for GPIO flags, but more important: are you sure this is not
coming from a PMIC? What's the voltage? It looks like a stub for missing
PMIC, because UFS voltages are usually provided by PMIC.

> + regulator-boot-on;
> + enable-active-high;
> + };
> };
>
> &ext_24_5m {
> @@ -106,6 +114,15 @@ &serial_0 {
> status = "okay";
> };
>
> +&ufs_0 {
> + status = "okay";
> + vcc-supply = <&ufs_0_fixed_vcc_reg>;
> +};
> +
> +&ufs_0_phy {
> + status = "okay";
> +};
> +
> &usi_uart {
> samsung,clkreq-on; /* needed for UART mode */
> status = "okay";
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index 608369cec47b..9c94829bf14c 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -1277,6 +1277,41 @@ pinctrl_hsi2: pinctrl@14440000 {
> interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
> };
>
> + ufs_0_phy: phy@17e04000 {
> + compatible = "google,gs101-ufs-phy";
> + reg = <0x14704000 0x3000>;
> + reg-names = "phy-pma";
> + samsung,pmu-syscon = <&pmu_system_controller>;
> + #phy-cells = <0>;
> + clocks = <&ext_24_5m>;
> + clock-names = "ref_clk";
> + status = "disabled";
> + };
> +
> + ufs_0: ufs@14700000 {
> + compatible = "google,gs101-ufs";
> +

Drop blank line.

> + reg = <0x14700000 0x200>,
> + <0x14701100 0x200>,
> + <0x14780000 0xa000>,
> + <0x14600000 0x100>;

Best regards,
Krzysztof

2024-04-05 08:09:05

[permalink] [raw]

Subject: Re: [PATCH 16/17] scsi: ufs: host: ufs-exynos: Add support for Tensor gs101 SoC

On 04/04/2024 14:25, Peter Griffin wrote:
> Add a dedicated compatible and drv_data with associated
> hooks for gs101 SoC found on Pixel 6.
>
> Note we make use of the previously added EXYNOS_UFS_OPT_UFSPR_SECURE
> option, to skip initialisation of UFSPR registers as these are only
> accessible via SMC call.
>
> EXYNOS_UFS_OPT_TIMER_TICK_SELECT option is also set to select tick
> source. This has been done so as not to effect any existing platforms.
>
> DBG_OPTION_SUITE on gs101 has different address offsets to other SoCs
> so these register offsets now come from uic_attr struct.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---

Acked-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

2024-04-05 08:09:35

[permalink] [raw]

Subject: Re: [PATCH 17/17] MAINTAINERS: Add phy-gs101-ufs file to Tensor GS101.

On 04/04/2024 14:25, Peter Griffin wrote:
> Add the newly created ufs phy for GS101 to MAINTAINERS.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> MAINTAINERS | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 491d48f7c2fa..48ac9bd64f22 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -9256,6 +9256,7 @@ S: Maintained
> F: Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> F: arch/arm64/boot/dts/exynos/google/
> F: drivers/clk/samsung/clk-gs101.c
> +F: drivers/phy/samsung/phy-gs101-ufs.c

This could go also via phy-tree:

Acked-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

2024-04-06 09:26:45

by Vinod Koul

[permalink] [raw]

Subject: Re: (subset) [PATCH 00/17] HSI2, UFS & UFS phy support for Tensor GS101

On Thu, 04 Apr 2024 13:25:42 +0100, Peter Griffin wrote:
> This series adds support for the High Speed Interface (HSI) 2 clock
> management unit, UFS controller and UFS phy calibration/tuning for GS101.
>
> With this series applied, UFS is now functional! The SKhynix HN8T05BZGKX015
> can be enumerated, partitions mounted etc. This then allows us to move away
> from the initramfs rootfs we have been using for development so far.
>
> [...]

Applied, thanks!

[04/17] dt-bindings: phy: samsung,ufs-phy: Add dedicated gs101-ufs-phy compatible
commit: 724e4fc053fe217d0ed477517ae68db11feab1f5
[09/17] phy: samsung-ufs: use exynos_get_pmu_regmap_by_phandle() to obtain PMU regmap
commit: f2c6d0fa197a1558f4ef50162bb87e6644af232d
[10/17] phy: samsung-ufs: ufs: Add SoC callbacks for calibration and clk data recovery
commit: a4de58a9096b471f9dc1c2bc6bfaa8aa48110c31
[11/17] phy: samsung-ufs: ufs: Add support for gs101 UFS phy tuning
commit: c1cf725db1065153459f0deb69bd4d497a5fd183
[17/17] MAINTAINERS: Add phy-gs101-ufs file to Tensor GS101.
commit: 0338e1d2f933a4ec7ae96ed1f40c39b899e357d7

Best regards,
--
~Vinod

2024-04-08 08:31:05

by Alim Akhtar

[permalink] [raw]

Subject: RE: [PATCH 00/17] HSI2, UFS & UFS phy support for Tensor GS101

Hi Peter

> -----Original Message-----
> From: Peter Griffin <[email protected]>
> Sent: Thursday, April 4, 2024 5:56 PM
> To: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]; linux-samsung-
> [email protected]; [email protected]; linux-arm-
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; Peter Griffin <[email protected]>
> Subject: [PATCH 00/17] HSI2, UFS & UFS phy support for Tensor GS101
>
> Hi folks,
>
>
> Question
> ========
>
> Currently the link comes up in Gear 3 due to ufshcd_init_host_params()
> host_params initialisation. If I update that to use UFS_HS_G4 for
negotiation
> then the link come up in Gear 4. I propose (in a future patch) to use VER
> register offset 0x8 to determine whether to set G4 capability or not (if
major
> version is >= 3).
>
> The bitfield of VER register in gs101 docs is
>
> RSVD [31:16] Reserved
> MJR [15:8] Major version number
> MNR [7:4] Minor version number
> VS [3:0] Version Suffix
>
> Can anyone confirm if other Exynos platforms supported by this driver have
> the same register, and if it conforms to the bitfield described above?
>

VER (offset 0x8) is standard UFS HCI spec, so all vendor need to have this
(unless something really wrong with the HW)
Yes, Exynos and FSD SoC has these bitfield implemented.

>
> 2.44.0.478.gd926399ef9-goog

2024-04-08 15:23:39

[permalink] [raw]

Subject: Re: [PATCH 08/17] clk: samsung: gs101: add support for cmu_hsi2

Hi Pete,

On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> CMU_HSI2 is the clock management unit used for the hsi2 block.
> HSI stands for High Speed Interface and as such it generates
> clocks for PCIe, UFS and MMC card.
>
> This patch adds support for the muxes, dividers, and gates in
> cmu_hsi2.
>
> CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK is marked as CLK_IS_CRITICAL
> as disabling it leads to an immediate system hang.
>
> CLK_GOUT_HSI2_SYSREG_HSI2_PCLK is also marked CLK_IS_CRITICAL.
> A hang is not observed with fine grained clock control, but
> UFS IP does not function with syscon controlling this clock
> just around hsi2_sysreg register accesses.

Would it make sense to add this clock to the &ufs_0 node in the DTS
instead? Seems more natural than a clock that's constantly enabled?

> [...]
>
> Updated regex for clock name mangling
>     sed \
>         -e 's|^PLL_LOCKTIME_PLL_$[^_]\+$|fout_\L\1_pll|' \
>         \
>         -e 's|^PLL_CON0_MUX_CLKCMU_$[^_]\+$_$.*$|mout_\L\1_\2|' \
>         -e 's|^PLL_CON0_PLL_$.*$|mout_pll_\L\1|' \
>         -e 's|^CLK_CON_MUX_MUX_CLK_$.*$|mout_\L\1|' \
>         -e '/^PLL_CON[1-4]_[^_]\+_/d' \
>         -e '/^[^_]\+_CMU_[^_]\+_CONTROLLER_OPTION/d' \
>         -e '/^CLKOUT_CON_BLK_[^_]\+_CMU_[^_]\+_CLKOUT0/d' \
>         \
>         -e 's|_IPCLKPORT||' \
>         -e 's|_RSTNSYNC||' \
>         -e 's|_G4X2_DWC_PCIE_CTL||' \
>         -e 's|_G4X1_DWC_PCIE_CTL||' \
>         -e 's|_PCIE_SUB_CTRL||' \
>         -e 's|_INST_0||g' \
>         -e 's|_LN05LPE||' \
>         -e 's|_TM_WRAPPER||' \
>         -e 's|_SF||' \
>         \
>         -e 's|^CLK_CON_DIV_DIV_CLK_$[^_]\+$_$.*$|dout_\L\1_\2|' \
>         \
>         -e 's|^CLK_CON_BUF_CLKBUF_$[^_]\+$_$.*$|gout_\L\1_\2|' \
>         -e 's|^CLK_CON_GAT_CLK_BLK_$[^_]\+$_UID_$.*$|gout_\L\1_\2|' \
>         -e 's|^gout_[^_]\+_[^_]\+_cmu_$[^_]\+$_pclk$|gout_\1_\1_pclk|' \
>         -e 's|^CLK_CON_GAT_GOUT_BLK_$[^_]\+$_UID_$.*$|gout_\L\1_\2|' \
>         -e 's|^CLK_CON_GAT_CLK_$[^_]\+$_$.*$|gout_\L\1_clk_\L\1_\2|' \
>         \
>         -e '/^$DMYQCH\|PCH\|QCH\|QUEUE$_/d'

Thank you for the updated regex.

> ---
> drivers/clk/samsung/clk-gs101.c          | 558 +++++++++++++++++++++++
> include/dt-bindings/clock/google,gs101.h | 63 +++
> 2 files changed, 621 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> index d065e343a85d..b9f84c7d5c22 100644
> --- a/drivers/clk/samsung/clk-gs101.c
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -22,6 +22,7 @@
> #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
> #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)
> #define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1)
> +#define CLKS_NR_HSI2 (CLK_GOUT_HSI2_XIU_P_HSI2_ACLK + 1)
>
> /* ---- CMU_TOP ------------------------------------------------------------- */
>
> @@ -3409,6 +3410,560 @@ static const struct samsung_cmu_info peric1_cmu_info __initconst = {
> .clk_name = "bus",
> };
>
> +/* ---- CMU_HSI2 ---------------------------------------------------------- */

This comment is shorter that all the other similar comments in this file.

> [...]
> +
> +PNAME(mout_hsi2_bus_user_p) = { "oscclk", "dout_cmu_hsi2_bus" };
> +PNAME(mout_hsi2_pcie_user_p) = { "oscclk", "dout_cmu_hsi2_pcie" };
> +PNAME(mout_hsi2_ufs_embd_user_p) = { "oscclk", "dout_cmu_hsi2_ufs_embd" };
> +PNAME(mout_hsi2_mmc_card_user_p) = { "oscclk", "dout_cmu_hsi2_mmc_card" };

Can you make these alphabetical, too, please, which would also match their usage
below:

> +
> +static const struct samsung_mux_clock hsi2_mux_clks[] __initconst = {
> + MUX(CLK_MOUT_HSI2_BUS_USER, "mout_hsi2_bus_user", mout_hsi2_bus_user_p,
> +     PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER, 4, 1),
> + MUX(CLK_MOUT_HSI2_MMC_CARD_USER, "mout_hsi2_mmc_card_user",
> +     mout_hsi2_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER,
> +     4, 1),
> + MUX(CLK_MOUT_HSI2_PCIE_USER, "mout_hsi2_pcie_user",
> +     mout_hsi2_pcie_user_p, PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER,
> +     4, 1),
> + MUX(CLK_MOUT_HSI2_UFS_EMBD_USER, "mout_hsi2_ufs_embd_user",
> +     mout_hsi2_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
> +     4, 1),
> +};
> +
> +static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = {
> +

Here and below: all these extra empty lines are not needed.

> + GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_PHY_REFCLK_IN,
> +      "gout_hsi2_pcie_gen4_1_pcie_003_phy_refclk_in",
> +      "mout_hsi2_pcie_user",
> +      CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
> +      21, 0, 0),
> +
> + GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_PHY_REFCLK_IN,
> +      "gout_hsi2_pcie_gen4_1_pcie_004_phy_refclk_in",
> +      "mout_hsi2_pcie_user",
> +      CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
> +      21, 0, 0),
> +
> + GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_ACLK,
> +      "gout_hsi2_ssmt_pcie_ia_gen4a_1_aclk",
> +      "mout_hsi2_bus_user",

The two strings fit on the same line.

> +      CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK,
> +      21, 0, 0),
> +
> + GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_PCLK,
> +      "gout_hsi2_ssmt_pcie_ia_gen4a_1_pclk",
> +      "mout_hsi2_bus_user",

dito.

> [...]
> + /* Disabling this clock makes the system hang. Mark the clock as critical. */
> + GATE(CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK,
> +      "gout_hsi2_hsi2_cmu_hsi2_pclk", "mout_hsi2_bus_user",
> +      CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK,
> +      21, CLK_IS_CRITICAL, 0),

I have a similar clock in USB, which also causes a hang if off, I wonder what we
could do better here.

Cheers,
Andre'

2024-04-09 20:31:15

[permalink] [raw]

Subject: Re: [PATCH 12/17] scsi: ufs: host: ufs-exynos: Add EXYNOS_UFS_OPT_UFSPR_SECURE option

On 04/04/2024, Peter Griffin wrote:
> This option is intended to be set on platforms whose ufspr
> registers are only accessible via smc call (such as gs101).
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---

Tested-by: Will McVicker <[email protected]>

I tested this patch series on a Pixel 6 device. I was able to successfully
mount two of the Android ext4 partitions -- efs and metadata.

root@google-gs:~# mount | grep /dev/sda
/dev/sda5 on /mnt/efs type ext4 (rw,relatime)
/dev/sda8 on /mnt/metadata type ext4 (rw,relatime)

Regards,
Will

2024-04-09 20:32:10

[permalink] [raw]

Subject: Re: [PATCH 13/17] scsi: ufs: host: ufs-exynos: add EXYNOS_UFS_OPT_TIMER_TICK_SELECT option

On 04/04/2024, Peter Griffin wrote:
> This option is intended to be set for SoCs that have HCI_V2P1_CTRL
> register and can select their tick source via IA_TICK_SEL bit.
>
> Source clock selection for timer tick
> 0x0 = Bus clock (aclk)
> 0x1 = Function clock (mclk)
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---

Tested-by: Will McVicker <[email protected]>

I tested this patch series on a Pixel 6 device. I was able to successfully
mount two of the Android ext4 partitions -- efs and metadata.

root@google-gs:~# mount | grep /dev/sda
/dev/sda5 on /mnt/efs type ext4 (rw,relatime)
/dev/sda8 on /mnt/metadata type ext4 (rw,relatime)

Regards,
Will

2024-04-09 20:32:38

[permalink] [raw]

Subject: Re: [PATCH 14/17] scsi: ufs: host: ufs-exynos: allow max frequencies up to 267Mhz

On 04/04/2024, Peter Griffin wrote:
> Platforms such as Tensor gs101 the pclk frequency is 267Mhz.
> Increase PCLK_AVAIL_MAX so we don't fail the frequency check.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---

Tested-by: Will McVicker <[email protected]>

I tested this patch series on a Pixel 6 device. I was able to successfully
mount two of the Android ext4 partitions -- efs and metadata.

root@google-gs:~# mount | grep /dev/sda
/dev/sda5 on /mnt/efs type ext4 (rw,relatime)
/dev/sda8 on /mnt/metadata type ext4 (rw,relatime)

Regards,
Will

2024-04-09 20:35:35

[permalink] [raw]

Subject: Re: [PATCH 15/17] scsi: ufs: host: ufs-exynos: add some pa_dbg_ register offsets into drvdata

On 04/04/2024, Peter Griffin wrote:
> This allows these registers to be at different offsets or not
> exist at all on some SoCs variants.
>
> Signed-off-by: Peter Griffin <[email protected]>

Tested-by: Will McVicker <[email protected]>

I tested this patch series on a Pixel 6 device. I was able to successfully
mount two of the Android ext4 partitions -- efs and metadata.

root@google-gs:~# mount | grep /dev/sda
/dev/sda5 on /mnt/efs type ext4 (rw,relatime)
/dev/sda8 on /mnt/metadata type ext4 (rw,relatime)

Regards,
Will

2024-04-09 20:36:26

[permalink] [raw]

Subject: Re: [PATCH 16/17] scsi: ufs: host: ufs-exynos: Add support for Tensor gs101 SoC

On 04/04/2024, Peter Griffin wrote:
> Add a dedicated compatible and drv_data with associated
> hooks for gs101 SoC found on Pixel 6.
>
> Note we make use of the previously added EXYNOS_UFS_OPT_UFSPR_SECURE
> option, to skip initialisation of UFSPR registers as these are only
> accessible via SMC call.
>
> EXYNOS_UFS_OPT_TIMER_TICK_SELECT option is also set to select tick
> source. This has been done so as not to effect any existing platforms.
>
> DBG_OPTION_SUITE on gs101 has different address offsets to other SoCs
> so these register offsets now come from uic_attr struct.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---

Tested-by: Will McVicker <[email protected]>

I tested this patch series on a Pixel 6 device. I was able to successfully
mount two of the Android ext4 partitions -- efs and metadata.

root@google-gs:~# mount | grep /dev/sda
/dev/sda5 on /mnt/efs type ext4 (rw,relatime)
/dev/sda8 on /mnt/metadata type ext4 (rw,relatime)

Regards,
Will

2024-04-10 00:59:41

by Alim Akhtar

[permalink] [raw]

Subject: RE: [PATCH 09/17] phy: samsung-ufs: use exynos_get_pmu_regmap_by_phandle() to obtain PMU regmap

Hi Peter,

> -----Original Message-----
> From: Peter Griffin <[email protected]>
> Sent: Thursday, April 4, 2024 5:56 PM
> To: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]; linux-samsung-
> [email protected]; [email protected]; linux-arm-
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; Peter Griffin <[email protected]>
> Subject: [PATCH 09/17] phy: samsung-ufs: use
> exynos_get_pmu_regmap_by_phandle() to obtain PMU regmap
>
> This allows us to obtain a PMU regmap that is created by the exynos-pmu
> driver. Platforms such as gs101 require exynos-pmu created regmap to issue
> SMC calls for PMU register accesses. Existing platforms still get a MMIO
> regmap as before.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---

Acked-by: Alim Akhtar <[email protected]>

> drivers/phy/samsung/phy-samsung-ufs.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/samsung/phy-samsung-ufs.c
> b/drivers/phy/samsung/phy-samsung-ufs.c
> index 183c88e3d1ec..c567efafc30f 100644
> --- a/drivers/phy/samsung/phy-samsung-ufs.c
> +++ b/drivers/phy/samsung/phy-samsung-ufs.c
> @@ -18,6 +18,7 @@
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
> +#include <linux/soc/samsung/exynos-pmu.h>
>
> #include "phy-samsung-ufs.h"
>
> @@ -255,8 +256,8 @@ static int samsung_ufs_phy_probe(struct
> platform_device *pdev)
> goto out;
> }
>
> - phy->reg_pmu = syscon_regmap_lookup_by_phandle(
> - dev->of_node, "samsung,pmu-syscon");
> + phy->reg_pmu = exynos_get_pmu_regmap_by_phandle(dev-
> >of_node,
> + "samsung,pmu-
> syscon");
> if (IS_ERR(phy->reg_pmu)) {
> err = PTR_ERR(phy->reg_pmu);
> dev_err(dev, "failed syscon remap for pmu\n");
> --
> 2.44.0.478.gd926399ef9-goog

2024-04-10 16:40:44

by Rob Herring

[permalink] [raw]

Subject: Re: [PATCH 02/17] dt-bindings: soc: google: exynos-sysreg: add dedicated hsi2 sysreg compatible

On Thu, 04 Apr 2024 13:25:44 +0100, Peter Griffin wrote:
> Update dt schema to include the gs101 hsi2 sysreg compatible.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> .../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>

Acked-by: Rob Herring <[email protected]>

2024-04-16 10:28:51

[permalink] [raw]

Subject: Re: [PATCH 00/17] HSI2, UFS & UFS phy support for Tensor GS101

Hi Krzysztof,

On Fri, 5 Apr 2024 at 08:45, Krzysztof Kozlowski <[email protected]> wrote:
>
> On 04/04/2024 14:25, Peter Griffin wrote:
> > Hi folks,
> >
> > This series adds support for the High Speed Interface (HSI) 2 clock
> > management unit, UFS controller and UFS phy calibration/tuning for GS101.
> >
> > With this series applied, UFS is now functional! The SKhynix HN8T05BZGKX015
> > can be enumerated, partitions mounted etc. This then allows us to move away
> > from the initramfs rootfs we have been using for development so far.
> >
> > The intention is this series will be merged via Krzysztofs Samsung Exynos
> > tree(s). This series is rebased on next-20240404.
> >
> > The series is broadly split into the following parts:
> > 1) dt-bindings documentation updates
> > 2) gs101 device tree updates
> > 3) Prepatory patches for samsung-ufs driver
> > 4) GS101 ufs-phy support
> > 5) Prepatory patches for ufs-exynos driver
> > 6) GS101 ufs-exynos support
>
> UFS phy and host should go through their trees. What is the
> reason/need/requirement to put it into this patchset and merge via
> Samsung SoC tree?

Good point, there is no requirement for it to all go via Samsung SoC
tree I will remove that from the cover letter in future versions.
I see Vinod has already queued the phy parts of the series which is great :-)

regards,

Peter

2024-04-16 10:30:26

[permalink] [raw]

Subject: Re: [PATCH 00/17] HSI2, UFS & UFS phy support for Tensor GS101

Hi Alim,

Thanks for your review feedback.

On Mon, 8 Apr 2024 at 09:30, Alim Akhtar <[email protected]> wrote:
>
> Hi Peter
>
> > -----Original Message-----
> > From: Peter Griffin <[email protected]>
> > Sent: Thursday, April 4, 2024 5:56 PM
> > To: [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; [email protected]
> > Cc: [email protected]; [email protected];
> > [email protected]; [email protected]; linux-samsung-
> > [email protected]; [email protected]; linux-arm-
> > [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; Peter Griffin <[email protected]>
> > Subject: [PATCH 00/17] HSI2, UFS & UFS phy support for Tensor GS101
> >
> > Hi folks,
> >
> >
> > Question
> > ========
> >
> > Currently the link comes up in Gear 3 due to ufshcd_init_host_params()
> > host_params initialisation. If I update that to use UFS_HS_G4 for
> negotiation
> > then the link come up in Gear 4. I propose (in a future patch) to use VER
> > register offset 0x8 to determine whether to set G4 capability or not (if
> major
> > version is >= 3).
> >
> > The bitfield of VER register in gs101 docs is
> >
> > RSVD [31:16] Reserved
> > MJR [15:8] Major version number
> > MNR [7:4] Minor version number
> > VS [3:0] Version Suffix
> >
> > Can anyone confirm if other Exynos platforms supported by this driver have
> > the same register, and if it conforms to the bitfield described above?
> >
>
> VER (offset 0x8) is standard UFS HCI spec, so all vendor need to have this
> (unless something really wrong with the HW)
> Yes, Exynos and FSD SoC has these bitfield implemented.

Thanks for confirming! I will look to propose something once this
series is merged.

Peter.

2024-04-16 10:54:07

[permalink] [raw]

Subject: Re: [PATCH 01/17] dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit

Hi André,

Thanks for the review feedback.

On Fri, 5 Apr 2024 at 08:15, André Draszik <[email protected]> wrote:
>
> Hi Pete,
>
> On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> > Add dt schema documentation and clock IDs for the High Speed Interface
> > 2 (HSI2) clock management unit. This CMU feeds high speed interfaces
> > such as PCIe and UFS.
> >
> > Signed-off-by: Peter Griffin <[email protected]>
> > ---
> > .../bindings/clock/google,gs101-clock.yaml | 30 +++++++++++++++++--
> > 1 file changed, 28 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clockyaml b/Documentation/devicetree/bindings/clock/google,gs101-
> > clock.yaml
> > index 1d2bcea41c85..a202fd5d1ead 100644
> > --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> > +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> > @@ -32,14 +32,15 @@ properties:
> > - google,gs101-cmu-misc
> > - google,gs101-cmu-peric0
> > - google,gs101-cmu-peric1
> > + - google,gs101-cmu-hsi2
>
> Can you keep this alphabetical and add hsi before misc please.

Will fix

> >
> > clocks:
> > minItems: 1
> > - maxItems: 3
> > + maxItems: 5
> >
> > clock-names:
> > minItems: 1
> > - maxItems: 3
> > + maxItems: 5
> >
> > "#clock-cells":
> > const: 1
> > @@ -112,6 +113,31 @@ allOf:
> > - const: bus
> > - const: ip
> >
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - google,gs101-cmu-hsi2
>
> this block should also come before misc please.

Will fix

>
> Once done, feel free to add
>
> Reviewed-by: André Draszik <[email protected]>

Thanks!

regards,

Pete

2024-04-16 11:31:21

[permalink] [raw]

Subject: Re: [PATCH 03/17] dt-bindings: ufs: exynos-ufs: Add gs101 compatible

Hi Krzysztof,

Thanks for the review.

On Fri, 5 Apr 2024 at 08:49, Krzysztof Kozlowski <[email protected]> wrote:
>
> On 04/04/2024 14:25, Peter Griffin wrote:
> > Add dedicated google,gs101-ufs compatible for Google Tensor gs101
> > SoC.
> >
> > Signed-off-by: Peter Griffin <[email protected]>
> > ---
> > .../bindings/ufs/samsung,exynos-ufs.yaml | 51 +++++++++++++++----
> > 1 file changed, 42 insertions(+), 9 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
> > index b2b509b3944d..898da6c0e94f 100644
> > --- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
> > +++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
> > @@ -12,12 +12,10 @@ maintainers:
> > description: |
> > Each Samsung UFS host controller instance should have its own node.
> >
> > -allOf:
> > - - $ref: ufs-common.yaml
> > -
> > properties:
> > compatible:
> > enum:
> > + - google,gs101-ufs
> > - samsung,exynos7-ufs
> > - samsung,exynosautov9-ufs
> > - samsung,exynosautov9-ufs-vh
> > @@ -38,14 +36,12 @@ properties:
> > - const: ufsp
> >
> > clocks:
> > - items:
> > - - description: ufs link core clock
> > - - description: unipro main clock
> > + minItems: 2
> > + maxItems: 5
>
> Keep here minItems and:
>
> + - description: ufs link core clock
> + - description: unipro main clock
> + - description: fmp clock
> + - description: ufs aclk clock
> + - description: ufs pclk clock
>
> >
> > clock-names:
> > - items:
> > - - const: core_clk
> > - - const: sclk_unipro_main
> > + minItems: 2
> > + maxItems: 5
>
> Similarly here
>
> >
> > phys:
> > maxItems: 1
> > @@ -72,6 +68,43 @@ required:
> > - clocks
> > - clock-names
> >
> > +allOf:
> > + - $ref: ufs-common.yaml
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: google,gs101-ufs
> > +
> > + then:
> > + properties:
> > + clocks:
>
> Enough is:
> minItems: 5
>
> > + items:
>
> and drop the items since they are defined in top-level.
>
> Your original code is correct, but with my approach we keep the list
> synced between variants, at least part of the list. If another variant
> appears, then maybe it will go back to your approach, but maybe we can
> still have the same clocks and their order.

Will update like you suggest in v2.

Thanks,

Peter

2024-04-16 11:45:43

[permalink] [raw]

Subject: Re: [PATCH 04/17] dt-bindings: phy: samsung,ufs-phy: Add dedicated gs101-ufs-phy compatible

Hi Krzysztof,

On Fri, 5 Apr 2024 at 08:50, Krzysztof Kozlowski <[email protected]> wrote:
>
> On 04/04/2024 14:25, Peter Griffin wrote:
> > Update dt schema to include the gs101 ufs phy compatible.
> >
> > Signed-off-by: Peter Griffin <[email protected]>
> > ---
> > Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml | 1 +
> > 1 file changed, 1 insertion(+)
>
> This should go via phy tree. DTS should not depend on other subsystems.
>
> If, after resending as separate series, phy does not take patches for
> longer time, feel free to ping me, but first let's try to go via phy/UFS.
>
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>

Thanks for the review. fyi Vinod has now queued this and the other ufs
phy patches :)

regards,

Peter

2024-04-16 11:57:16

[permalink] [raw]

Subject: Re: [PATCH 05/17] arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller

Hi André,

Thanks for the review.

On Fri, 5 Apr 2024 at 08:38, André Draszik <[email protected]> wrote:
>
> On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> > Enable the cmu_hsi2 clock management unit. It feeds some of
> > the high speed interfaces such as PCIe and UFS.
> >
> > Signed-off-by: Peter Griffin <[email protected]>
> > ---
> > arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > index eddb6b326fde..38ac4fb1397e 100644
> > --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > @@ -1253,6 +1253,18 @@ pinctrl_hsi1: pinctrl@11840000 {
> > interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
> > };
> >
> > + cmu_hsi2: clock-controller@14400000 {
> > + compatible = "google,gs101-cmu-hsi2";
> > + reg = <0x14400000 0x4000>;
> > + #clock-cells = <1>;
> > + clocks = <&ext_24_5m>,
> > + <&cmu_top CLK_DOUT_CMU_HSI2_BUS>,
> > + <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>,
> > + <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>,
> > + <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>;
> > + clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card";
> > + };
>
> This doesn't build because you didn't add the clock ids in the binding patch.

These clock IDs are for cmu_top, not cmu_hsi2. They were added as part
of the initial gs101/Oriole upstream support series in the following
commit

commit 0a910f1606384a5886a045e36b1fc80a7fa6706b
Author: Peter Griffin <[email protected]>
Date: Sat Dec 9 23:30:48 2023 +0000

dt-bindings: clock: Add Google gs101 clock management unit bindings

Provide dt-schema documentation for Google gs101 SoC clock controller.
Currently this adds support for cmu_top, cmu_misc and cmu_apm.

Reviewed-by: Sam Protsenko <[email protected]>
Signed-off-by: Peter Griffin <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>

regards,

Peter

2024-04-16 12:14:26

[permalink] [raw]

Subject: Re: [PATCH 06/17] arm64: dts: exynos: gs101: Add the hsi2 sysreg node

Hi André,

Thanks for the review.

On Fri, 5 Apr 2024 at 08:33, André Draszik <[email protected]> wrote:
>
> Hi Pete,
>
> On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> > This has some configuration bits such as sharability that
> > are required by UFS.
> >
> > Signed-off-by: Peter Griffin <[email protected]>
> > ---
> > arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > index 38ac4fb1397e..608369cec47b 100644
> > --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > @@ -1265,6 +1265,12 @@ cmu_hsi2: clock-controller@14400000 {
> > clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card";
> > };
> >
> > + sysreg_hsi2: syscon@14420000 {
> > + compatible = "google,gs101-hsi2-sysreg", "syscon";
> > + reg = <0x14420000 0x1000>;
>
> Should the length not be 0x10000?

The downstream kernel uses a length of 0x1000 for all the
foobar-sysreg nodes, but checking the specs it does indeed seem that
the length should be 0x10000 (and that is what we've used for all the
other sysreg nodes upstream).

Will update this in v2.

regards,

Pete

2024-04-16 12:22:10

[permalink] [raw]

Subject: Re: [PATCH 05/17] arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller

Hi Pete,

On Tue, 2024-04-16 at 12:56 +0100, Peter Griffin wrote:
> Hi André,
>
> Thanks for the review.
>
> On Fri, 5 Apr 2024 at 08:38, André Draszik <[email protected]> wrote:
> >
> > On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> > > Enable the cmu_hsi2 clock management unit. It feeds some of
> > > the high speed interfaces such as PCIe and UFS.
> > >
> > > Signed-off-by: Peter Griffin <[email protected]>
> > > ---
> > > arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++
> > > 1 file changed, 12 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > > index eddb6b326fde..38ac4fb1397e 100644
> > > --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > > @@ -1253,6 +1253,18 @@ pinctrl_hsi1: pinctrl@11840000 {
> > >                       interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
> > >               };
> > >
> > > +             cmu_hsi2: clock-controller@14400000 {
> > > +                     compatible = "google,gs101-cmu-hsi2";
> > > +                     reg = <0x14400000 0x4000>;
> > > +                     #clock-cells = <1>;
> > > +                     clocks = <&ext_24_5m>,
> > > +                              <&cmu_top CLK_DOUT_CMU_HSI2_BUS>,
> > > +                              <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>,
> > > +                              <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>,
> > > +                              <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>;
> > > +                     clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card";
> > > +             };
> >
> > This doesn't build because you didn't add the clock ids in the binding patch.
>
> These clock IDs are for cmu_top, not cmu_hsi2.

Right. I replied to the wrong patch. Sorry for that. It is patch 7 that
uses clock ids that are only added in patch 8. The clock ids from patch 8
in include/dt-bindings/clock/google,gs101.h should be added in patch 1
instead.

Cheers,
Andre'

2024-04-16 14:35:46

[permalink] [raw]

Subject: Re: [PATCH 05/17] arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller

Hi André,

On Tue, 16 Apr 2024 at 13:21, André Draszik <[email protected]> wrote:
>
> Hi Pete,
>
> On Tue, 2024-04-16 at 12:56 +0100, Peter Griffin wrote:
> > Hi André,
> >
> > Thanks for the review.
> >
> > On Fri, 5 Apr 2024 at 08:38, André Draszik <[email protected]> wrote:
> > >
> > > On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> > > > Enable the cmu_hsi2 clock management unit. It feeds some of
> > > > the high speed interfaces such as PCIe and UFS.
> > > >
> > > > Signed-off-by: Peter Griffin <[email protected]>
> > > > ---
> > > > arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++
> > > > 1 file changed, 12 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > > > index eddb6b326fde..38ac4fb1397e 100644
> > > > --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > > > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > > > @@ -1253,6 +1253,18 @@ pinctrl_hsi1: pinctrl@11840000 {
> > > > interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
> > > > };
> > > >
> > > > + cmu_hsi2: clock-controller@14400000 {
> > > > + compatible = "google,gs101-cmu-hsi2";
> > > > + reg = <0x14400000 0x4000>;
> > > > + #clock-cells = <1>;
> > > > + clocks = <&ext_24_5m>,
> > > > + <&cmu_top CLK_DOUT_CMU_HSI2_BUS>,
> > > > + <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>,
> > > > + <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>,
> > > > + <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>;
> > > > + clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card";
> > > > + };
> > >
> > > This doesn't build because you didn't add the clock ids in the binding patch.
> >
> > These clock IDs are for cmu_top, not cmu_hsi2.
>
> Right. I replied to the wrong patch. Sorry for that. It is patch 7 that
> uses clock ids that are only added in patch 8. The clock ids from patch 8
> in include/dt-bindings/clock/google,gs101.h should be added in patch 1
> instead.

Ah I see, thanks for the clarification. I'll fix that in v2.

Thanks,

Pete

2024-04-17 09:52:34

by Dan Carpenter

[permalink] [raw]

Subject: Re: [PATCH 10/17] phy: samsung-ufs: ufs: Add SoC callbacks for calibration and clk data recovery

On Thu, Apr 04, 2024 at 01:25:52PM +0100, Peter Griffin wrote:
> diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
> index c567efafc30f..f57a2f2a415d 100644
> --- a/drivers/phy/samsung/phy-samsung-ufs.c
> +++ b/drivers/phy/samsung/phy-samsung-ufs.c
> @@ -46,7 +46,7 @@ static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
> }
> }
>
> -static int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy)
> +int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy, u8 lane)
> {
> struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
> const unsigned int timeout_us = 100000;
> @@ -98,8 +98,15 @@ static int samsung_ufs_phy_calibrate(struct phy *phy)
> }
> }
>
> - if (ufs_phy->ufs_phy_state == CFG_POST_PWR_HS)
> - err = samsung_ufs_phy_wait_for_lock_acq(phy);
> + for_each_phy_lane(ufs_phy, i) {
> + if (ufs_phy->ufs_phy_state == CFG_PRE_INIT &&
> + ufs_phy->drvdata->wait_for_cal)
> + err = ufs_phy->drvdata->wait_for_cal(phy, i);
> +
> + if (ufs_phy->ufs_phy_state == CFG_POST_PWR_HS &&
> + ufs_phy->drvdata->wait_for_cdr)
> + err = ufs_phy->drvdata->wait_for_cdr(phy, i);

The "err" value is only preserved from the last iteration in this loop.

regards,
dan carpenter

> + }
>
> /**
> * In Samsung ufshci, PHY need to be calibrated at different

2024-04-18 13:20:56

[permalink] [raw]

Subject: Re: [PATCH 07/17] arm64: dts: exynos: gs101: Add ufs, ufs-phy and ufs regulator dt nodes

Hi Krzysztof,

Thanks for your review feedback.

On Fri, 5 Apr 2024 at 08:53, Krzysztof Kozlowski <[email protected]> wrote:
>
> On 04/04/2024 14:25, Peter Griffin wrote:
> > Enable the ufs controller, ufs phy and ufs regulator in device tree.
> >
> > Signed-off-by: Peter Griffin <[email protected]>
> > ---
> > .../boot/dts/exynos/google/gs101-oriole.dts | 17 +++++++++
> > arch/arm64/boot/dts/exynos/google/gs101.dtsi | 35 +++++++++++++++++++
>
> If you wish you can split DTSI and DTS into separate patches. Up to you.

Thanks for the heads up
>
> > 2 files changed, 52 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
> > index 6be15e990b65..986eb5c9898a 100644
> > --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
> > +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
> > @@ -53,6 +53,14 @@ button-power {
> > wakeup-source;
> > };
> > };
> > +
> > + ufs_0_fixed_vcc_reg: regulator-0 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "ufs-vcc";
> > + gpio = <&gpp0 1 0>;
>
> Use defines for GPIO flags,

Will fix in v2

> but more important: are you sure this is not
> coming from a PMIC? What's the voltage? It looks like a stub for missing
> PMIC, because UFS voltages are usually provided by PMIC.

UFS vcc is 1.2v. The gpio signal from gs101 SoC is called BOOTLD0, and
it is connected to slave pmic (S2MPG11) UFS_EN signal which is a gpio
enabled voltage rail for UFS (LDO8S).

The downstream driver code declares the UFS supply as regulator-fixed
even though it has a fully featured regulator driver for the pmic,
with the LDO8S regulator exposed. Checking the DT for the pmic the min
and max volt are different, so using regulator-fixed seems wrong for
downstream.

s_ldo8_reg: LDO8S {
regulator-name = "S2MPG11_LDO8";
regulator-min-microvolt = <1127800>;
regulator-max-microvolt = <1278600>;
regulator-always-on;
regulator-initial-mode = <SEC_OPMODE_SUSPEND>;
channel-mux-selection = <0x28>;
schematic-name = "L8S_UFS_VCCQ";
subsys-name = "UFS";
};

So I think you're correct this is a stub pending full pmic support. I
propose in v2 to add a comment similar to what we have in
exynos850-e850-96.dts today above the regulator-fixed node like /*
TODO: Remove this once PMIC is implemented */?

regards,

Peter.

>
> > + regulator-boot-on;
> > + enable-active-high;
> > + };
> > };
> >
> > &ext_24_5m {
> > @@ -106,6 +114,15 @@ &serial_0 {
> > status = "okay";
> > };
> >
> > +&ufs_0 {
> > + status = "okay";
> > + vcc-supply = <&ufs_0_fixed_vcc_reg>;
> > +};
> > +
> > +&ufs_0_phy {
> > + status = "okay";
> > +};
> > +
> > &usi_uart {
> > samsung,clkreq-on; /* needed for UART mode */
> > status = "okay";
> > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > index 608369cec47b..9c94829bf14c 100644
> > --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > @@ -1277,6 +1277,41 @@ pinctrl_hsi2: pinctrl@14440000 {
> > interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
> > };
> >
> > + ufs_0_phy: phy@17e04000 {
> > + compatible = "google,gs101-ufs-phy";
> > + reg = <0x14704000 0x3000>;
> > + reg-names = "phy-pma";
> > + samsung,pmu-syscon = <&pmu_system_controller>;
> > + #phy-cells = <0>;
> > + clocks = <&ext_24_5m>;
> > + clock-names = "ref_clk";
> > + status = "disabled";
> > + };
> > +
> > + ufs_0: ufs@14700000 {
> > + compatible = "google,gs101-ufs";
> > +
>
> Drop blank line.
>
> > + reg = <0x14700000 0x200>,
> > + <0x14701100 0x200>,
> > + <0x14780000 0xa000>,
> > + <0x14600000 0x100>;
>
>
> Best regards,
> Krzysztof
>

2024-04-18 17:33:37

[permalink] [raw]

Subject: Re: [PATCH 07/17] arm64: dts: exynos: gs101: Add ufs, ufs-phy and ufs regulator dt nodes

On 18/04/2024 15:20, Peter Griffin wrote:
>
> s_ldo8_reg: LDO8S {
> regulator-name = "S2MPG11_LDO8";
> regulator-min-microvolt = <1127800>;
> regulator-max-microvolt = <1278600>;
> regulator-always-on;
> regulator-initial-mode = <SEC_OPMODE_SUSPEND>;
> channel-mux-selection = <0x28>;
> schematic-name = "L8S_UFS_VCCQ";
> subsys-name = "UFS";
> };
>
> So I think you're correct this is a stub pending full pmic support. I
> propose in v2 to add a comment similar to what we have in
> exynos850-e850-96.dts today above the regulator-fixed node like /*
> TODO: Remove this once PMIC is implemented */?
>

Sounds good.

Best regards,
Krzysztof

2024-04-22 12:40:23

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Subject: Re: [PATCH 10/17] phy: samsung-ufs: ufs: Add SoC callbacks for calibration and clk data recovery

Hi Dan,

Thanks for the review.

On Wed, 17 Apr 2024 at 10:52, Dan Carpenter <[email protected]> wrote:
>
> On Thu, Apr 04, 2024 at 01:25:52PM +0100, Peter Griffin wrote:
> > diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
> > index c567efafc30f..f57a2f2a415d 100644
> > --- a/drivers/phy/samsung/phy-samsung-ufs.c
> > +++ b/drivers/phy/samsung/phy-samsung-ufs.c
> > @@ -46,7 +46,7 @@ static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
> > }
> > }
> >
> > -static int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy)
> > +int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy, u8 lane)
> > {
> > struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
> > const unsigned int timeout_us = 100000;
> > @@ -98,8 +98,15 @@ static int samsung_ufs_phy_calibrate(struct phy *phy)
> > }
> > }
> >
> > - if (ufs_phy->ufs_phy_state == CFG_POST_PWR_HS)
> > - err = samsung_ufs_phy_wait_for_lock_acq(phy);
> > + for_each_phy_lane(ufs_phy, i) {
> > + if (ufs_phy->ufs_phy_state == CFG_PRE_INIT &&
> > + ufs_phy->drvdata->wait_for_cal)
> > + err = ufs_phy->drvdata->wait_for_cal(phy, i);
> > +
> > + if (ufs_phy->ufs_phy_state == CFG_POST_PWR_HS &&
> > + ufs_phy->drvdata->wait_for_cdr)
> > + err = ufs_phy->drvdata->wait_for_cdr(phy, i);
>
> The "err" value is only preserved from the last iteration in this loop.

I'll send a follow up patch for this as it's already applied.

Thanks,

Peter

2024-04-22 12:44:41

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Subject: Re: [PATCH 09/17] phy: samsung-ufs: use exynos_get_pmu_regmap_by_phandle() to obtain PMU regmap

Hi André,

Thanks for the review feedback.

On Fri, 5 Apr 2024 at 08:04, André Draszik <[email protected]> wrote:
>
> On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> > This allows us to obtain a PMU regmap that is created by the exynos-pmu
> > driver. Platforms such as gs101 require exynos-pmu created regmap to
> > issue SMC calls for PMU register accesses. Existing platforms still get
> > a MMIO regmap as before.
> >
> > Signed-off-by: Peter Griffin <[email protected]>
> > ---
> > drivers/phy/samsung/phy-samsung-ufs.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
> > index 183c88e3d1ec..c567efafc30f 100644
> > --- a/drivers/phy/samsung/phy-samsung-ufs.c
> > +++ b/drivers/phy/samsung/phy-samsung-ufs.c
> > @@ -18,6 +18,7 @@
> > #include <linux/phy/phy.h>
> > #include <linux/platform_device.h>
> > #include <linux/regmap.h>
> > +#include <linux/soc/samsung/exynos-pmu.h>
>
> You can now drop the include of linux/mfd/syscon.h

I'll send a followup patch for this.

Thanks,

Peter

2024-04-22 14:56:19

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Subject: Re: [PATCH 08/17] clk: samsung: gs101: add support for cmu_hsi2

Hi André,

On Thu, 4 Apr 2024 at 14:24, André Draszik <[email protected]> wrote:
>
> Hi Pete,
>
> Thanks for this!
>
> I haven't reviewed this, but one immediate comment...
>
> On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> > [...]
> > diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> > index d065e343a85d..b9f84c7d5c22 100644
> > --- a/drivers/clk/samsung/clk-gs101.c
> > +++ b/drivers/clk/samsung/clk-gs101.c
> > @@ -22,6 +22,7 @@
> > #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
> > #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)
> > #define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1)
> > +#define CLKS_NR_HSI2 (CLK_GOUT_HSI2_XIU_P_HSI2_ACLK + 1)
>
> Can you please keep the #defines alphabetical (hsi before misc).

Will fix

>
> >
> > /* ---- CMU_TOP ------------------------------------------------------------- */
> >
> > @@ -3409,6 +3410,560 @@ static const struct samsung_cmu_info peric1_cmu_info __initconst = {
> > .clk_name = "bus",
> > };
> >
> > +/* ---- CMU_HSI2 ---------------------------------------------------------- */
>
> and this code block should be earlier in the file

Will fix
>
> > [..]
>
> > static int __init gs101_cmu_probe(struct platform_device *pdev)
> > @@ -3432,6 +3987,9 @@ static const struct of_device_id gs101_cmu_of_match[] = {
> > }, {
> > .compatible = "google,gs101-cmu-peric1",
> > .data = &peric1_cmu_info,
> > + }, {
> > + .compatible = "google,gs101-cmu-hsi2",
> > + .data = &hsi2_cmu_info,
> > }, {
>
> and this block should move up

Will fix
>
> > },
> > };
> > diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h
> > index 3dac3577788a..ac239ce6821b 100644
> > --- a/include/dt-bindings/clock/google,gs101.h
> > +++ b/include/dt-bindings/clock/google,gs101.h
> > @@ -518,4 +518,67 @@
> > #define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK 45
> > #define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 46
> >
> > +/* CMU_HSI2 */
>
> and all these defines, too.

Will fix.

regards,

Peter

2024-04-23 17:46:15