Hi all,
I rebuilt the 2.4.20 kernel with C3 CPU and found it been downgraded to
i486.
And I check the file, linux/arch/i386/Makefile, in both of 2.4.19 and
2.4.20 kernels.
In 2.4.19, the CFLAGS adds "-march=i586".
But in 2.4.20, the CFLAGS adds
"-march=i486 -malign-functions=0 -malign-jumps=0 -malign-loops=0".
Why do this? Could anybody explain this to me?
BTW, if I substitute"i586" for "i486" and remove other parameters in that
file under 2.4.20, is there any affection during/after rebuilding kernel?
Any help is appreciated.
Best Regards,
Joseph
-----------------------------------------------------------------
< ?C?ѳ? Yahoo!?_?? > http://www.yahoo.com.tw
On Tue, Dec 10, 2002 at 12:02:25PM +0800, Joseph wrote:
> Hi all,
> I rebuilt the 2.4.20 kernel with C3 CPU and found it been downgraded to
> i486.
> And I check the file, linux/arch/i386/Makefile, in both of 2.4.19 and
> 2.4.20 kernels.
> In 2.4.19, the CFLAGS adds "-march=i586".
> But in 2.4.20, the CFLAGS adds
> "-march=i486 -malign-functions=0 -malign-jumps=0 -malign-loops=0".
> Why do this? Could anybody explain this to me?
I believe someone (Jeff Garzik?) benchmarked gcc code generation,
and the C3 executed code scheduled for a 486 faster than it did for
-m586
I'm not sure about the alignment flags. I've been meaning to look
into that myself...
Dave
On Tue, Dec 10, 2002 at 08:22:21AM +0100, Daniel Egger wrote:
> Interesting. I have no clue about which C3 you're talking about here but
> a VIA Ezra has all 686 instructions including cmov and thus optimising
> for PPro works best for me.
Mine disagrees.
(davej@equinox:davej)$ cat /proc/cpuinfo
processor : 0
vendor_id : CentaurHauls
cpu family : 6
model : 8
model name : VIA C3 Ezra
stepping : 9
cpu MHz : 433.362
cache size : 64 KB
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu de tsc msr cx8 mtrr pge mmx 3dnow
bogomips : 865.07
Dave
Am Die, 2002-12-10 um 06.52 schrieb Dave Jones:
> I believe someone (Jeff Garzik?) benchmarked gcc code generation,
> and the C3 executed code scheduled for a 486 faster than it did for
> -m586
> I'm not sure about the alignment flags. I've been meaning to look
> into that myself...
Interesting. I have no clue about which C3 you're talking about here but
a VIA Ezra has all 686 instructions including cmov and thus optimising
for PPro works best for me.
Prolly I would have to do more benchmarking to find out about aligment
advantages.
--
Servus,
Daniel
>>>>> "daniel" == Daniel Egger <[email protected]> writes:
daniel> Am Die, 2002-12-10 um 06.52 schrieb Dave Jones:
>> I believe someone (Jeff Garzik?) benchmarked gcc code generation,
>> and the C3 executed code scheduled for a 486 faster than it did for
>> -m586
>> I'm not sure about the alignment flags. I've been meaning to look
>> into that myself...
daniel> Interesting. I have no clue about which C3 you're talking about here but
daniel> a VIA Ezra has all 686 instructions including cmov and thus optimising
daniel> for PPro works best for me.
Have you tested it?
Here, we got cmov to work if the two operands are registers, if any of
the operands is in memory, it don't work.
Been there, been burned :p
Later, Juan.
--
In theory, practice and theory are the same, but in practice they
are different -- Larry McVoy
Am Die, 2002-12-10 um 08.24 schrieb Dave Jones:
> Mine disagrees.
My bad, sorry. This conclusion came from a quick disassemble of a small
program I run on those boxes which indeed contain cmovs and I believed
that the boxes execercise the complete program but obviously not.
A quick check with a just written testprogram calculating some primes
revealed that -march=i686 -mcpu=i686 does *not* work...
--
Servus,
Daniel
Am Die, 2002-12-10 um 13.40 schrieb Juan Quintela:
> Have you tested it?
Sort of.... :/
> Here, we got cmov to work if the two operands are registers, if any of
> the operands is in memory, it don't work.
Now *this* is really informative because it explains why my
testapplication which uses
80488c7: 0f 43 d0 cmovae %eax,%edx
doesn't SEGILL.
> Been there, been burned :p
Me too, just this morning.
--
Servus,
Daniel
> Interesting. I have no clue about which C3 you're talking about here but
> a VIA Ezra has all 686 instructions including cmov and thus optimising
> for PPro works best for me.
Well if you optimise for ppro it won't actually always work. Also the
scheduling seems to be best with 486. Remember the C3 is a single issue
risc processor.
Alan
Am Die, 2002-12-10 um 17.51 schrieb Alan Cox:
> Well if you optimise for ppro it won't actually always work.
Yeah, I had to learn earlier that it seems to support certain
kind of cmovs but certainly not all of them and some other
instructions seem also to be missing.
> Also thescheduling seems to be best with 486.
> Remember the C3 is a single issue risc processor.
Do you have pointers to some optimisation manual or whatever?
gcc currently defines the c3 as 486+mmx+3dnow however I doubt
that this model is entirely correct and as such leaves some
space for improvements.
> --
> Servus,
> Daniel
On Tue, Dec 10, 2002 at 08:39:38PM +0100, Daniel Egger wrote:
> Am Die, 2002-12-10 um 17.51 schrieb Alan Cox:
>
> > Well if you optimise for ppro it won't actually always work.
>
> Yeah, I had to learn earlier that it seems to support certain
> kind of cmovs but certainly not all of them and some other
> instructions seem also to be missing.
Yes.
> > Also thescheduling seems to be best with 486.
> > Remember the C3 is a single issue risc processor.
>
> Do you have pointers to some optimisation manual or whatever?
> gcc currently defines the c3 as 486+mmx+3dnow however I doubt
> that this model is entirely correct and as such leaves some
> space for improvements.
Definitely. Read my email message that went along with that commit for
more details ;-) (finding it isn't hard, it's probably one of the few
gcc-patches mails I have ever sent)
On Tue, 2002-12-10 at 19:39, Daniel Egger wrote:
> Do you have pointers to some optimisation manual or whatever?
> gcc currently defines the c3 as 486+mmx+3dnow however I doubt
> that this model is entirely correct and as such leaves some
> space for improvements.
VIA are a little odd at times. A vendor that doesn't publish CPU manuals
and push optimisation data at app writers is -odd- by my standards
anyway. I've been discussing a few things with VIA recently and we'll
see what happens over time.
Alan
On 10 December 2002 05:22, Daniel Egger wrote:
> Am Die, 2002-12-10 um 06.52 schrieb Dave Jones:
> > I believe someone (Jeff Garzik?) benchmarked gcc code generation,
> > and the C3 executed code scheduled for a 486 faster than it did for
> > -m586
> > I'm not sure about the alignment flags. I've been meaning to look
> > into that myself...
>
> Interesting. I have no clue about which C3 you're talking about here
> but a VIA Ezra has all 686 instructions including cmov and thus
> optimising for PPro works best for me.
>
> Prolly I would have to do more benchmarking to find out about
> aligment advantages.
I heard cmovs are microcoded in Centaurs.
s...l...o...w...
--
vda
On Wed, Dec 11, 2002 at 11:19:23AM -0200, Denis Vlasenko wrote:
> > Prolly I would have to do more benchmarking to find out about
> > aligment advantages.
> I heard cmovs are microcoded in Centaurs.
> s...l...o...w...
Hardly surprising given that the chip isn't targetted at the performance
market.
Dave
On 11 December 2002 08:58, Dave Jones wrote:
> On Wed, Dec 11, 2002 at 11:19:23AM -0200, Denis Vlasenko wrote:
> > > Prolly I would have to do more benchmarking to find out about
> > > aligment advantages.
> >
> > I heard cmovs are microcoded in Centaurs.
> > s...l...o...w...
>
> Hardly surprising given that the chip isn't targetted at the
> performance market.
*We Support 686 Instruction Set* plastered everywhere? ;)
Who cares that a single cmov take some tens of cycles...
(btw, can someone measure that? I have no C3...)
On 7 July 2002 12:32, Willy TARREAU wrote:
> because GCC's output is really ugly. In fact, it is
> also ugly when it generates cmov. I disassembled my
> libc and found that it subobtimizes the code at the
> point that it's far worse with cmov than without !
> (more instructions, more memory accesses, more
> registers used).
Do not try to optimize "pedal to the metal" without
actually looking at the results.
With "-march=i686" on C3 one will get:
* Non-optimal GCC code generation
* Really Slow (tm) cmovs
* Buggy code (cmov with mem operands)
if one don't think above two are not enough ;)
On 10 December 2002 05:22, Daniel Egger wrote:
> Am Die, 2002-12-10 um 06.52 schrieb Dave Jones:
> > I believe someone (Jeff Garzik?) benchmarked gcc code generation,
> > and the C3 executed code scheduled for a 486 faster than it did for
> > -m586
> > I'm not sure about the alignment flags. I've been meaning to look
> > into that myself...
>
> Interesting. I have no clue about which C3 you're talking about here
> but a VIA Ezra has all 686 instructions including cmov and thus
> optimising for PPro works best for me.
Such things need testing. A kernel compile would suffice I guess.
--
vda
On Wed, Dec 11, 2002 at 05:09:34PM -0200, Denis Vlasenko wrote:
> > > I heard cmovs are microcoded in Centaurs.
> > > s...l...o...w...
> > Hardly surprising given that the chip isn't targetted at the
> > performance market.
> *We Support 686 Instruction Set* plastered everywhere? ;)
It's an *optional* extension to the 686 as stated in
the Intel documentation.
Dave
--
| Dave Jones. http://www.codemonkey.org.uk
| SuSE Labs
On 10 Dec 2002, Alan Cox wrote:
>
> > Interesting. I have no clue about which C3 you're talking about here but
> > a VIA Ezra has all 686 instructions including cmov and thus optimising
> > for PPro works best for me.
>
> Well if you optimise for ppro it won't actually always work. Also the
> scheduling seems to be best with 486. Remember the C3 is a single issue
> risc processor.
Is this the CPU in the $200 "Lindows" PC Wal-Mart is selling? I was
thinking of one for a low volume router, and it looks as if there are two
VIA chips called C3 (or advertizers have hacked the specs).
--
bill davidsen <[email protected]>
CTO, TMR Associates, Inc
Doing interesting things with little computers since 1979.
On Wed, Dec 11, 2002 at 01:51:13PM -0500, Bill Davidsen wrote:
> Is this the CPU in the $200 "Lindows" PC Wal-Mart is selling?
Yes. Looks like it judging from
http://www.walmart.com/catalog/product_listing.gsp?path=0%3A3944%3A3951%3A41937%3A86796%3A96356&dept=3944&cat=96356&sb=61&bti=0
> I was thinking of one for a low volume router,
Seems to do the job nicely for me.
> and it looks as if there are two
> VIA chips called C3 (or advertizers have hacked the specs).
http://www.viaarena.com/?PageID=15
Dave
--
| Dave Jones. http://www.codemonkey.org.uk
| SuSE Labs
On Wed, Dec 11, 2002 at 01:51:13PM -0500, Bill Davidsen wrote:
> Is this the CPU in the $200 "Lindows" PC Wal-Mart is selling? I was
> thinking of one for a low volume router, and it looks as if there are two
> VIA chips called C3 (or advertizers have hacked the specs).
We don't know for sure; however the cnn.com story on these PCs had a
"Via C3" logo in the story's graphic, so it's strongly probable :)
On Wed, 11 Dec 2002, Jeff Garzik wrote:
> On Wed, Dec 11, 2002 at 01:51:13PM -0500, Bill Davidsen wrote:
> > Is this the CPU in the $200 "Lindows" PC Wal-Mart is selling? I was
> > thinking of one for a low volume router, and it looks as if there are two
> > VIA chips called C3 (or advertizers have hacked the specs).
>
> We don't know for sure; however the cnn.com story on these PCs had a
> "Via C3" logo in the story's graphic, so it's strongly probable :)
http://www.walmart.com/catalog/product.gsp?product_id=2009643&cat=3951&type=19&dept=3944&path=0%3A3944%3A3951
> -
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--
--------------------------------------------------------------------------
Joel Jaeggli Academic User Services [email protected]
-- PGP Key Fingerprint: 1DE9 8FCA 51FB 4195 B42A 9C32 A30D 121E --
In Dr. Johnson's famous dictionary patriotism is defined as the last
resort of the scoundrel. With all due respect to an enlightened but
inferior lexicographer I beg to submit that it is the first.
-- Ambrose Bierce, "The Devil's Dictionary"
On Wed, 2002-12-11 at 18:51, Bill Davidsen wrote:
> Is this the CPU in the $200 "Lindows" PC Wal-Mart is selling? I was
> thinking of one for a low volume router, and it looks as if there are two
> VIA chips called C3 (or advertizers have hacked the specs).
It is. Its a nice CPU for appliances. FPU is nondescript, integer
performance is sort of the same as an equivalently clocked celewrong for
the current Ezra core at least. The older Samuel II core seems a little
slower.
There is also a subspecies that comes in at 500-600MHz and is designed
for low power fanless operation (though with a decent sized heatsink the
same is true for the 1GHz ones).
If you think the Walmart PC is cool take a look at the EPIA board or see
http://www.mini-itx.com. 60W for a complete PC
Thanks for all response. :)
I think I know more why it downgrades.
But one more curious question.
In the file, arch/i386/Makefile, under kernel 2.5.51.
I found the C3 alignments , $(call check_gcc, -march=c3,-march=i486).
Does the C3 CPU type be included in gcc compile option??
I've downloaded the latest gcc 3.2.1 version.
But I don't find the c3 options in the file gcc/config/i396/i386.c, i386.h
or etc.
BR,
Joseph
-----------------------------------------------------------------
< ?C?ѳ? Yahoo!?_?? > http://www.yahoo.com.tw
Alan Cox wrote:
> On Wed, 2002-12-11 at 18:51, Bill Davidsen wrote:
>
>>Is this the CPU in the $200 "Lindows" PC Wal-Mart is selling? I was
>>thinking of one for a low volume router, and it looks as if there are two
>>VIA chips called C3 (or advertizers have hacked the specs).
>
> It is. Its a nice CPU for appliances. FPU is nondescript, integer
> performance is sort of the same as an equivalently clocked celewrong for
> the current Ezra core at least. The older Samuel II core seems a little
> slower.
>
> There is also a subspecies that comes in at 500-600MHz and is designed
> for low power fanless operation (though with a decent sized heatsink the
> same is true for the 1GHz ones).
Although don't try to do this in 1U with 1GHz chips unless you clock
down and reduce the voltage (you need a "fair amount" of free space
above the heatsink to dissipate the heat). Hmm that reminds me I must
complete the auto voltage selection code in cpufreq.
> If you think the Walmart PC is cool take a look at the EPIA board or see
> http://www.mini-itx.com. 60W for a complete PC
I built a "no moving parts" router thingy in 1U that used max 19W.
You get a nice MTBF (5.25 years for our config) when there's nothing
mechanical as well as a good power saving. The main parts were:
PSU: EOS VLT60-3000 (now celetron)
MB: Advantech PCM9576
CPU: Ezra C3 866a
HD: 64MB compact flash
P?draig.
On Thu, Dec 12, 2002 at 05:17:29PM +0800, Joseph wrote:
> Thanks for all response. :)
> I think I know more why it downgrades.
> But one more curious question.
> In the file, arch/i386/Makefile, under kernel 2.5.51.
> I found the C3 alignments , $(call check_gcc, -march=c3,-march=i486).
> Does the C3 CPU type be included in gcc compile option??
> I've downloaded the latest gcc 3.2.1 version.
> But I don't find the c3 options in the file gcc/config/i396/i386.c, i386.h
> or etc.
Not in a currently released gcc. CVS HEAD supports it, as will 3.3
Dave
--
| Dave Jones. http://www.codemonkey.org.uk
>>On Thu, Dec 12, 2002 at 05:17:29PM +0800, Joseph wrote:
>> Thanks for all response. :)
>> I think I know more why it downgrades.
>> But one more curious question.
>> In the file, arch/i386/Makefile, under kernel 2.5.51.
>> I found the C3 alignments , $(call check_gcc, -march=c3,-march=i486).
>> Does the C3 CPU type be included in gcc compile option??
>> I've downloaded the latest gcc 3.2.1 version.
>> But I don't find the c3 options in the file gcc/config/i396/i386.c,
i386.h
>> or etc.
>Not in a currently released gcc. CVS HEAD supports it, as will 3.3
>Dave
I've checked the gcc CVS. But it seems to use i486 pluse MMX and 3DNOW
instructions.
* config.gcc: Treat winchip_c6-*|winchip2-*|c3-* as pentium-mmx.
* config/i386/i386.c (processor_alias_table): Add winchip-c6, winchip2 and
c3.
* doc/invoke.texi: Mention new aliases.
** {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW}, **
Is there any plan to optimize for C3 CPU in future gcc released version?
BR,
Joseph
-----------------------------------------------------------------
< ?C?ѳ? Yahoo!?_?? > http://www.yahoo.com.tw
Am Fre, 2002-12-13 um 07.55 schrieb Joseph:
> Is there any plan to optimize for C3 CPU in future gcc released version?
Certainly, as soon as some reliable (optimisation-) manual shows up.
Whether that will happen before you fixed your mailer is a different
question though.... :)
> --
> Servus,
> Daniel
On Fri, Dec 13, 2002 at 02:55:04PM +0800, Joseph wrote:
> I've checked the gcc CVS. But it seems to use i486 pluse MMX and 3DNOW
> instructions.
> * config.gcc: Treat winchip_c6-*|winchip2-*|c3-* as pentium-mmx.
> * config/i386/i386.c (processor_alias_table): Add winchip-c6, winchip2 and
> c3.
> * doc/invoke.texi: Mention new aliases.
> ** {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW}, **
> Is there any plan to optimize for C3 CPU in future gcc released version?
Maybe if an optimisation guide appears for the C3.
Dave
--
| Dave Jones. http://www.codemonkey.org.uk
Hi!
> > > I believe someone (Jeff Garzik?) benchmarked gcc code generation,
> > > and the C3 executed code scheduled for a 486 faster than it did for
> > > -m586
> > > I'm not sure about the alignment flags. I've been meaning to look
> > > into that myself...
> >
> > Interesting. I have no clue about which C3 you're talking about here
> > but a VIA Ezra has all 686 instructions including cmov and thus
> > optimising for PPro works best for me.
> >
> > Prolly I would have to do more benchmarking to find out about
> > aligment advantages.
>
> I heard cmovs are microcoded in Centaurs.
>
> s...l...o...w...
It still might be faster then a branch... or not if centaurs are
really that simple.
Pavel
--
Worst form of spam? Adding advertisment signatures ala sourceforge.net.
What goes next? Inserting advertisment *into* email?
On 12 December 2002 18:09, Pavel Machek wrote:
> Hi!
>
> > > > I believe someone (Jeff Garzik?) benchmarked gcc code
> > > > generation, and the C3 executed code scheduled for a 486 faster
> > > > than it did for -m586
> > > > I'm not sure about the alignment flags. I've been meaning to
> > > > look into that myself...
> > >
> > > Interesting. I have no clue about which C3 you're talking about
> > > here but a VIA Ezra has all 686 instructions including cmov and
> > > thus optimising for PPro works best for me.
> > >
> > > Prolly I would have to do more benchmarking to find out about
> > > aligment advantages.
> >
> > I heard cmovs are microcoded in Centaurs.
> >
> > s...l...o...w...
>
> It still might be faster then a branch... or not if centaurs are
> really that simple.
> Pavel
I did not measure it myself, but rumors were they took tens of cycles.
Well, a IFcc prefix meaning 'execute next instruction if' would be
way more cool that CMOVcc. Because I want CADDcc, CTESTcc, CBSWAPcc too ;)
But since all 1 byte opcodes are taken and
Jcc skip # <- 2 byte opcode
opcode op1,op2
skip:
I think some CPU magic can detect such short jumps and handle'em just like
they were such a prefix, saving potential branch (mis-)prediction.
--
vda