Hi,
On the Core2 cpus, the rdtsc instruction is not serializing (as defined
in the architecture reference since rdtsc exists) and due to the deep
speculation of these cores, it's possible that you can observe time go
backwards between cores due to this speculation. Since the kernel
already deals with this with the SYNC_RDTSC flag, the solution is
simple, only assume that the instruction is serializing on family 15...
The price one pays for this is a slightly slower gettimeofday (by a
dozen or two cycles), but that increase is quite small to pay for a
really-going-forward tsc counter.
Signed-off-by: Arjan van de Ven <[email protected]>
--- linux-2.6.18/arch/x86_64/kernel/setup.c.org 2006-11-28 11:22:08.000000000 +0100
+++ linux-2.6.18/arch/x86_64/kernel/setup.c 2006-11-28 11:22:50.000000000 +0100
@@ -854,7 +854,10 @@ static void __cpuinit init_intel(struct
set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
if (c->x86 == 6)
set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
- set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
+ if (c->x86 == 15)
+ set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
+ else
+ clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
c->x86_max_cores = intel_num_cpu_cores(c);
srat_detect_node();
On Tuesday 28 November 2006 11:28, Arjan van de Ven wrote:
> Hi,
>
> On the Core2 cpus, the rdtsc instruction is not serializing (as defined
> in the architecture reference since rdtsc exists) and due to the deep
> speculation of these cores, it's possible that you can observe time go
> backwards between cores due to this speculation. Since the kernel
> already deals with this with the SYNC_RDTSC flag, the solution is
> simple, only assume that the instruction is serializing on family 15...
>
> The price one pays for this is a slightly slower gettimeofday (by a
> dozen or two cycles), but that increase is quite small to pay for a
> really-going-forward tsc counter.
Added thanks
-Andi
Zhang, Yanmin wrote:
> If it's a single processor, the go backwards issue doesn't exist. Below is
> my patch based on Arjan's. It's against 2.6.19-rc5-mm2.
Hi,
this patch is incorrect
> --- linux-2.6.19-rc5-mm2_arjan/arch/x86_64/kernel/setup.c 2006-11-29 10:41:21.000000000 +0800
> +++ linux-2.6.19-rc5-mm2_arjan_fix/arch/x86_64/kernel/setup.c 2006-11-29 10:42:28.000000000 +0800
> @@ -861,7 +861,7 @@ static void __cpuinit init_intel(struct
> set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
> if (c->x86 == 6)
> set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
> - if (c->x86 == 15)
> + if (c->x86 == 15 && num_possible_cpus() != 1)
> set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
first of all, you probably meant "|| num_possible_cpus() == 1"
but second of all, the core2 cpus are dual core so.. .what does it
bring you at all?
Arjan van de Ven wrote:
> Zhang, Yanmin wrote:
>
>> If it's a single processor, the go backwards issue doesn't exist.
>> Below is
>> my patch based on Arjan's. It's against 2.6.19-rc5-mm2.
>
> Hi,
>
> this patch is incorrect
>
>> --- linux-2.6.19-rc5-mm2_arjan/arch/x86_64/kernel/setup.c
>> 2006-11-29 10:41:21.000000000 +0800
>> +++ linux-2.6.19-rc5-mm2_arjan_fix/arch/x86_64/kernel/setup.c
>> 2006-11-29 10:42:28.000000000 +0800
>> @@ -861,7 +861,7 @@ static void __cpuinit init_intel(struct
>> set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
>> if (c->x86 == 6)
>> set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
>> - if (c->x86 == 15)
>> + if (c->x86 == 15 && num_possible_cpus() != 1)
>> set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
>
>
> first of all, you probably meant "|| num_possible_cpus() == 1"
>
> but second of all, the core2 cpus are dual core so.. .what does it bring
> you at all?
I guess you could boot with a UP kernel or maxcpus=1?
--
SUSE Labs, Novell Inc.
Send instant messages to your online friends http://au.messenger.yahoo.com
Zhang, Yanmin wrote:
>> but second of all, the core2 cpus are dual core so.. .what does it
>> bring you at all?
>
> When there is only one cpu (or UP), the go backwards issue doesn't exist,
it does exist for single-socket dual core already. And core2 is dual
core...
> so
> don't use cpuid here for UP. Another function init_amd already does so.
>
not anymore.. that got fixed very recently...
(but you are right; on AMD the speculation is even bigger so there
even on single core you need cpuid)
On Wed, 2006-11-29 at 19:05 +1100, Nick Piggin wrote:
> Arjan van de Ven wrote:
> > Zhang, Yanmin wrote:
> >
> >> If it's a single processor, the go backwards issue doesn't exist.
> >> Below is
> >> my patch based on Arjan's. It's against 2.6.19-rc5-mm2.
> >
> > Hi,
> >
> > this patch is incorrect
> >
> >> --- linux-2.6.19-rc5-mm2_arjan/arch/x86_64/kernel/setup.c
> >> 2006-11-29 10:41:21.000000000 +0800
> >> +++ linux-2.6.19-rc5-mm2_arjan_fix/arch/x86_64/kernel/setup.c
> >> 2006-11-29 10:42:28.000000000 +0800
> >> @@ -861,7 +861,7 @@ static void __cpuinit init_intel(struct
> >> set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
> >> if (c->x86 == 6)
> >> set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
> >> - if (c->x86 == 15)
> >> + if (c->x86 == 15 && num_possible_cpus() != 1)
> >> set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
> >
> >
> > first of all, you probably meant "|| num_possible_cpus() == 1"
> >
> > but second of all, the core2 cpus are dual core so.. .what does it bring
> > you at all?
>
> I guess you could boot with a UP kernel or maxcpus=1?
Yes, with the new patch. My reply email to Arjan was lost in LKML because
my email client was crazy to set the email as HTML format.
>
On Wed, 2006-11-29 at 09:35 +0100, Arjan van de Ven wrote:
> Zhang, Yanmin wrote:
> >> but second of all, the core2 cpus are dual core so.. .what does it
> >> bring you at all?
> >
> > When there is only one cpu (or UP), the go backwards issue doesn't exist,
>
> it does exist for single-socket dual core already. And core2 is dual
> core...
>
> > so
> > don't use cpuid here for UP. Another function init_amd already does so.
> >
> not anymore.. that got fixed very recently...
Thanks.
> (but you are right; on AMD the speculation is even bigger so there
> even on single core you need cpuid)