This is the version3 patch. It delete platform.h and delete some code in platsmp.c that's not necessary. The patchs add smp support for Allwinner A20. It add cpu register node and arch timer node in dts for smp booting. SMP need arch timer as clocksource, It does use virtual counter timer and does not use physical counter timer, so bootloader ***must*** set CNTVOFF register for a20 before kernel booting. I have add support set CNTVOFF register for uboot, if you want to test it in a20 board, you need update uboot. Thanks for advice of Mark Rutland, Marc Zyngier, Ian Campbell, Russell King and Maxime Ripard.
Fan Rong (3):
Add smp support for Allwinner A20(sunxi 7i).
Add cpuconfig nodes in dts for smp configure.
add arch count timer node in dts for Allwinner A20(sunxi 7i).
arch/arm/boot/dts/sun7i-a20.dtsi | 19 ++++++++-
arch/arm/mach-sunxi/Makefile | 2 +
arch/arm/mach-sunxi/headsmp.S | 17 ++++++++
arch/arm/mach-sunxi/platsmp.c | 86 ++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-sunxi/sunxi.c | 31 +++++++++++++++
5 files changed, 153 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/mach-sunxi/headsmp.S
create mode 100644 arch/arm/mach-sunxi/platsmp.c
--
1.8.1.2
Signed-off-by: Fan Rong <[email protected]>
---
arch/arm/mach-sunxi/Makefile | 2 +
arch/arm/mach-sunxi/headsmp.S | 17 +++++++++
arch/arm/mach-sunxi/platsmp.c | 86 +++++++++++++++++++++++++++++++++++++++++++
arch/arm/mach-sunxi/sunxi.c | 31 ++++++++++++++++
4 files changed, 136 insertions(+)
create mode 100644 arch/arm/mach-sunxi/headsmp.S
create mode 100644 arch/arm/mach-sunxi/platsmp.c
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 93bebfc..d7f1ef4 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -1 +1,3 @@
obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
+obj-$(CONFIG_ARCH_SUNXI) += platsmp.o
+obj-$(CONFIG_ARCH_SUNXI) += headsmp.o
diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
new file mode 100644
index 0000000..5899399
--- /dev/null
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -0,0 +1,17 @@
+/*
+ * SMP support for A20
+ *
+ * Copyright (C) 2013 Fan Rong <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+.section ".text.head", "ax" ENTRY(sun7i_secondary_startup)
+msr cpsr_fsxc,
+#0xd3
+b secondary_startup ENDPROC(sun7i_secondary_startup)
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
new file mode 100644
index 0000000..5e3e994
--- /dev/null
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -0,0 +1,86 @@
+/*
+ * linux/arch/arm/mach-sun7i/platsmp.c
+ *
+ * Copyright (C) 2013 Fan Rong <[email protected]>
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/smp.h>
+
+extern void __iomem *sunxi7i_cc_base;
+void sun7i_secondary_startup(void);
+
+/*
+ * CPUCFG
+ */
+#define SUN7I_CPUCFG_BOOTADDR 0x01a4
+
+#define SUN7I_CPUCFG_GENCTL 0x0184
+#define SUN7I_CPUCFG_DBGCTL0 0x01e0
+#define SUN7I_CPUCFG_DBGCTL1 0x01e4
+
+#define SUN7I_CPU1_PWR_CLAMP 0x01b0
+#define SUN7I_CPU1_PWROFF_REG 0x01b4
+#define SUN7I_CPUX_RESET_CTL(x) (0x40 + (x)*0x40)
+
+static int sun7i_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ long paddr;
+ uint32_t pwr_reg;
+ uint32_t j = 0xff << 1;
+ if (!sunxi7i_cc_base) {
+ pr_debug("error map cpu configure\n");
+ return -ENOSYS;
+ }
+ /* Set boot addr */
+ paddr = virt_to_phys(sun7i_secondary_startup);
+ writel(paddr, sunxi7i_cc_base + SUN7I_CPUCFG_BOOTADDR);
+
+ /* Assert cpu core reset */
+ writel(0, sunxi7i_cc_base + SUN7I_CPUX_RESET_CTL(cpu));
+
+ /* Ensure CPU reset also invalidates L1 caches */
+ pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPUCFG_GENCTL);
+ pwr_reg &= ~ BIT(cpu);
+ writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPUCFG_GENCTL);
+
+ /* DBGPWRDUP hold low */
+ pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
+ pwr_reg &= ~ BIT(cpu);
+ writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
+
+ /* Ramp up power to CPU1 */
+ do {
+ writel(j, sunxi7i_cc_base + SUN7I_CPU1_PWR_CLAMP);
+ j = j >> 1;
+ } while (j != 0);
+
+ mdelay(10);
+
+ pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPU1_PWROFF_REG);
+ pwr_reg &= ~1;
+ writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPU1_PWROFF_REG);
+ mdelay(1);
+
+ /* Release CPU reset */
+ writel(3, sunxi7i_cc_base + SUN7I_CPUX_RESET_CTL(cpu));
+
+ /* Unlock CPU */
+ pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
+ pwr_reg |= BIT(cpu);
+ writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
+
+ return 0;
+}
+
+struct smp_operations sun7i_smp_ops __initdata = {
+ .smp_boot_secondary = sun7i_boot_secondary,
+};
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index e79fb34..a692350 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -26,6 +26,8 @@
#include <asm/mach/map.h>
#include <asm/system_misc.h>
+extern struct smp_operations sun7i_smp_ops;
+
#define SUN4I_WATCHDOG_CTRL_REG 0x00
#define SUN4I_WATCHDOG_CTRL_RESTART BIT(0)
#define SUN4I_WATCHDOG_MODE_REG 0x04
@@ -42,6 +44,14 @@
#define SUN6I_WATCHDOG1_MODE_ENABLE BIT(0)
static void __iomem *wdt_base;
+/*
+ * CPU Configure module support
+ * 1: Software reset for smp cpus
+ * 2: Configure for smp cpus including boot.
+ * 3: Three 64-bit idle counters and two 64-bit common counters
+ * it is needed for smp cpus
+ */
+void __iomem *sunxi7i_cc_base; /*CPU Configure Base*/
static void sun4i_restart(enum reboot_mode mode, const char *cmd)
{
@@ -98,6 +108,11 @@ static struct of_device_id sunxi_restart_ids[] = {
{ /*sentinel*/ }
};
+static struct of_device_id sunxi_cc_ids[] = {
+ { .compatible = "allwinner,sun7i-a20-cpuconfig"},
+ { /*sentinel*/ }
+};
+
static void sunxi_setup_restart(void)
{
const struct of_device_id *of_id;
@@ -138,7 +153,23 @@ static const char * const sunxi_board_dt_compat[] = {
NULL,
};
+static int __init sunxi_init_cpuconfig_map(void)
+{
+ struct device_node *np;
+
+ np = of_find_matching_node(NULL, sunxi_cc_ids);
+ if (WARN(!np, "unable to setup cup configure"))
+ return -ENOSYS;
+ sunxi7i_cc_base = of_iomap(np, 0);
+ if (WARN(!sunxi7i_cc_base, "failed to map cup configure base address"))
+ return -ENOSYS;
+ return 0;
+}
+
+early_initcall(sunxi_init_cpuconfig_map);
+
DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
+ .smp = smp_ops(sun7i_smp_ops),
.init_machine = sunxi_dt_init,
.init_time = sunxi_timer_init,
.dt_compat = sunxi_board_dt_compat,
--
1.8.1.2
Signed-off-by: Fan Rong <[email protected]>
---
arch/arm/boot/dts/sun7i-a20.dtsi | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 999ff45..f745e0b 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -20,13 +20,13 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
@@ -167,6 +167,11 @@
#size-cells = <1>;
ranges;
+ cpuconfig: cpuconfig@01c25c00 {
+ compatible = "allwinner,sun7i-a20-cpuconfig";
+ reg = <0x01c25c00 0x400>;
+ };
+
pio: pinctrl@01c20800 {
compatible = "allwinner,sun7i-a20-pinctrl";
reg = <0x01c20800 0x400>;
--
1.8.1.2
Signed-off-by: Fan Rong <[email protected]>
---
arch/arm/boot/dts/sun7i-a20.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index f745e0b..76b8c3f 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -312,5 +312,15 @@
#interrupt-cells = <3>;
interrupts = <1 9 0xf04>;
};
+
+ timer {
+ compatible ="arm,armv7-timer";
+ interrupts = <1 13 0x308>,
+ <1 14 0x308>,
+ <1 11 0x308>,
+ <1 10 0x308>;
+ clock-frequency = <24000000>;
+ };
+
};
};
--
1.8.1.2
On Sun, Sep 22, 2013 at 08:21:26PM +0800, Fan Rong wrote:
> +.section ".text.head", "ax" ENTRY(sun7i_secondary_startup)
> +msr cpsr_fsxc,
> +#0xd3
> +b secondary_startup ENDPROC(sun7i_secondary_startup)
This looks like it's been messed up somehow.
Yes, I get it, it is cause by using ./scripts/Lindent. I have to
remail patch aggin. :)
On 22 September 2013 21:00, Russell King - ARM Linux
<[email protected]> wrote:
> On Sun, Sep 22, 2013 at 08:21:26PM +0800, Fan Rong wrote:
>> +.section ".text.head", "ax" ENTRY(sun7i_secondary_startup)
>> +msr cpsr_fsxc,
>> +#0xd3
>> +b secondary_startup ENDPROC(sun7i_secondary_startup)
>
> This looks like it's been messed up somehow.
>
On Sun, 2013-09-22 at 20:21 +0800, Fan Rong wrote:
> + /* Set boot addr */
> + paddr = virt_to_phys(sun7i_secondary_startup);
> + writel(paddr, sunxi7i_cc_base + SUN7I_CPUCFG_BOOTADDR);
This means that the secondary cores will miss out on any setup which the
bootloader might have done for the primary CPU, e.g. switching to NS HYP
mode, setting the CNTFRQ etc.
Wouldn't it be better to do all this stuff in the bootloader and either
implement PSCI or have the bootloader do the traditional holding pen and
mbox address thing?
Hi Fan,
On Sun, Sep 22, 2013 at 08:21:27PM +0800, Fan Rong wrote:
> Signed-off-by: Fan Rong <[email protected]>
> ---
> arch/arm/boot/dts/sun7i-a20.dtsi | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
> index 999ff45..f745e0b 100644
> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
> @@ -20,13 +20,13 @@
> #address-cells = <1>;
> #size-cells = <0>;
>
> - cpu@0 {
> + cpu0: cpu@0 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> reg = <0>;
> };
>
> - cpu@1 {
> + cpu1: cpu@1 {
You still haven't replied on why you need these two changes.
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
Hi Fang,
On Sun, Sep 22, 2013 at 08:21:28PM +0800, Fan Rong wrote:
> Signed-off-by: Fan Rong <[email protected]>
Please be more verbose here, especially on the consequences it has.
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
Hi Fang,
On Sun, Sep 22, 2013 at 08:21:26PM +0800, Fan Rong wrote:
> Signed-off-by: Fan Rong <[email protected]>
> ---
> arch/arm/mach-sunxi/Makefile | 2 +
> arch/arm/mach-sunxi/headsmp.S | 17 +++++++++
> arch/arm/mach-sunxi/platsmp.c | 86 +++++++++++++++++++++++++++++++++++++++++++
> arch/arm/mach-sunxi/sunxi.c | 31 ++++++++++++++++
> 4 files changed, 136 insertions(+)
> create mode 100644 arch/arm/mach-sunxi/headsmp.S
> create mode 100644 arch/arm/mach-sunxi/platsmp.c
>
> diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
> index 93bebfc..d7f1ef4 100644
> --- a/arch/arm/mach-sunxi/Makefile
> +++ b/arch/arm/mach-sunxi/Makefile
> @@ -1 +1,3 @@
> obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
> +obj-$(CONFIG_ARCH_SUNXI) += platsmp.o
> +obj-$(CONFIG_ARCH_SUNXI) += headsmp.o
> diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
> new file mode 100644
> index 0000000..5899399
> --- /dev/null
> +++ b/arch/arm/mach-sunxi/headsmp.S
> @@ -0,0 +1,17 @@
> +/*
> + * SMP support for A20
> + *
> + * Copyright (C) 2013 Fan Rong <[email protected]>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/linkage.h>
> +#include <linux/init.h>
> +
> +.section ".text.head", "ax" ENTRY(sun7i_secondary_startup)
> +msr cpsr_fsxc,
> +#0xd3
> +b secondary_startup ENDPROC(sun7i_secondary_startup)
> diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
> new file mode 100644
> index 0000000..5e3e994
> --- /dev/null
> +++ b/arch/arm/mach-sunxi/platsmp.c
> @@ -0,0 +1,86 @@
> +/*
> + * linux/arch/arm/mach-sun7i/platsmp.c
> + *
> + * Copyright (C) 2013 Fan Rong <[email protected]>
> + * All Rights Reserved
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +#include <linux/init.h>
> +#include <linux/errno.h>
> +#include <linux/smp.h>
> +#include <linux/io.h>
> +#include <linux/delay.h>
> +#include <linux/smp.h>
> +
> +extern void __iomem *sunxi7i_cc_base;
Please use sun7i here as well.
> +void sun7i_secondary_startup(void);
> +
> +/*
> + * CPUCFG
> + */
> +#define SUN7I_CPUCFG_BOOTADDR 0x01a4
> +
> +#define SUN7I_CPUCFG_GENCTL 0x0184
> +#define SUN7I_CPUCFG_DBGCTL0 0x01e0
> +#define SUN7I_CPUCFG_DBGCTL1 0x01e4
> +
> +#define SUN7I_CPU1_PWR_CLAMP 0x01b0
> +#define SUN7I_CPU1_PWROFF_REG 0x01b4
> +#define SUN7I_CPUX_RESET_CTL(x) (0x40 + (x)*0x40)
> +
> +static int sun7i_boot_secondary(unsigned int cpu, struct task_struct *idle)
> +{
> + long paddr;
> + uint32_t pwr_reg;
> + uint32_t j = 0xff << 1;
> + if (!sunxi7i_cc_base) {
> + pr_debug("error map cpu configure\n");
> + return -ENOSYS;
> + }
> + /* Set boot addr */
> + paddr = virt_to_phys(sun7i_secondary_startup);
> + writel(paddr, sunxi7i_cc_base + SUN7I_CPUCFG_BOOTADDR);
> +
> + /* Assert cpu core reset */
> + writel(0, sunxi7i_cc_base + SUN7I_CPUX_RESET_CTL(cpu));
> +
> + /* Ensure CPU reset also invalidates L1 caches */
> + pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPUCFG_GENCTL);
> + pwr_reg &= ~ BIT(cpu);
> + writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPUCFG_GENCTL);
> +
> + /* DBGPWRDUP hold low */
> + pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
> + pwr_reg &= ~ BIT(cpu);
> + writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
> +
> + /* Ramp up power to CPU1 */
> + do {
> + writel(j, sunxi7i_cc_base + SUN7I_CPU1_PWR_CLAMP);
> + j = j >> 1;
> + } while (j != 0);
> +
> + mdelay(10);
> +
> + pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPU1_PWROFF_REG);
> + pwr_reg &= ~1;
> + writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPU1_PWROFF_REG);
> + mdelay(1);
> +
> + /* Release CPU reset */
> + writel(3, sunxi7i_cc_base + SUN7I_CPUX_RESET_CTL(cpu));
> +
> + /* Unlock CPU */
> + pwr_reg = readl(sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
> + pwr_reg |= BIT(cpu);
> + writel(pwr_reg, sunxi7i_cc_base + SUN7I_CPUCFG_DBGCTL1);
> +
> + return 0;
> +}
> +
> +struct smp_operations sun7i_smp_ops __initdata = {
> + .smp_boot_secondary = sun7i_boot_secondary,
> +};
> diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
> index e79fb34..a692350 100644
> --- a/arch/arm/mach-sunxi/sunxi.c
> +++ b/arch/arm/mach-sunxi/sunxi.c
> @@ -26,6 +26,8 @@
> #include <asm/mach/map.h>
> #include <asm/system_misc.h>
>
> +extern struct smp_operations sun7i_smp_ops;
> +
> #define SUN4I_WATCHDOG_CTRL_REG 0x00
> #define SUN4I_WATCHDOG_CTRL_RESTART BIT(0)
> #define SUN4I_WATCHDOG_MODE_REG 0x04
> @@ -42,6 +44,14 @@
> #define SUN6I_WATCHDOG1_MODE_ENABLE BIT(0)
>
> static void __iomem *wdt_base;
> +/*
> + * CPU Configure module support
> + * 1: Software reset for smp cpus
> + * 2: Configure for smp cpus including boot.
> + * 3: Three 64-bit idle counters and two 64-bit common counters
> + * it is needed for smp cpus
> + */
> +void __iomem *sunxi7i_cc_base; /*CPU Configure Base*/
>
> static void sun4i_restart(enum reboot_mode mode, const char *cmd)
> {
> @@ -98,6 +108,11 @@ static struct of_device_id sunxi_restart_ids[] = {
> { /*sentinel*/ }
> };
>
> +static struct of_device_id sunxi_cc_ids[] = {
> + { .compatible = "allwinner,sun7i-a20-cpuconfig"},
> + { /*sentinel*/ }
> +};
> +
> static void sunxi_setup_restart(void)
> {
> const struct of_device_id *of_id;
> @@ -138,7 +153,23 @@ static const char * const sunxi_board_dt_compat[] = {
> NULL,
> };
>
> +static int __init sunxi_init_cpuconfig_map(void)
> +{
> + struct device_node *np;
> +
> + np = of_find_matching_node(NULL, sunxi_cc_ids);
> + if (WARN(!np, "unable to setup cup configure"))
> + return -ENOSYS;
> + sunxi7i_cc_base = of_iomap(np, 0);
> + if (WARN(!sunxi7i_cc_base, "failed to map cup configure base address"))
> + return -ENOSYS;
> + return 0;
> +}
> +
> +early_initcall(sunxi_init_cpuconfig_map);
You still haven't said why you don't want to use smp_init_cpus there.
> +
> DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
> + .smp = smp_ops(sun7i_smp_ops),
Please align the "=" with the rest of the structure, and please rebase
on top of my "ARM: sunxi: Split out the DT machines for sun6i and sun7i"
patch.
Thanks a lot,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
>
> Please use sun7i here as well.
>
Ok, it will be modified by next patch.
>> +early_initcall(sunxi_init_cpuconfig_map);
>
> You still haven't said why you don't want to use smp_init_cpus there.
I find that of_funcation liking of_find_matching_node and of_iomap can
not run well in smp_init_cpus. It cause kernel crash. So I have to use
early_initcall.
Fan
Hi Fan,
On Wed, Sep 25, 2013 at 12:22:44AM +0800, cinifr wrote:
> > You still haven't said why you don't want to use smp_init_cpus there.
> I find that of_funcation liking of_find_matching_node and of_iomap can
> not run well in smp_init_cpus. It cause kernel crash. So I have to use
> early_initcall.
Ah, right.
Then, can't we use smp_prepare_cpus for this? it looks to be late enough
so that we can use ioremap there.
I don't want it to be an initcall. The code will be different on the
A31, and we don't want it to be run on all the other machines whenever
we boot a multiplatform kernel anyway.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
Hi Maxime,
I have test it, but I found it does not work. If using
smp_prepare_cpus, the kernenl cannot find the secondary cpus because
that smp_prepare_cpus semms not be excuted before kernel is booting
secondary cpus. So I have to use early_initcall.
Fan.
On 26 September 2013 02:44, Maxime Ripard
<[email protected]> wrote:
> Hi Fan,
>
> On Wed, Sep 25, 2013 at 12:22:44AM +0800, cinifr wrote:
>> > You still haven't said why you don't want to use smp_init_cpus there.
>> I find that of_funcation liking of_find_matching_node and of_iomap can
>> not run well in smp_init_cpus. It cause kernel crash. So I have to use
>> early_initcall.
>
> Ah, right.
>
> Then, can't we use smp_prepare_cpus for this? it looks to be late enough
> so that we can use ioremap there.
>
> I don't want it to be an initcall. The code will be different on the
> A31, and we don't want it to be run on all the other machines whenever
> we boot a multiplatform kernel anyway.
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com
Hi Fan,
On Sat, Sep 28, 2013 at 09:48:11PM +0800, cinifr wrote:
> Hi Maxime,
> I have test it, but I found it does not work. If using
> smp_prepare_cpus, the kernenl cannot find the secondary cpus because
> that smp_prepare_cpus semms not be excuted before kernel is booting
> secondary cpus. So I have to use early_initcall.
At least two other platforms (sti and rockchip) do it like that.
And an early_initcall is not an option.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
On Sat, Sep 28, 2013 at 09:48:11PM +0800, cinifr wrote:
> Hi Maxime,
> I have test it, but I found it does not work. If using
> smp_prepare_cpus, the kernenl cannot find the secondary cpus because
> that smp_prepare_cpus semms not be excuted before kernel is booting
> secondary cpus. So I have to use early_initcall.
Please don't do this - you're hacking around what could be a real problem.
Instead, please investigate what is going on and why your smp_prepare_cpus()
function never gets called.
Quite honestly, whenever I see crap like the above, it just makes me want
to tell the ARM-SoC people to forever /dev/null your emails because you
really don't know how to deal with the Linux kernel.
Always *fully* investigate a problem that you find to determine whether
it's your problem or some as yet undiscovered kernel bug. Never hack
around it and then submit a patch suggesting that your workaround is
something that "has" to be done.