In this fifth revision the patchset moves away from the idea
including ARMv7-M platforms into ARCH_MULTIPLATFORM, but
instead adds a new top-level config symbol ARM_SINGLE_ARMV7M
Patch 7 adds this new config symbol while patch 8 alters the
existing ARMv7-M platform ARCH_EFM32 to use ARM_SINGLE_ARMV7M.
I chose to move the config symbol of the ARMv7-M specific
architectures (ARCH_EFM32 at that point) below the multiarch
includes. I think it is a good idea to keep them together, but
I'm not sure if this is an appropriate place. The architecture
which Vybrid is depending on, ARCH_MXC, is not also selectable
when ARM_SINGLE_ARMV7M is selected.
Since v3, this patchset does not contain the interrupt router
driver anymore (MSCM IR). The driver has been merged inbetween:
https://lkml.org/lkml/2015/3/8/6
This patchset extends the NVIC driver to support irq domain
hierarchy and the MSCM IR driver to support NVIC as a parent
irq controller.
The patchset has proven to be working on the Cortex-M4 of the
Vybrid SoC using a Colibri VF61 module.
Note: This patchset has dependencies on "ARM: ARMv7-M: Enlarge
vector table up to 256 entries" (Maxime Coquelin) and the
"irqchip: vf610-mscm: add MSCM interrupt router driver" patch-
set (lined up for next in Jason Cooper's irqchip git tree).
Changes since v4:
- Added ARM_SINGLE_ARMV7M as top-level config symbol for ARMv7-M
architectures
- Cleaned up unnecessary selects within SOC_VF610
- Added linux,stdout-path to device tree
Changes since v3:
- Added dependency IRQ_DOMAIN_HIERARCHY for ARM_NVIC
- Fix MSCM IR disable function check
- Remove "ARM: imx: depend MXC debug board on 3DS machines",
the patch has been merged
Changes since v2:
- Update MSCM patches to merged version of MSCM interrupt router
- Use the GPLv2/X11 dual license in the new device tree files
- Drop SD controller in device tree (initramfs works now and is
probably more appropriate for most cases)
- Disable GPIO nodes since the A5 is using them
- Drop CONFIG_ prefixes in Kconfig changes for MXC_DEBUG_BOARD
- Drop vector table resizing in favor of Maxime Coquelin's patch
(https://lkml.org/lkml/2015/2/20/399)
- Remove !MMU dependency for ARCH_EFM32 since its part of
ARCH_MULTI_V7M
- Rebased on v4.0-rc1
Changes since v1:
- Remove MSCM driver
- Support irq domain hierarchy with NVIC irq controller
- Extend MSCM interrupt router with NVIC as parent in the irq
domain hierarchy
- Rebased on v3.19-rc1 with MSCM driver
- NVIC: Register only the amount of IRQ's which vectors are
available for
Changes since RFC:
- Unified addruart calls for MMU/!MMU
- Add MSCM support along with routable IRQ support in NVIC
- Rebased on Shawns for-next tree which made some changes
obsolete (mainly the Vybrid SoC device tree files in for-next
are already prepared for Cortex-M4 support)
- Removed SRC_GPR3 hack, this is now part of a mini boot-loader:
https://github.com/falstaff84/vf610m4bootldr
*** SUBJECT HERE ***
*** BLURB HERE ***
Stefan Agner (11):
genirq: generic chip: support hierarchy domain
irqchip: nvic: support hierarchy irq domain
irqchip: vf610-mscm: support NVIC parent
ARM: ARMv7M: define size of vector table for Vybrid
clocksource: add dependencies for Vybrid pit clocksource
ARM: unify MMU/!MMU addruart calls
ARM: introduce ARM_SINGLE_ARMV7M for ARMv7-M platforms
ARM: efm32: use ARM_SINGLE_ARMV7M
ARM: vf610: enable Cortex-M4 configuration on Vybrid SoC
ARM: dts: add support for Vybrid running on Cortex-M4
ARM: vf610m4: add defconfig for Linux on Vybrids Cortex-M4
Documentation/devicetree/bindings/arm/fsl.txt | 3 +
arch/arm/Kconfig | 41 ++++++-----
arch/arm/Kconfig.debug | 2 +-
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/vf610m4-colibri.dts | 99 +++++++++++++++++++++++++++
arch/arm/boot/dts/vf610m4.dtsi | 50 ++++++++++++++
arch/arm/configs/efm32_defconfig | 1 +
arch/arm/configs/vf610m4_defconfig | 42 ++++++++++++
arch/arm/include/debug/efm32.S | 2 +-
arch/arm/kernel/debug.S | 2 +-
arch/arm/mach-imx/Kconfig | 38 ++++++----
arch/arm/mach-imx/Makefile.boot | 0
arch/arm/mach-imx/mach-vf610.c | 1 +
arch/arm/mm/Kconfig | 1 +
drivers/clocksource/Kconfig | 2 +
drivers/irqchip/Kconfig | 1 +
drivers/irqchip/irq-nvic.c | 28 +++++++-
drivers/irqchip/irq-vf610-mscm-ir.c | 32 +++++++--
kernel/irq/generic-chip.c | 5 +-
19 files changed, 305 insertions(+), 46 deletions(-)
create mode 100644 arch/arm/boot/dts/vf610m4-colibri.dts
create mode 100644 arch/arm/boot/dts/vf610m4.dtsi
create mode 100644 arch/arm/configs/vf610m4_defconfig
create mode 100644 arch/arm/mach-imx/Makefile.boot
--
2.3.5
Use the new helper function irq_domain_set_info to make sure the
function irq_domain_set_hwirq_and_chip is being called, which is
crucial to save irqdomain specific data to irq_data.
Signed-off-by: Stefan Agner <[email protected]>
---
kernel/irq/generic-chip.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c
index 61024e8..15b370d 100644
--- a/kernel/irq/generic-chip.c
+++ b/kernel/irq/generic-chip.c
@@ -360,7 +360,7 @@ static struct lock_class_key irq_nested_lock_class;
int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
irq_hw_number_t hw_irq)
{
- struct irq_data *data = irq_get_irq_data(virq);
+ struct irq_data *data = irq_domain_get_irq_data(d, virq);
struct irq_domain_chip_generic *dgc = d->gc;
struct irq_chip_generic *gc;
struct irq_chip_type *ct;
@@ -405,8 +405,7 @@ int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
else
data->mask = 1 << idx;
- irq_set_chip_and_handler(virq, chip, ct->handler);
- irq_set_chip_data(virq, gc);
+ irq_domain_set_info(d, virq, hw_irq, chip, gc, ct->handler, NULL, NULL);
irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
return 0;
}
--
2.3.5
Add support for hierarchy irq domains. This is required to stack
the MSCM interrupt router and the NVIC controller found in Vybrid
SoC.
Signed-off-by: Stefan Agner <[email protected]>
---
drivers/irqchip/Kconfig | 1 +
drivers/irqchip/irq-nvic.c | 28 +++++++++++++++++++++++++++-
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index cc79d2a..ab8de26 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -30,6 +30,7 @@ config ARM_GIC_V3_ITS
config ARM_NVIC
bool
select IRQ_DOMAIN
+ select IRQ_DOMAIN_HIERARCHY
select GENERIC_IRQ_CHIP
config ARM_VIC
diff --git a/drivers/irqchip/irq-nvic.c b/drivers/irqchip/irq-nvic.c
index 4ff0805..5fac910 100644
--- a/drivers/irqchip/irq-nvic.c
+++ b/drivers/irqchip/irq-nvic.c
@@ -49,6 +49,31 @@ nvic_handle_irq(irq_hw_number_t hwirq, struct pt_regs *regs)
handle_IRQ(irq, regs);
}
+static int nvic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs, void *arg)
+{
+ int i, ret;
+ irq_hw_number_t hwirq;
+ unsigned int type = IRQ_TYPE_NONE;
+ struct of_phandle_args *irq_data = arg;
+
+ ret = irq_domain_xlate_onecell(domain, irq_data->np, irq_data->args,
+ irq_data->args_count, &hwirq, &type);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < nr_irqs; i++)
+ irq_map_generic_chip(domain, virq + i, hwirq + i);
+
+ return 0;
+}
+
+static const struct irq_domain_ops nvic_irq_domain_ops = {
+ .xlate = irq_domain_xlate_onecell,
+ .alloc = nvic_irq_domain_alloc,
+ .free = irq_domain_free_irqs_top,
+};
+
static int __init nvic_of_init(struct device_node *node,
struct device_node *parent)
{
@@ -70,7 +95,8 @@ static int __init nvic_of_init(struct device_node *node,
irqs = NVIC_MAX_IRQ;
nvic_irq_domain =
- irq_domain_add_linear(node, irqs, &irq_generic_chip_ops, NULL);
+ irq_domain_add_linear(node, irqs, &nvic_irq_domain_ops, NULL);
+
if (!nvic_irq_domain) {
pr_warn("Failed to allocate irq domain\n");
return -ENOMEM;
--
2.3.5
Support the NVIC interrupt controller as node parent of the MSCM
interrupt router. On the dual-core variants of Vybird (VF6xx), the
NVIC interrupt controller is used by the Cortex-M4. To support
running Linux on this core too, MSCM needs NVIC parent support too.
Signed-off-by: Stefan Agner <[email protected]>
---
drivers/irqchip/irq-vf610-mscm-ir.c | 32 ++++++++++++++++++++++++++------
1 file changed, 26 insertions(+), 6 deletions(-)
diff --git a/drivers/irqchip/irq-vf610-mscm-ir.c b/drivers/irqchip/irq-vf610-mscm-ir.c
index 9521057..40b7d8d 100644
--- a/drivers/irqchip/irq-vf610-mscm-ir.c
+++ b/drivers/irqchip/irq-vf610-mscm-ir.c
@@ -47,6 +47,7 @@ struct vf610_mscm_ir_chip_data {
void __iomem *mscm_ir_base;
u16 cpu_mask;
u16 saved_irsprc[MSCM_IRSPRC_NUM];
+ bool is_nvic;
};
static struct vf610_mscm_ir_chip_data *mscm_ir_data;
@@ -91,6 +92,7 @@ static void vf610_mscm_ir_enable(struct irq_data *data)
{
irq_hw_number_t hwirq = data->hwirq;
struct vf610_mscm_ir_chip_data *chip_data = data->chip_data;
+ struct irq_data *parent = data->parent_data;
u16 irsprc;
irsprc = readw_relaxed(chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
@@ -101,17 +103,25 @@ static void vf610_mscm_ir_enable(struct irq_data *data)
writew_relaxed(chip_data->cpu_mask,
chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
- irq_chip_unmask_parent(data);
+ if (parent->chip->irq_enable)
+ parent->chip->irq_enable(parent);
+ else
+ parent->chip->irq_unmask(parent);
+
}
static void vf610_mscm_ir_disable(struct irq_data *data)
{
irq_hw_number_t hwirq = data->hwirq;
struct vf610_mscm_ir_chip_data *chip_data = data->chip_data;
+ struct irq_data *parent = data->parent_data;
writew_relaxed(0x0, chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
- irq_chip_mask_parent(data);
+ if (parent->chip->irq_disable)
+ parent->chip->irq_disable(parent);
+ else
+ parent->chip->irq_mask(parent);
}
static struct irq_chip vf610_mscm_ir_irq_chip = {
@@ -143,10 +153,17 @@ static int vf610_mscm_ir_domain_alloc(struct irq_domain *domain, unsigned int vi
domain->host_data);
gic_data.np = domain->parent->of_node;
- gic_data.args_count = 3;
- gic_data.args[0] = GIC_SPI;
- gic_data.args[1] = irq_data->args[0];
- gic_data.args[2] = irq_data->args[1];
+
+ if (mscm_ir_data->is_nvic) {
+ gic_data.args_count = 1;
+ gic_data.args[0] = irq_data->args[0];
+ } else {
+ gic_data.args_count = 3;
+ gic_data.args[0] = GIC_SPI;
+ gic_data.args[1] = irq_data->args[0];
+ gic_data.args[2] = irq_data->args[1];
+ }
+
return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_data);
}
@@ -199,6 +216,9 @@ static int __init vf610_mscm_ir_of_init(struct device_node *node,
goto out_unmap;
}
+ if (of_device_is_compatible(domain->parent->of_node, "arm,armv7m-nvic"))
+ mscm_ir_data->is_nvic = true;
+
cpu_pm_register_notifier(&mscm_ir_notifier_block);
return 0;
--
2.3.5
Vybrids has 112 peripherial interrupts which can be routed to the
Cortex-M4's NVIC interrupt controller.
Signed-off-by: Stefan Agner <[email protected]>
---
arch/arm/mm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 16d077e..8eebc0d 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -609,6 +609,7 @@ config CPUV7M_NUM_IRQ
depends on CPU_V7M
default 90 if ARCH_STM32
default 38 if ARCH_EFM32
+ default 112 if SOC_VF610
default 240
help
This option indicates the number of interrupts connected to the NVIC.
--
2.3.5
Add the minimal dependencies required to use the Vybrid PIT
clocksource driver. Those are not part of the SoC dependencies.
Acked-by: Daniel Lezcano <[email protected]>
Signed-off-by: Stefan Agner <[email protected]>
---
drivers/clocksource/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 1c2506f..350e742 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -164,6 +164,8 @@ config FSL_FTM_TIMER
config VF_PIT_TIMER
bool
+ select CLKSRC_MMIO
+ select CLKSRC_OF
help
Support for Period Interrupt Timer on Freescale Vybrid Family SoCs.
--
2.3.5
Remove the needless differences between MMU/!MMU addruart calls.
This allows to use the same addruart macro on SoC level. Useful
for SoC consisting of multiple CPUs with and without MMU such as
Freescale Vybrid.
Signed-off-by: Stefan Agner <[email protected]>
---
arch/arm/include/debug/efm32.S | 2 +-
arch/arm/kernel/debug.S | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/debug/efm32.S b/arch/arm/include/debug/efm32.S
index 2265a19..660fa1e 100644
--- a/arch/arm/include/debug/efm32.S
+++ b/arch/arm/include/debug/efm32.S
@@ -16,7 +16,7 @@
#define UARTn_TXDATA 0x0034
- .macro addruart, rx, tmp
+ .macro addruart, rx, tmp, tmp2
ldr \rx, =(CONFIG_DEBUG_UART_PHYS)
/*
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index 78c91b5..ea9646c 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -35,7 +35,7 @@
#else /* !CONFIG_MMU */
.macro addruart_current, rx, tmp1, tmp2
- addruart \rx, \tmp1
+ addruart \rx, \tmp1, \tmp2
.endm
#endif /* CONFIG_MMU */
--
2.3.5
This introduces a new top level config symbol ARM_SINGLE_ARMV7M
for non-MMU, ARMv7-M platforms. It also support multiple ARMv7-M
platforms in one kernel image since the cores share the same
basic memory layout and interrupt controller. However, this works
only if the combined platforms also have a similar (main) memory
layout.
Signed-off-by: Stefan Agner <[email protected]>
---
arch/arm/Kconfig | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9f1f09a..66e60af 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -323,6 +323,19 @@ config ARCH_MULTIPLATFORM
select SPARSE_IRQ
select USE_OF
+config ARM_SINGLE_ARMV7M
+ bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
+ depends on !MMU
+ select ARCH_WANT_OPTIONAL_GPIOLIB
+ select ARM_NVIC
+ select CLKSRC_OF
+ select COMMON_CLK
+ select CPU_V7M
+ select GENERIC_CLOCKEVENTS
+ select NO_IOPORT_MAP
+ select SPARSE_IRQ
+ select USE_OF
+
config ARCH_REALVIEW
bool "ARM Ltd. RealView family"
select ARCH_WANT_OPTIONAL_GPIOLIB
--
2.3.5
Use the new config symbol ARM_SINGLE_ARMV7M which groups config
symbols used by modern ARMv7-M platforms. It also support multiple
ARMv7-M platforms in one kernel image. However, this only works if
the combined platforms share the same (main) memory layout.
Signed-off-by: Stefan Agner <[email protected]>
---
arch/arm/Kconfig | 28 ++++++++++------------------
arch/arm/configs/efm32_defconfig | 1 +
2 files changed, 11 insertions(+), 18 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 66e60af..9c139fb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -418,24 +418,6 @@ config ARCH_EBSA110
Ethernet interface, two PCMCIA sockets, two serial ports and a
parallel port.
-config ARCH_EFM32
- bool "Energy Micro efm32"
- depends on !MMU
- select ARCH_REQUIRE_GPIOLIB
- select ARM_NVIC
- select AUTO_ZRELADDR
- select CLKSRC_OF
- select COMMON_CLK
- select CPU_V7M
- select GENERIC_CLOCKEVENTS
- select NO_DMA
- select NO_IOPORT_MAP
- select SPARSE_IRQ
- select USE_OF
- help
- Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
- processors.
-
config ARCH_EP93XX
bool "EP93xx-based"
select ARCH_HAS_HOLES_MEMORYMODEL
@@ -982,6 +964,16 @@ source "arch/arm/mach-w90x900/Kconfig"
source "arch/arm/mach-zynq/Kconfig"
+# ARMv7-M architecture
+config ARCH_EFM32
+ bool "Energy Micro efm32"
+ depends on ARM_SINGLE_ARMV7M
+ select ARCH_REQUIRE_GPIOLIB
+ select AUTO_ZRELADDR
+ help
+ Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
+ processors.
+
# Definitions to make life easier
config ARCH_ACORN
bool
diff --git a/arch/arm/configs/efm32_defconfig b/arch/arm/configs/efm32_defconfig
index c4c17e3..e969f78 100644
--- a/arch/arm/configs/efm32_defconfig
+++ b/arch/arm/configs/efm32_defconfig
@@ -16,6 +16,7 @@ CONFIG_EMBEDDED=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
# CONFIG_MMU is not set
+CONFIG_ARM_SINGLE_ARMV7M=y
CONFIG_ARCH_EFM32=y
CONFIG_SET_MEM_PARAM=y
CONFIG_DRAM_BASE=0x88000000
--
2.3.5
This patch allows to build the Kernel for Vybrid (VF6xx) SoC
when ARMv7-M CPU is selected. The resulting image runs on the
secondary Cortex-M4 core. This core has equally access to all
peripherals as the main Cortex-A5 core. However, there is no
resource control mechanism, hence when both cores are used
simultaneously, orthogonal device tree's are required.
The boot CPU is dependent on the SoC variant. The available
boards use mostly variants where the Cortex-A5 is the primary
and hence the boot CPU. Booting the secondary Cortex-M4 CPU
needs SoC specific registers written. There is no in kernel
support for this right now, a external userspace utility
called "m4boot" can be used to boot the kernel:
m4boot xipImage initramfs.cpio.lzo vf610m4-colibri.dtb
Signed-off-by: Stefan Agner <[email protected]>
---
Documentation/devicetree/bindings/arm/fsl.txt | 3 +++
arch/arm/Kconfig.debug | 2 +-
arch/arm/mach-imx/Kconfig | 38 ++++++++++++++++-----------
arch/arm/mach-imx/Makefile.boot | 0
arch/arm/mach-imx/mach-vf610.c | 1 +
5 files changed, 28 insertions(+), 16 deletions(-)
create mode 100644 arch/arm/mach-imx/Makefile.boot
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index a5462b6..2a3ba73 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -81,12 +81,15 @@ Freescale Vybrid Platform Device Tree Bindings
For the Vybrid SoC familiy all variants with DDR controller are supported,
which is the VF5xx and VF6xx series. Out of historical reasons, in most
places the kernel uses vf610 to refer to the whole familiy.
+The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4
+core support.
Required root node compatible property (one of them):
- compatible = "fsl,vf500";
- compatible = "fsl,vf510";
- compatible = "fsl,vf600";
- compatible = "fsl,vf610";
+ - compatible = "fsl,vf610m4";
Freescale LS1021A Platform Device Tree Bindings
------------------------------------------------
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 970de75..2e55557 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -1573,7 +1573,7 @@ config DEBUG_UNCOMPRESS
config UNCOMPRESS_INCLUDE
string
default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || \
- PLAT_SAMSUNG || ARCH_EFM32
+ PLAT_SAMSUNG || ARCH_EFM32 || SOC_VF610
default "mach/uncompress.h"
config EARLY_PRINTK
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index c8dffce..aa8ad4a 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,5 +1,5 @@
menuconfig ARCH_MXC
- bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7
+ bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7 || ARM_SINGLE_ARMV7M
select ARCH_REQUIRE_GPIOLIB
select ARM_CPU_SUSPEND if PM
select CLKSRC_MMIO
@@ -557,9 +557,11 @@ config MACH_VPR200
endif
+comment "Device tree only"
+
if ARCH_MULTI_V7
-comment "Device tree only"
+comment "Cortex-A platforms"
config SOC_IMX5
bool
@@ -629,10 +631,26 @@ config SOC_IMX6SX
help
This enables support for Freescale i.MX6 SoloX processor.
+
+config SOC_LS1021A
+ bool "Freescale LS1021A support"
+ select ARM_GIC
+ select HAVE_ARM_ARCH_TIMER
+ select PCI_DOMAINS if PCI
+ select ZONE_DMA if ARM_LPAE
+
+ help
+ This enable support for Freescale LS1021A processor.
+
+endif
+
+comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms"
+
+if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
+
config SOC_VF610
bool "Vybrid Family VF610 support"
- select IRQ_DOMAIN_HIERARCHY
- select ARM_GIC
+ select ARM_GIC if ARCH_MULTI_V7
select PINCTRL_VF610
select PL310_ERRATA_769419 if CACHE_L2X0
@@ -645,7 +663,7 @@ choice
default VF_USE_ARM_GLOBAL_TIMER
config VF_USE_ARM_GLOBAL_TIMER
- bool "Use ARM Global Timer"
+ bool "Use ARM Global Timer" if ARCH_MULTI_V7
select ARM_GLOBAL_TIMER
select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
help
@@ -659,16 +677,6 @@ choice
endchoice
-config SOC_LS1021A
- bool "Freescale LS1021A support"
- select ARM_GIC
- select HAVE_ARM_ARCH_TIMER
- select PCI_DOMAINS if PCI
- select ZONE_DMA if ARM_LPAE
-
- help
- This enable support for Freescale LS1021A processor.
-
endif
source "arch/arm/mach-imx/devices/Kconfig"
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
new file mode 100644
index 0000000..e69de29
diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c
index 2e7c75b..b20f6c1 100644
--- a/arch/arm/mach-imx/mach-vf610.c
+++ b/arch/arm/mach-imx/mach-vf610.c
@@ -17,6 +17,7 @@ static const char * const vf610_dt_compat[] __initconst = {
"fsl,vf510",
"fsl,vf600",
"fsl,vf610",
+ "fsl,vf610m4",
NULL,
};
--
2.3.5
This adds an initial device tree to run Linux on the Cortex-M4 on
the Vybrid based Colibri VF61 module.
Signed-off-by: Stefan Agner <[email protected]>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/vf610m4-colibri.dts | 99 +++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/vf610m4.dtsi | 50 ++++++++++++++++++
3 files changed, 150 insertions(+)
create mode 100644 arch/arm/boot/dts/vf610m4-colibri.dts
create mode 100644 arch/arm/boot/dts/vf610m4.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a1c776b..3a6ff9f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -309,6 +309,7 @@ dtb-$(CONFIG_SOC_LS1021A) += \
dtb-$(CONFIG_SOC_VF610) += \
vf500-colibri-eval-v3.dtb \
vf610-colibri-eval-v3.dtb \
+ vf610m4-colibri.dtb \
vf610-cosmic.dtb \
vf610-twr.dtb
dtb-$(CONFIG_ARCH_MXS) += \
diff --git a/arch/arm/boot/dts/vf610m4-colibri.dts b/arch/arm/boot/dts/vf610m4-colibri.dts
new file mode 100644
index 0000000..2931a80
--- /dev/null
+++ b/arch/arm/boot/dts/vf610m4-colibri.dts
@@ -0,0 +1,99 @@
+/*
+ * Device tree for Colibri VF61 Cortex-M4 support
+ *
+ * Copyright (C) 2015 Stefan Agner
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "vf610m4.dtsi"
+
+/ {
+ model = "VF610 Cortex-M4";
+ compatible = "fsl,vf610m4";
+
+ chosen {
+ bootargs = "console=ttyLP2,115200 clk_ignore_unused init=/linuxrc rw";
+ linux,stdout-path = "&uart2";
+ };
+
+ memory {
+ reg = <0x8c000000 0x3000000>;
+ };
+};
+
+&gpio0 {
+ status = "disabled";
+};
+
+&gpio1 {
+ status = "disabled";
+};
+
+&gpio2 {
+ status = "disabled";
+};
+
+&gpio3 {
+ status = "disabled";
+};
+
+&gpio4 {
+ status = "disabled";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&iomuxc {
+ vf610-colibri {
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ VF610_PAD_PTD0__UART2_TX 0x21a2
+ VF610_PAD_PTD1__UART2_RX 0x21a1
+ VF610_PAD_PTD2__UART2_RTS 0x21a2
+ VF610_PAD_PTD3__UART2_CTS 0x21a1
+ >;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/vf610m4.dtsi b/arch/arm/boot/dts/vf610m4.dtsi
new file mode 100644
index 0000000..9ffe2eb
--- /dev/null
+++ b/arch/arm/boot/dts/vf610m4.dtsi
@@ -0,0 +1,50 @@
+/*
+ * Device tree for VF6xx Cortex-M4 support
+ *
+ * Copyright (C) 2015 Stefan Agner
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "armv7-m.dtsi"
+#include "vfxxx.dtsi"
+
+&mscm_ir {
+ interrupt-parent = <&nvic>;
+};
--
2.3.5
Add defconfig for Linux on Vybrid (vf610) on the secondary Cortex-
M4 CPU. The use of a XIP image has been tested which needs to be
loaded (e.g. using the custom m4boot loader) to the end of the
available RAM at address 0x8f000000. The Cortex-M4 has a code-alias
which makes sure that the instructions get fetched through the code
bus (alias starts at 0x00800000 => 0x80800000 in system address).
Hence, to get optimal performance, use 0x0f000000 as XIP_PHYS_ADDR.
This address is additionally shifted by the length of the minimal
loader which is inserted by m4boot. Currently, this offset is 0x80.
The standard DRAM base address is configured to 0x8C000000, which
gives the Cortex-M4 48MiB of RAM.
Signed-off-by: Stefan Agner <[email protected]>
---
arch/arm/configs/vf610m4_defconfig | 42 ++++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
create mode 100644 arch/arm/configs/vf610m4_defconfig
diff --git a/arch/arm/configs/vf610m4_defconfig b/arch/arm/configs/vf610m4_defconfig
new file mode 100644
index 0000000..aeb2482
--- /dev/null
+++ b/arch/arm/configs/vf610m4_defconfig
@@ -0,0 +1,42 @@
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZ4 is not set
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_MMU is not set
+CONFIG_ARM_SINGLE_ARMV7M=y
+CONFIG_ARCH_MXC=y
+CONFIG_SOC_VF610=y
+CONFIG_SET_MEM_PARAM=y
+CONFIG_DRAM_BASE=0x8c000000
+CONFIG_FLASH_MEM_BASE=0x8f000000
+CONFIG_FLASH_SIZE=0x01000000
+CONFIG_CMDLINE="console=/dev/ttyLP2"
+CONFIG_XIP_KERNEL=y
+CONFIG_XIP_PHYS_ADDR=0x0f000080
+CONFIG_BINFMT_FLAT=y
+CONFIG_BINFMT_ZFLAT=y
+CONFIG_BINFMT_SHARED_FLAT=y
+# CONFIG_SUSPEND is not set
+# CONFIG_UEVENT_HELPER is not set
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+# CONFIG_ALLOW_DEV_COREDUMP is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=4
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_MFD_SYSCON=y
+# CONFIG_HID is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_FTRACE is not set
--
2.3.5
Hi Stefan,
2015-04-09 22:04 GMT+02:00 Stefan Agner <[email protected]>:
> In this fifth revision the patchset moves away from the idea
> including ARMv7-M platforms into ARCH_MULTIPLATFORM, but
> instead adds a new top-level config symbol ARM_SINGLE_ARMV7M
> Patch 7 adds this new config symbol while patch 8 alters the
> existing ARMv7-M platform ARCH_EFM32 to use ARM_SINGLE_ARMV7M.
> I chose to move the config symbol of the ARMv7-M specific
> architectures (ARCH_EFM32 at that point) below the multiarch
> includes. I think it is a good idea to keep them together, but
> I'm not sure if this is an appropriate place. The architecture
> which Vybrid is depending on, ARCH_MXC, is not also selectable
> when ARM_SINGLE_ARMV7M is selected.
>
> Since v3, this patchset does not contain the interrupt router
> driver anymore (MSCM IR). The driver has been merged inbetween:
> https://lkml.org/lkml/2015/3/8/6
>
> This patchset extends the NVIC driver to support irq domain
> hierarchy and the MSCM IR driver to support NVIC as a parent
> irq controller.
>
> The patchset has proven to be working on the Cortex-M4 of the
> Vybrid SoC using a Colibri VF61 module.
>
> Note: This patchset has dependencies on "ARM: ARMv7-M: Enlarge
> vector table up to 256 entries" (Maxime Coquelin) and the
I just submitted the patch to Russell's patch tracking system:
http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=8340/1
Kind regards,
Maxime
Just two whitespace nits. (Please don't tell anyone, I'm a bit
embarrassed that I even spot them, let alone that I comment on them.)
On Thu, 2015-04-09 at 22:04 +0200, Stefan Agner wrote:
> --- a/arch/arm/Kconfig.debug
> +++ b/arch/arm/Kconfig.debug
> @@ -629,10 +631,26 @@ config SOC_IMX6SX
> help
> This enables support for Freescale i.MX6 SoloX processor.
>
> +
This second empty line is unneeded.
> +config SOC_LS1021A
> + bool "Freescale LS1021A support"
> + select ARM_GIC
> + select HAVE_ARM_ARCH_TIMER
> + select PCI_DOMAINS if PCI
> + select ZONE_DMA if ARM_LPAE
> +
Please drop this empty line.
> + help
> + This enable support for Freescale LS1021A processor.
> +
> +endif
> +
> +comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms"
> +
> +if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
> +
> config SOC_VF610
> bool "Vybrid Family VF610 support"
> - select IRQ_DOMAIN_HIERARCHY
> - select ARM_GIC
> + select ARM_GIC if ARCH_MULTI_V7
> select PINCTRL_VF610
> select PL310_ERRATA_769419 if CACHE_L2X0
>
Thanks,
Paul Bolle
Stefan,
On Thu, Apr 09, 2015 at 10:04:04PM +0200, Stefan Agner wrote:
> Stefan Agner (11):
> genirq: generic chip: support hierarchy domain
> irqchip: nvic: support hierarchy irq domain
> irqchip: vf610-mscm: support NVIC parent
I've applied patches 1 to 3 onto irqchip/vybrid. And will merge them in for
-next testing. We don't know if v4.0 is dropping on Sunday or not. If
it doesn't, we should be able to get these in for v4.1. Otherwise,
they'll have to wait for the next cycle.
thx,
Jason.
On Thursday 09 April 2015, Stefan Agner wrote:
> In this fifth revision the patchset moves away from the idea
> including ARMv7-M platforms into ARCH_MULTIPLATFORM, but
> instead adds a new top-level config symbol ARM_SINGLE_ARMV7M
> Patch 7 adds this new config symbol while patch 8 alters the
> existing ARMv7-M platform ARCH_EFM32 to use ARM_SINGLE_ARMV7M.
> I chose to move the config symbol of the ARMv7-M specific
> architectures (ARCH_EFM32 at that point) below the multiarch
> includes. I think it is a good idea to keep them together, but
> I'm not sure if this is an appropriate place. The architecture
> which Vybrid is depending on, ARCH_MXC, is not also selectable
> when ARM_SINGLE_ARMV7M is selected.
It's a shame we didn't manage to pull these in in time for 4.1,
but while the patches look ok to me, they came a little late,
and it's not clear to me how we should maintain that platform.
You have lots of people on 'To:' for the emails, which is always
confusing. My preferred way of merging these in 4.2 would be for
you to send the patches to the imx maintainers so they can
pick them up and send them to [email protected].
Arnd