The datasheet for the 334x PHY mentions that a reset can be performed:
"... by bringing the pin low for a minimum of 1 microsecond and
then high."
A delay of 5ms to implement that seems overly long, so reduce it to
just 1us.
As for the delay after reset, the datasheet only mentioned that the
chip will assert the DIR output. 1ms seems like a safe time to wait
for that to happen, so no change there.
Signed-off-by: Mike Looijmans <[email protected]>
---
drivers/usb/chipidea/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index e970863..c865abe 100644
--- a/drivers/usb/chipidea/core.c
+++ b/drivers/usb/chipidea/core.c
@@ -664,7 +664,7 @@ static int ci_hdrc_create_ulpi_phy(struct device *dev, struct ci_hdrc *ci)
dev_err(dev, "Failed to request ULPI reset gpio: %d\n", ret);
return ret;
}
- msleep(5);
+ udelay(1);
gpio_set_value_cansleep(reset_gpio, 1);
msleep(1);
}
--
1.9.1
The datasheet for the USB343x PHY mentions a 50ms wait time before
reading back the ID bit after enabling the internal pull-up or a
reset:
"To monitor the status of the ID pin, the Link activates the IdPullup
bit in the OTG Control register, waits 50mS and then reads the status
of the IdGnd bit in the USB Interrupt Status register."
Implement this by adding a 50ms sleep at the only point in the code
where the ID status is being read without IRQ trigger.
When starting the board with a USB cable connected to a PC, the
system would activate host mode, then in ~20ms get an ID IRQ and
attempt to switch to gadget mode. This then failed because the
VBUS will not drop to zero (because the host is supplying it).
After this patch, the system starts up correctly and selects
gadget mode immediately, and the USB link works. It also fixes
the issue that the VBUS supply was being activated while already
being supplied from the host PC.
Signed-off-by: Mike Looijmans <[email protected]>
---
drivers/usb/chipidea/core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index c865abe..4c6cf48 100644
--- a/drivers/usb/chipidea/core.c
+++ b/drivers/usb/chipidea/core.c
@@ -801,6 +801,7 @@ static int ci_hdrc_probe(struct platform_device *pdev)
if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
if (ci->is_otg) {
+ msleep(50); /* Datasheet: Wait 50ms to read ID */
ci->role = ci_otg_role(ci);
/* Enable ID change irq */
hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
--
1.9.1
On Fri, Jun 26, 2015 at 03:47:03PM +0200, Mike Looijmans wrote:
> The datasheet for the 334x PHY mentions that a reset can be performed:
> "... by bringing the pin low for a minimum of 1 microsecond and
> then high."
> A delay of 5ms to implement that seems overly long, so reduce it to
> just 1us.
> As for the delay after reset, the datasheet only mentioned that the
> chip will assert the DIR output. 1ms seems like a safe time to wait
> for that to happen, so no change there.
>
> Signed-off-by: Mike Looijmans <[email protected]>
> ---
> drivers/usb/chipidea/core.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
> index e970863..c865abe 100644
> --- a/drivers/usb/chipidea/core.c
> +++ b/drivers/usb/chipidea/core.c
> @@ -664,7 +664,7 @@ static int ci_hdrc_create_ulpi_phy(struct device *dev, struct ci_hdrc *ci)
> dev_err(dev, "Failed to request ULPI reset gpio: %d\n", ret);
> return ret;
> }
> - msleep(5);
> + udelay(1);
> gpio_set_value_cansleep(reset_gpio, 1);
> msleep(1);
> }
> --
> 1.9.1
>
We have no such function at mainline code.
--
Best Regards,
Peter Chen
On Fri, Jun 26, 2015 at 03:47:04PM +0200, Mike Looijmans wrote:
> The datasheet for the USB343x PHY mentions a 50ms wait time before
> reading back the ID bit after enabling the internal pull-up or a
> reset:
> "To monitor the status of the ID pin, the Link activates the IdPullup
> bit in the OTG Control register, waits 50mS and then reads the status
> of the IdGnd bit in the USB Interrupt Status register."
> Implement this by adding a 50ms sleep at the only point in the code
> where the ID status is being read without IRQ trigger.
This 50mS delay is dedicated for this PHY, you may add it at the
PHY driver.
>
> When starting the board with a USB cable connected to a PC, the
> system would activate host mode, then in ~20ms get an ID IRQ and
> attempt to switch to gadget mode. This then failed because the
> VBUS will not drop to zero (because the host is supplying it).
>
> After this patch, the system starts up correctly and selects
> gadget mode immediately, and the USB link works. It also fixes
> the issue that the VBUS supply was being activated while already
> being supplied from the host PC.
>
> Signed-off-by: Mike Looijmans <[email protected]>
> ---
> drivers/usb/chipidea/core.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
> index c865abe..4c6cf48 100644
> --- a/drivers/usb/chipidea/core.c
> +++ b/drivers/usb/chipidea/core.c
> @@ -801,6 +801,7 @@ static int ci_hdrc_probe(struct platform_device *pdev)
>
> if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
> if (ci->is_otg) {
> + msleep(50); /* Datasheet: Wait 50ms to read ID */
> ci->role = ci_otg_role(ci);
> /* Enable ID change irq */
> hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
> --
> 1.9.1
>
--
Best Regards,
Peter Chen
From: Peter Chen
> Sent: 30 June 2015 03:06
> On Fri, Jun 26, 2015 at 03:47:03PM +0200, Mike Looijmans wrote:
> > The datasheet for the 334x PHY mentions that a reset can be performed:
> > "... by bringing the pin low for a minimum of 1 microsecond and
> > then high."
> > A delay of 5ms to implement that seems overly long, so reduce it to
> > just 1us.
> > As for the delay after reset, the datasheet only mentioned that the
> > chip will assert the DIR output. 1ms seems like a safe time to wait
> > for that to happen, so no change there.
> >
> > Signed-off-by: Mike Looijmans <[email protected]>
> > ---
> > drivers/usb/chipidea/core.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
> > index e970863..c865abe 100644
> > --- a/drivers/usb/chipidea/core.c
> > +++ b/drivers/usb/chipidea/core.c
> > @@ -664,7 +664,7 @@ static int ci_hdrc_create_ulpi_phy(struct device *dev, struct ci_hdrc *ci)
> > dev_err(dev, "Failed to request ULPI reset gpio: %d\n", ret);
> > return ret;
> > }
> > - msleep(5);
> > + udelay(1);
If the spec says 1us I'd delay for longer just to make sure.
And add a comment saying that the reset needs to be 1us long.
David
On 02-07-15 11:39, David Laight wrote:
> From: Peter Chen
>> Sent: 30 June 2015 03:06
>> On Fri, Jun 26, 2015 at 03:47:03PM +0200, Mike Looijmans wrote:
>>> The datasheet for the 334x PHY mentions that a reset can be performed:
>>> "... by bringing the pin low for a minimum of 1 microsecond and
>>> then high."
>>> A delay of 5ms to implement that seems overly long, so reduce it to
>>> just 1us.
>>> As for the delay after reset, the datasheet only mentioned that the
>>> chip will assert the DIR output. 1ms seems like a safe time to wait
>>> for that to happen, so no change there.
>>>
>>> Signed-off-by: Mike Looijmans <[email protected]>
>>> ---
>>> drivers/usb/chipidea/core.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
>>> index e970863..c865abe 100644
>>> --- a/drivers/usb/chipidea/core.c
>>> +++ b/drivers/usb/chipidea/core.c
>>> @@ -664,7 +664,7 @@ static int ci_hdrc_create_ulpi_phy(struct device *dev, struct ci_hdrc *ci)
>>> dev_err(dev, "Failed to request ULPI reset gpio: %d\n", ret);
>>> return ret;
>>> }
>>> - msleep(5);
>>> + udelay(1);
>
> If the spec says 1us I'd delay for longer just to make sure.
> And add a comment saying that the reset needs to be 1us long.
Why? It's not as if the chip would reset any "better" if you pull the line
longer. For some of these USB PHYs, the internal regulators and other analog
parts will be disabled as well and the longer you keep it in reset, the longer
it will take the device to start back up again.
The 1us value already takes into account a generous compensation for
temperature and other factors, and probably the reset will work just fine even
if you only use half the time.
Even if I'd agree with you here, I think you'll also have to admit that 5000x
the value in the datasheet might be a bit over the top.
M.