On Tue, Dec 15, 2015 at 04:37:12PM +0800, Xiubo Li wrote:
> On 15/12/2015 01:57, Mark Brown wrote:
> >On Mon, Dec 14, 2015 at 03:14:34PM +0800, Xiubo Li wrote:
> >I'm guessing for your particular register maps the performance isn't too
> >big an issue... do you have any numbers for how much space you're
> >saving overall?
> Not yet, but maybe in the future we could see a larger register
> striding, like 32 for MMIO using flat cache.
OK, well I'd like to se
> >Is it worth finding a way to make this possible to
> >enable on maps that benefit?
> I'm thinking to use the bit rotation to improve the performance of
> the whole regmap.
> like:
> if(reg % reg_stride) --> if(!IS_ALIGNED(reg, reg_stride))
> ...
> index = reg / reg_stride; --> index = reg >> reg_stride_order;
>
> And do you have any comment and suggestion for the above?
I think we'll need to continue supporting non power of two strides so
an unconditional conversion to shifts might be an issue - some weird DSP
probably does that.
On Fri, Dec 18, 2015 at 04:59:38PM +0800, [email protected] wrote:
> > I think we'll need to continue supporting non power of two strides so
> > an unconditional conversion to shifts might be an issue - some weird DSP
> > probably does that.
> Yes, agreed.
> IMO this won't happen to MMIO, and for the device using MMIO the
> register strides should equal to power of two.
> Are there some cases I have met?
DSPs exposed via I2C and SPI are the main things I'm worried about.
It's fairly common for DSPs to have unusual word sizes including things
like three bytes.
On 31/12/2015 01:58, Mark Brown wrote:
> On Fri, Dec 18, 2015 at 04:59:38PM +0800, [email protected] wrote:
>
>>> I think we'll need to continue supporting non power of two strides so
>>> an unconditional conversion to shifts might be an issue - some weird DSP
>>> probably does that.
>
>> Yes, agreed.
>
>> IMO this won't happen to MMIO, and for the device using MMIO the
>> register strides should equal to power of two.
>
>> Are there some cases I have met?
>
> DSPs exposed via I2C and SPI are the main things I'm worried about.
> It's fairly common for DSPs to have unusual word sizes including things
> like three bytes.
>
Yes, if so, for this case the non power of two strides should be still
supported.
Thanks for your promotion, and I will think over of this carefully.
BRs
Xiubo Li